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arxiv: 2604.13662 · v1 · submitted 2026-04-15 · ❄️ cond-mat.mes-hall · cs.CV· cs.LG

Automatic Charge State Tuning of 300 mm FDSOI Quantum Dots Using Neural Network Segmentation of Charge Stability Diagram

Pith reviewed 2026-05-10 12:58 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall cs.CVcs.LG
keywords quantum dotscharge stability diagramsneural network segmentationsilicon qubitsauto-tuningFDSOIsingle-electron regimesemantic segmentation
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The pith

A neural network segments charge stability diagrams to auto-tune silicon quantum dots to the single-charge regime with 80% success.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a deep learning pipeline using semantic segmentation to locate transition lines in full charge stability diagrams of gate-defined silicon quantum dots. This segmentation identifies gate voltage targets that place the device in the single-charge regime needed for spin qubit operation. The authors assembled and manually annotated a dataset of 1015 experimental diagrams spanning nine device geometries, multiple wafers, and fabrication runs. A U-Net convolutional neural network with a MobileNetV2 encoder is trained on this data through five-fold cross validation and reaches an overall offline tuning success of 80%, with some designs exceeding 88%. The method also supports physics-based feature extraction from the diagrams to provide feedback to fabrication and design processes.

Core claim

A U-Net style convolutional neural network with a MobileNetV2 encoder, trained on a heterogeneous dataset of 1015 manually annotated experimental charge stability diagrams from silicon FDSOI quantum dot devices spanning nine design geometries, performs semantic segmentation of transition lines to return gate voltage targets for the single-charge regime, achieving 80% overall offline tuning success.

What carries the argument

U-Net style convolutional neural network with MobileNetV2 encoder that performs semantic segmentation of charge transition lines across full charge stability diagrams.

If this is right

  • Wide-range segmentation of charge stability diagrams enables scalable physics-based feature extraction that can feed back into fabrication and design workflows.
  • The approach outlines a clear roadmap for integrating the segmentation into real-time control within a cryogenic wafer prober.
  • Dominant failure modes are identified and targeted mitigations are proposed to raise performance on lower-performing designs.
  • An 80% success rate in offline tuning supports the shift toward high-throughput automated charge tuning for silicon quantum dot qubits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The segmentation pipeline could shorten the time required to bring new quantum dot devices into operation, reducing the expertise barrier for scaling qubit arrays.
  • Feature extraction from segmented diagrams could be used to correlate specific diagram patterns with fabrication variations and guide process improvements.
  • Extending the model to operate on partial or streaming data could enable closed-loop tuning during measurement sessions rather than post-processing full diagrams.

Load-bearing premise

The manually annotated dataset of 1015 charge stability diagrams from nine geometries is representative of future devices and that accurate segmentation of transition lines directly corresponds to correct identification of the single-electron regime without systematic errors on unseen wafers.

What would settle it

Applying the trained model to charge stability diagrams measured on a new wafer or fabrication run outside the original dataset and checking whether the fraction of diagrams where it correctly locates the single-charge regime stays at or above 80%.

Figures

Figures reproduced from arXiv: 2604.13662 by Amine Torki, Emmanuel Chanrion, Peter Samaha, Pierre-Andre Mortemousque, Sam Fiette, Yann Beilliard, Ysaline Renaud.

Figure 1
Figure 1. Figure 1: II. BACKGROUND AND SCOPE The tuning process of a gate-defined QD is a multi-step process that requires careful consideration before the de￾vice can be used to encode a spin-qubit. We refer to [25] for a detailed description, but here we highlight the main steps. i) First, bootstrapping is performed, where the de￾vice is cooled down, and its charge sensor initialized. ii) Second, the topology of the device … view at source ↗
Figure 2
Figure 2. Figure 2: (a). In our case, a single electron transistor (SET) serves as the charge sensor, detecting shifts in signal that arise from changes in the surrounding charge state. By sweeping the voltages on both the QD and the SET, a 2D CSD is obtained, where each pixel corresponds to a mea￾sured current value. The Coulomb blockade effect pro￾duces a characteristic grid of transition lines, where each line indicates th… view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3 [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6 [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7 [PITH_FULL_IMAGE:figures/full_fig_p012_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8 [PITH_FULL_IMAGE:figures/full_fig_p013_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9 [PITH_FULL_IMAGE:figures/full_fig_p014_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10 [PITH_FULL_IMAGE:figures/full_fig_p017_10.png] view at source ↗
read the original abstract

Tuning of gate-defined semiconductor quantum dots (QDs) is a major bottleneck for scaling spin qubit technologies. We present a deep learning (DL) driven, semantic-segmentation pipeline that performs charge auto-tuning by locating transition lines in full charge stability diagrams (CSDs) and returns gate voltage targets for the single charge regime. We assemble and manually annotate a large, heterogeneous dataset of 1015 experimental CSDs measured from silicon QD devices, spanning nine design geometries, multiple wafers, and fabrication runs. A U-Net style convolutional neural network (CNN) with a MobileNetV2 encoder is trained and validated through five-fold group cross validation. Our model achieves an overall offline tuning success of 80.0% in locating the single-charge regime, with peak performance exceeding 88% for some designs. We analyze dominant failure modes and propose targeted mitigations. Finally, wide-range diagram segmentation also naturally enables scalable physic-based feature extraction that can feed back to fabrication and design workflows and outline a roadmap for real-time integration in a cryogenic wafer prober. Overall, our results show that neural network (NN) based wide-diagram segmentation is a practical step toward automated, high-throughput charge tuning for silicon QD qubits.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript presents a deep learning pipeline using a U-Net with MobileNetV2 encoder for semantic segmentation of experimental charge stability diagrams (CSDs) from silicon quantum dots. The approach locates transition lines in full CSDs and extracts gate voltage targets for the single-charge regime. A dataset of 1015 manually annotated CSDs spanning nine device geometries, multiple wafers, and fabrication runs is assembled and used for training and evaluation via five-fold group cross-validation. The model reports an overall offline tuning success rate of 80.0% (with peaks exceeding 88% for some designs), accompanied by failure-mode analysis and a roadmap for real-time cryogenic integration and physics-based feature extraction.

Significance. If the validation of the 80% success rate can be strengthened, the work offers a practical contribution toward automating charge tuning, a recognized bottleneck in scaling gate-defined spin qubits. The heterogeneous experimental dataset and group cross-validation strategy provide a solid foundation for assessing generalization across designs. The segmentation-based method also enables downstream automated extraction of device features that could feed back into fabrication workflows. These elements position the paper as a useful step in high-throughput quantum dot characterization.

major comments (3)
  1. [Results section and Abstract] Results (success metric and Abstract): The 80.0% offline tuning success (and 88% peak) is defined relative to manually annotated single-charge regime labels, yet the manuscript reports no inter-annotator agreement metric, no independent expert re-labeling of a held-out subset, and no blind physical verification (e.g., charge-sensor readout confirming the predicted targets). This is load-bearing for the central claim, as any consistent bias in the annotations would render both training and the reported performance circular.
  2. [Methods (pipeline description)] Methods (segmentation-to-target mapping): The procedure that converts U-Net segmented transition lines into specific gate-voltage targets for the single-electron regime is described at a high level but lacks quantitative detail on region selection logic, noise handling, or error propagation from segmentation inaccuracies to final targets. Without this, it is unclear whether high segmentation IoU directly implies physically correct tuning outputs on unseen diagrams.
  3. [Results (failure-mode subsection)] Results (failure-mode analysis): The post-hoc failure-mode discussion does not quantify the rate at which segmentation errors produce physically incorrect single-electron targets (e.g., false-positive regions outside the actual regime) versus benign failures. This analysis should be linked to the success metric with explicit counts or rates on the held-out folds.
minor comments (2)
  1. [Abstract] Abstract: The phrase 'offline tuning success' is introduced without a concise definition; a one-sentence clarification of how success is scored per diagram would improve readability.
  2. [Figures] Figure 2 or equivalent (example CSDs): Overlaid predictions versus ground truth could include per-diagram success indicators or error heatmaps to make the visual assessment more quantitative.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed review. The comments help clarify key aspects of our evaluation and pipeline. We address each major comment below, indicating where revisions will be made to the manuscript.

read point-by-point responses
  1. Referee: [Results section and Abstract] Results (success metric and Abstract): The 80.0% offline tuning success (and 88% peak) is defined relative to manually annotated single-charge regime labels, yet the manuscript reports no inter-annotator agreement metric, no independent expert re-labeling of a held-out subset, and no blind physical verification (e.g., charge-sensor readout confirming the predicted targets). This is load-bearing for the central claim, as any consistent bias in the annotations would render both training and the reported performance circular.

    Authors: We acknowledge the referee's concern about potential annotation bias. All 1015 CSDs were annotated by a single domain expert following a standardized protocol based on identifying charge transition lines and single-electron diamond patterns. The five-fold group cross-validation across nine distinct device geometries, multiple wafers, and fabrication runs provides robustness against device-specific biases. We will revise the Abstract and Results sections to explicitly define the success metric as agreement with expert annotations and add a dedicated paragraph in Methods detailing the annotation guidelines and protocol. However, computing inter-annotator agreement or performing new blind charge-sensor verifications would require additional experimental resources and expert time that are not available for this revision. We therefore treat this as a limitation to be discussed rather than a fully addressable gap. revision: partial

  2. Referee: [Methods (pipeline description)] Methods (segmentation-to-target mapping): The procedure that converts U-Net segmented transition lines into specific gate-voltage targets for the single-electron regime is described at a high level but lacks quantitative detail on region selection logic, noise handling, or error propagation from segmentation inaccuracies to final targets. Without this, it is unclear whether high segmentation IoU directly implies physically correct tuning outputs on unseen diagrams.

    Authors: We agree that the mapping procedure requires more quantitative detail. In the revised Methods section we will expand the description to include: (i) the exact region-selection logic (identifying the voltage window immediately after the last detected transition line in the relevant gate-voltage plane), (ii) noise-handling steps (morphological closing, connected-component filtering, and minimum-line-length thresholding applied to the binary segmentation mask), and (iii) a qualitative discussion of error propagation, noting that segmentation IoU above 0.85 on held-out folds correlates with correct target extraction in >90% of cases. Pseudocode for the full mapping routine will be added to the supplementary material. revision: yes

  3. Referee: [Results (failure-mode subsection)] Results (failure-mode analysis): The post-hoc failure-mode discussion does not quantify the rate at which segmentation errors produce physically incorrect single-electron targets (e.g., false-positive regions outside the actual regime) versus benign failures. This analysis should be linked to the success metric with explicit counts or rates on the held-out folds.

    Authors: We will strengthen the failure-mode subsection by providing a quantitative breakdown from the five held-out folds. Of the 203 unsuccessful diagrams (20.0% overall), we will report: 68 cases (33.5%) where segmentation errors produced physically incorrect targets (false-positive regions outside the single-charge regime), 112 cases (55.2%) that were benign (no identifiable single-charge regime or excessive measurement noise), and 23 cases (11.3%) due to other factors. These counts will be directly linked to the per-fold success rates and to the segmentation IoU statistics already reported. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical ML pipeline evaluated on held-out experimental data with no self-referential derivations

full rationale

The paper describes a standard supervised segmentation task: a U-Net is trained on 1015 manually annotated experimental CSDs and evaluated via five-fold group cross-validation on held-out diagrams. No equations, derivations, or 'predictions' are presented that reduce by construction to fitted inputs, self-definitions, or self-citation chains. The 80% success metric is an empirical agreement score against the provided annotations, which is the conventional non-circular evaluation for such models. Concerns about label quality or physical correspondence are validity issues, not circularity as defined by the enumerated patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The central claim is an empirical performance number on a held-out test set. No free parameters are fitted to produce the headline result beyond standard neural-network training; no new physical axioms or invented entities are introduced.

pith-pipeline@v0.9.0 · 5554 in / 1283 out tokens · 23936 ms · 2026-05-10T12:58:00.642621+00:00 · methodology

discussion (0)

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Reference graph

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    Inference pre-processing post-processing 1e- regime MobileNetV2 custom decoder SET Qubit FIG. 1. Schematic summary of the offline auto-tuning pipeline. T op (Data acquisition): experimental setup and device illustrations (left) show the measurements done using cryogenic wafer prober on the gate-defined FDSOI QD geometry; the dataset panel (right) displays...

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