Paper Citation Record · LEDGER

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

As of 31 July 2026, this Paper Citation Record lists 31 of 31 outbound references and 0 inbound Pith citation observations for arXiv:2604.23602.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2604.23602 v1

Coverage vector

measured 31 of 31 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-05-08T05:19:55.032967Z

measured 31 of 31 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-07-31T06:34:12.847434+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

31 of 31 outbound references displayed

verified exact13
verified fuzzy15
unresolved1
parse uncertain0
malformed identifier0
metadata mismatch2

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 2d8994a3-1d8e-4cf6-b9e4-33be4a3df1eb · outbound

This paper cites Deeprtl: Bridging verilog understanding and generation with a unified representation model.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Deeprtl: Bridging verilog understanding and generation with a unified representation model

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.651069Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 1cb90b7b-aad0-4911-b65a-b0f69acb6c37 · outbound

This paper cites Betterv: Controlled verilog generation with discriminative guidance.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Betterv: Controlled verilog generation with discriminative guidance

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.604010Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation b20746bb-c2d5-450a-aff6-f90c945be39b · outbound

This paper cites HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

Reference 3

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.856474Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 0144fa8c-658c-4cb8-ad85-52db590f4abc · outbound

This paper cites Hivegen–hierarchical llm-based verilog generation for scalable chip design.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Hivegen–hierarchical llm-based verilog generation for scalable chip design

Reference 4

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.703917Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 4f221e8d-fdde-4f56-99b0-fab2017d583c · outbound

This paper cites LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models

Reference 5

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.810534Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation d1251b26-f2b7-43a6-bf43-f91a25a5ae7e · outbound

This paper cites Verigen: A large language model for verilog code generation.ACM Transactions on Design Automation of Electronic Systems, 29(3):1–31.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Verigen: A large language model for verilog code generation.ACM Transactions on Design Automation of Electronic Systems, 29(3):1–31

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.600135Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation f321bd89-4314-46b0-b4da-e57a9998c89c · outbound

This paper cites LLM-Aided Efficient Hardware Design Automation.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog LLM-Aided Efficient Hardware Design Automation

Reference 7

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.827210Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation c60c5277-9a4e-45e9-9f56-2c4313d5b00f · outbound

This paper cites MAGE: A Multi-Agent Engine for Automated RTL Code Generation.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog MAGE: A Multi-Agent Engine for Automated RTL Code Generation

Reference 8

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.786389Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 0b422b51-48fe-4bb4-b509-f16ba569fca3 · outbound

This paper cites Codev: Empowering llms with hdl generation through multi-level summarization.IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Codev: Empowering llms with hdl generation through multi-level summarization.IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.639814Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 1f92ed4d-c71b-4d86-bd3b-a53e8922a7b4 · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T21:31:14.800195Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation ff17a1cf-b875-4f35-bb50-3bfb704839a7 · outbound

This paper cites A multi-expert large language model architecture for verilog code generation.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog A multi-expert large language model architecture for verilog code generation

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.596233Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation a6affd56-9c68-43d1-880f-f2ab95791147 · outbound

This paper cites CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 12

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.713384Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 4e85bedf-00d9-4f0f-996c-670eb06078e6 · outbound

This paper cites Hdlforge: A two-stage multi-agent framework for efficient verilog code generation with adaptive model escalation.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Hdlforge: A two-stage multi-agent framework for efficient verilog code generation with adaptive model escalation

Reference 13

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.848632Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 1fa9fa57-ca4b-4109-aaa3-5ab713b792b0 · outbound

This paper cites Optimizing urban mobility through complex network analysis and big data from smart cards.IoT, 6(3):44.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Optimizing urban mobility through complex network analysis and big data from smart cards.IoT, 6(3):44

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.628465Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 5243de8e-977e-42d5-b81e-a56b5a709226 · outbound

This paper cites an unresolved cited work.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Unresolved cited work

Reference 15

Resolution: unresolved; raw_fallback, observed 2026-05-26T19:57:56.624349Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation b766bd0e-9a23-4b22-a50c-0337ecdfb65f · outbound

This paper cites OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 16

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.694367Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 3ad2f15a-279c-4cc0-bab4-4c2af4edd7bd · outbound

This paper cites Masterrtl: A pre-synthesis ppa estimation framework for any rtl design.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Masterrtl: A pre-synthesis ppa estimation framework for any rtl design

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.632370Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 2363c73f-74f4-4696-aaba-22ea52cffaee · outbound

This paper cites Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.636109Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 8a1d306b-8cb1-4dba-9b8a-3f9a11025711 · outbound

This paper cites Icd 2 s: A hybrid ising- classical-machines data-driven qubo solver method.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Icd 2 s: A hybrid ising- classical-machines data-driven qubo solver method

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.643302Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation a2f76c5a-f05f-4bde-92ea-e8b6dd13f0e8 · outbound

This paper cites MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications

Reference 20

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.755143Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 6ca5a29d-24e9-486c-b236-8f59dddd4174 · outbound

This paper cites Llsm: Llm-enhanced logic synthesis model with eda-guided cot prompting, hybrid embedding and aig-tailored acceleration.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Llsm: Llm-enhanced logic synthesis model with eda-guided cot prompting, hybrid embedding and aig-tailored acceleration

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.647472Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 7a34d4d0-50a2-42a0-92af-b441ef1eafa3 · outbound

This paper cites CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Reference 22

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.818923Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation ce11a261-9f85-4218-bcff-99d800ea6796 · outbound

This paper cites DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis

Reference 23

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.683806Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 1e4b88b1-3cdf-46db-a549-2e9bc5c505cf · outbound

This paper cites Rocketppa: Ultra-fast llm- based ppa estimator at code-level abstraction.arXiv e-prints, pages arXiv–2503.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Rocketppa: Ultra-fast llm- based ppa estimator at code-level abstraction.arXiv e-prints, pages arXiv–2503

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.617183Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 5180193d-38cd-4b3a-b796-d1b637843f21 · outbound

This paper cites Pyranet: A multi-layered hierarchical dataset for verilog.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Pyranet: A multi-layered hierarchical dataset for verilog

Reference 25

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.736356Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 2a545c0c-ec5a-4c9b-bf23-354d6fd1513c · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Verilogeval: Evaluating large language models for verilog code generation

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.621041Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 7f536603-d665-43f5-9f41-148c50e3aa12 · outbound

This paper cites The Llama 3 Herd of Models.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog The Llama 3 Herd of Models

Reference 27

Resolution: metadata mismatch; local_arxiv, observed 2026-05-11T21:31:14.832852Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation f38035a8-7eec-4aa1-b707-822922526a78 · outbound

This paper cites DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning

Reference 28

Resolution: verified exact; local_arxiv, observed 2026-05-11T21:31:14.774736Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 2756f2cb-abb8-4932-87cb-8b326d0c6494 · outbound

This paper cites Nangate open cell library 45nm.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Nangate open cell library 45nm

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.613619Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 2c04fea9-3d26-41fa-9c23-52830029d0cb · outbound

This paper cites Martins, J.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Martins, J

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.610355Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Observation 0119a209-d3a4-499d-bc01-1af50ef601bc · outbound

This paper cites Vashishtha, M.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog Vashishtha, M

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-05-26T19:57:56.607174Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-07-31T06:34:12.847434+00:00.

Pith citing papers

No inbound Pith citation observations are available.