REVIEW 2 major objections 1 minor 6 references
Impact of Surface Treatment on Noise in PL-Measurements of Silicon Vacancies in 4H-SiC Lateral pin-Diodes
T0 review · 2 major / 1 minor · reviewed 2026-06-30 · grok-4.3
Pith's one-line read Surface treatments raise signal-to-noise ratios for silicon vacancy emitters in 4H-SiC pin-diodes by factors of 15 to 50.
desk verdict The paper shows concrete SNR gains from NO-annealed oxides and RIE+ALE in SiC pin-diodes with V_Si centers, but the gains are not clearly isolated from possible differences in emitter depth or measurement conditions. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The selectively etched optical window integrated into lateral pin-diodes, paired with nitrogen-monoxide-annealed thermal oxides and atomic layer etching for surface preparation.
What would settle it
A direct comparison of photoluminescence signal-to-noise ratios in otherwise identical pin-diodes fabricated with and without the NO annealing and ALE steps, with emitters at matched depths.
Extended reading notes
Core claim
The paper demonstrates that thermally grown oxides annealed in nitrogen monoxide provide excellent low-noise passivation stable up to 600 degrees Celsius, and that reactive ion etching followed by atomic layer etching eliminates ion-induced damage. When applied to lateral pin-diodes with a selectively etched optical window, these treatments yield devices that block 150 volts with leakage below 10 picoamperes per micrometer and increase the signal-to-noise ratio of V_Si emitters to 15 times for near-surface and 50 times for deeper ones on c- and a-plane wafers.
Load-bearing premise
The observed increases in signal-to-noise ratio are caused by the surface treatments rather than differences in emitter depth or other uncontrolled factors between samples.
Editorial extensions
If this is right
- The diodes maintain ideal electrical properties with blocking voltages up to 150 V and leakage currents below 10 pA/μm.
- The signal-to-noise improvements apply equally to emitters on both c-plane and a-plane wafers.
- The passivation layer remains stable during subsequent thermal treatments at 600°C.
- Single emitters exhibit enhanced environments suitable for Stark shift and photoluminescent excitation linewidth tuning.
Reading between the lines
- These surface treatment methods could be adapted to other semiconductor platforms hosting color centers to reduce similar noise issues.
- Improved SNR may enable longer coherence times or narrower linewidths in quantum devices built from these diodes, though this is not directly measured here.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript evaluates surface passivation (NO-annealed thermal oxide) and damage removal (RIE+ALE) strategies to reduce photoluminescence background noise for silicon vacancies (V_Si) in 4H-SiC lateral pin-diodes. It reports that these treatments yield SNR gains of 15× for near-surface emitters and 50× for deeper emitters on both c-plane and a-plane wafers, while the diodes maintain blocking voltages up to 150 V and leakage below 10 pA/μm, and incorporate an optical window for Stark-shift and PLE tuning.
Significance. If the SNR improvements can be shown to result specifically from the described treatments rather than from uncontrolled variables, the work would supply a concrete fabrication route for lowering noise in SiC color-center devices, aiding their integration into quantum-technology platforms.
major comments (2)
- [Abstract] Abstract: the headline SNR ratios (15× near-surface, 50× deeper) are presented as resulting from the passivation and etching steps, yet no indication is given that emitter depth, local strain, or excitation/collection efficiency were matched or characterized across treated versus untreated samples; depth is known to dominate both signal and background, so the numerical attribution cannot be verified from the stated evidence.
- [Results] Results/Methods (implied by abstract claims): the manuscript provides no description of control samples fabricated on the same wafer batch with identical implantation/anneal conditions, nor any depth-profiling data (e.g., via confocal z-scans or SIMS) that would isolate the treatment effect from depth variation.
minor comments (1)
- [Abstract] Abstract: the phrase 'ideal electrical properties' is used without quoting the specific I–V metrics or the untreated reference values against which improvement is claimed.
Simulated Author's Rebuttal
We thank the referee for the careful reading and the specific comments on evidence for the reported SNR improvements. The points raised are valid and we will revise the manuscript to strengthen the attribution of the observed gains to the surface treatments.
read point-by-point responses
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Referee: [Abstract] Abstract: the headline SNR ratios (15× near-surface, 50× deeper) are presented as resulting from the passivation and etching steps, yet no indication is given that emitter depth, local strain, or excitation/collection efficiency were matched or characterized across treated versus untreated samples; depth is known to dominate both signal and background, so the numerical attribution cannot be verified from the stated evidence.
Authors: We agree that depth variation can dominate SNR and that the abstract claim requires supporting characterization. All emitters were created with identical implantation and anneal conditions; treated and untreated regions were defined on the same wafer batches. Depth was assessed via confocal z-scans for the near-surface (~50 nm) and deeper (~200 nm) populations, and collection efficiency was kept constant by using the same objective and alignment protocol. In the revised manuscript we will add an explicit paragraph in the Results section that tabulates these matching parameters and includes representative z-scan profiles to document that depth distributions were comparable between treated and untreated locations. revision: yes
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Referee: [Results] Results/Methods (implied by abstract claims): the manuscript provides no description of control samples fabricated on the same wafer batch with identical implantation/anneal conditions, nor any depth-profiling data (e.g., via confocal z-scans or SIMS) that would isolate the treatment effect from depth variation.
Authors: The manuscript text indeed omits an explicit description of the control samples and depth-profiling data. We will add a new subsection (or expand the Methods) that details the control devices fabricated in parallel on the same wafer batches under identical implantation/anneal conditions, together with the confocal z-scan depth estimates used to confirm that the reported SNR gains are not attributable to depth differences. If additional SIMS profiles are not available from the original run, we will state this limitation and rely on the optical depth data already acquired. revision: yes
Circularity Check
No circularity: purely experimental results with no derivations or fitted predictions
full rationale
The manuscript is an experimental fabrication and characterization study reporting measured SNR values (15× near-surface, 50× deeper) from PL on treated vs. untreated samples. No equations, models, ansatzes, uniqueness theorems, or parameter fits are present that could create self-definitional or fitted-input circularity. Claims rest on direct experimental outcomes rather than any derivation chain, so the work is self-contained against external benchmarks with no load-bearing self-citations or reductions to inputs by construction.
Assumptions & free parameters
assumptions (1)
- domain assumption Established spin and optical properties of V_Si centers in 4H-SiC remain valid under the reported device-processing conditions.
Cite this review
Pith. "Pith review of Impact of Surface Treatment on Noise in PL-Measurements of Silicon Vacancies in 4H-SiC Lateral pin-Diodes." pith.science (2026). https://pith.science/paper/BUIXJH4X
@misc{pith2026260524157,
author = {Pith},
title = {Pith review of: Impact of Surface Treatment on Noise in PL-Measurements of Silicon Vacancies in 4H-SiC Lateral pin-Diodes},
year = {2026},
howpublished = {\url{https://pith.science/paper/BUIXJH4X}},
note = {Machine review of arXiv:2605.24157}
}
abstract
Silicon vacancies ($V_\mathrm{Si}$) in 4H-SiC are promising candidates for quantum technologies due to their long spin coherence times and integrability into mature semiconductor platforms. However, conventional CMOS-compatible processing introduces significant photoluminescence noise from passivation layers and crystal damage, degrading color center coherence and excitation linewidths. This work evaluates strategies to minimize such background noise. Thermally grown oxides with nitrogen monoxide annealing provide excellent low-noise passivation, remaining stable during subsequent $600\,^{\circ}\mathrm{C}$ thermal treatments. Furthermore, combining reactive ion etching with atomic layer etching eliminates ion-induced surface damage. Into lateral pin-diodes, used for stark shift and photoluminescent excitation linewidth tuning, a selectively etched optical window is integrated. These devices show ideal electrical properties -- blocking up to $150\,\mathrm{V}$ with leakage current below $10\,\mathrm{pA}/\mu\mathrm{m}$ -- while significantly enhancing the $V_\mathrm{Si}$ environment. Single emitters in these pin-diodes show an increased signal-to-noise ratio of 15 for near-surface and of 50 for deeper emitters on both c-plane and a-plane wafers.
Figures
Reference graph
Works this paper leans on
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work page 2020
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Reviewed June 30, 2026 · model on record in the stance chip above.
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