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arxiv: 2605.25552 · v1 · pith:EFYTD7VBnew · submitted 2026-05-25 · 🪐 quant-ph

Beyond Logical Circuits: Hardware-Aware Analysis of Expressibility and Trainability in Variational Quantum Algorithms

Muhammad Kashif , Muhammad Shafique This is my paper

Pith reviewed 2026-06-29 21:50 UTC · model grok-4.3

classification 🪐 quant-ph
keywords variational quantum algorithmstranspilationexpressibilitytrainabilityparameterized quantum circuitshardware-aware analysisansatz robustness
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The pith

Transpilation perturbs variational quantum circuits enough to change their expressibility by up to 125 percent and trainability by up to 25 percent depending on the ansatz.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that standard hardware transpilation steps alter the structure of parameterized quantum circuits in ways that shift both how well they can represent states and how trainable their parameters are. These shifts are strongly dependent on the chosen ansatz family, with structured circuits holding up better than highly entangled ones. Because most prior work evaluates expressibility and trainability only on the original logical circuit, the authors argue that those results can fail to predict what actually happens when the circuit runs on real hardware. The measurements use fidelity-based KL divergence for expressibility and gradient variance for trainability, applied after qubit mapping, routing, and basis decomposition. If the claim holds, designers cannot safely optimize circuits at the logical level alone.

Core claim

Transpilation acts as an implicit architectural perturbation, producing strongly ansatz-dependent effects. Expressibility deviations exceed 125 percent in some cases while trainability variations reach up to 25 percent. Structured ansatzes are generally more robust, whereas highly entangled architectures are more sensitive to transpilation-induced transformations. Transpilation can alter the commonly assumed expressibility-trainability trade-off, demonstrating that logical-level analyses may not reliably predict hardware-level behavior.

What carries the argument

Comparison of logical versus transpiled parameterized quantum circuits, with expressibility measured by fidelity-based KL divergence and trainability by gradient variance after standard transpilation steps.

If this is right

  • Structured ansatzes maintain more stable expressibility and trainability after transpilation than highly entangled ones.
  • The expressibility-trainability trade-off observed at the logical level can reverse or disappear once the circuit is transpiled.
  • Logical-only studies of variational quantum algorithms can produce misleading rankings of which ansatzes perform best on hardware.
  • Hardware-aware evaluation is required to characterize variational quantum algorithm performance accurately.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Ansatz selection for near-term devices may need to include robustness to mapping and routing as an explicit design criterion.
  • Different qubit-connectivity graphs on real hardware could produce different sizes of these deviations, suggesting topology-specific ansatz libraries.
  • Future circuit compilers might incorporate expressibility or trainability preservation as an optimization objective alongside gate count.

Load-bearing premise

The analysis assumes that fidelity-based KL divergence and gradient variance computed after standard transpilation steps capture the dominant hardware-induced changes without requiring device-specific noise models or calibration data.

What would settle it

Running the same set of ansatzes on actual quantum hardware, measuring the real gradient variance and state fidelity distribution after transpilation, and finding that the deviations stay below 10 percent across all tested depths and qubit counts would falsify the reported magnitude of change.

Figures

Figures reproduced from arXiv: 2605.25552 by Muhammad Kashif, Muhammad Shafique.

Figure 1
Figure 1. Figure 1: Transpilation-induced overhead in expressibility and trainability for the [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: An illustration of PQC used in variational quantum algorithms [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Illustration of quantum circuit transpilation on IBM FakeWashington [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Overview of the our methodology. Logical PQCs from multiple ansatz families are first constructed across varying qubit counts and depths. These [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Ansatz Families used in this paper. (a) EfficientSU2 Ansatz, (b) HEA Ring Ansatz, (c) TTN Tree ansatz, (d) Real Amplitudes, (e) MPS Brick, (f) TwoLocalRYRZ circuit depths, and transpiler optimization levels [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Logical vs. transpiled qubit across all ansatz families. [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Logical vs. transpiled circuit depth as a function of ansatz repetitions (at logical level) for different logical qubit counts ( [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Expressibility overhead (transpiled-logical) of logical and transpiled ansatzes across all ansatz families. Positive values indicate higher KL values of [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Trainability overhead (transpiled-logical) of logical and transpiled ansatzes across all ansatz families. Positive values indicate higher trainability of [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
read the original abstract

Variational quantum algorithms (VQAs) rely on parameterized quantum circuits (PQCs), whose performance is governed by expressibility and trainability. Existing studies typically evaluate these properties at the logical circuit level, implicitly assuming that designed PQCs remain unchanged during hardware execution. In practice, however, hardware-aware transpilation modifies circuit structure through qubit mapping, routing, and basis decomposition, potentially altering PQC behavior. In this paper, we perform a systematic hardware-aware analysis of expressibility and trainability by comparing logical and transpiled PQCs across multiple ansatz families, qubit counts, and circuit depths. Expressibility is measured using fidelity-based KL divergence, while trainability is quantified through gradient variance. Our results show that transpilation acts as an implicit architectural perturbation, producing strongly ansatz-dependent effects. Expressibility deviations exceed upto 125% in some cases, while trainability variations reach up to 25%. Structured ansatzes are generally more robust, whereas highly entangled architectures are more sensitive to transpilation-induced transformations. We further show that transpilation can alter the commonly assumed expressibility-trainability trade-off, demonstrating that logical-level analyses may not reliably predict hardware-level behavior. These findings highlight the importance of hardware-aware evaluation for accurate characterization of VQAs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript claims that transpilation of parameterized quantum circuits (PQCs) in variational quantum algorithms acts as an implicit architectural perturbation. By comparing logical and transpiled circuits across ansatz families, qubit counts, and depths using fidelity-based KL divergence for expressibility and gradient variance for trainability, it reports ansatz-dependent deviations exceeding 125% in expressibility and reaching 25% in trainability. Structured ansatzes are more robust while entangled ones are sensitive, and transpilation can alter the expressibility-trainability trade-off, implying logical-level analyses do not reliably predict hardware behavior.

Significance. If the empirical findings hold under the stated metrics, the work is significant for highlighting that standard logical-circuit evaluations of VQAs can miss hardware-induced changes from mapping, routing, and decomposition. The systematic comparison across multiple ansatzes provides concrete, ansatz-specific evidence that could guide more reliable hardware-aware VQA design and evaluation practices.

major comments (1)
  1. [Abstract] Abstract: the central claim that 'logical-level analyses may not reliably predict hardware-level behavior' is load-bearing on the premise that noiseless post-transpilation metrics (fidelity KL divergence and gradient variance) capture dominant hardware effects. No device noise models, T1/T2 times, two-qubit error rates, or calibration data are incorporated, so the reported 125% and 25% deviations may not persist or could be reversed when realistic noise channels are added.
minor comments (1)
  1. [Abstract] Abstract: 'exceed upto 125%' contains a grammatical/typographical error and should read 'exceed up to 125%' or 'exceeds 125%'.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their detailed review and constructive feedback on our manuscript. We address the major comment point-by-point below, focusing on the scope of our hardware-aware analysis.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that 'logical-level analyses may not reliably predict hardware-level behavior' is load-bearing on the premise that noiseless post-transpilation metrics (fidelity KL divergence and gradient variance) capture dominant hardware effects. No device noise models, T1/T2 times, two-qubit error rates, or calibration data are incorporated, so the reported 125% and 25% deviations may not persist or could be reversed when realistic noise channels are added.

    Authors: We appreciate the referee's point on the distinction between structural and noisy hardware effects. Our work deliberately isolates the impact of transpilation (mapping, routing, and decomposition) as an implicit architectural change that occurs prior to and independently of noise during hardware execution. The reported deviations arise purely from these structural modifications to the PQC, which are mandatory for any hardware run and are not captured in logical-circuit analyses. While we agree that device noise would introduce further perturbations (potentially amplifying or mitigating the observed shifts), the core finding—that logical evaluations miss transpilation-induced changes—holds under the noiseless post-transpilation metrics used. We will revise the abstract and discussion sections to explicitly qualify the claim as applying to 'noiseless hardware-level circuit structure' and to note noise incorporation as valuable future work, without altering the empirical results or metrics. revision: partial

Circularity Check

0 steps flagged

Empirical comparison with no derivations or self-referential reductions

full rationale

The paper conducts a direct empirical comparison of expressibility (via fidelity-based KL divergence) and trainability (via gradient variance) between logical and transpiled PQCs across ansatz families. No equations, parameter fittings, or derivations are present in the provided text; results are obtained by applying standard transpilation steps and computing the metrics on the resulting circuits. No self-citations are invoked as load-bearing premises, and no ansatz or uniqueness theorem is smuggled in. The work is self-contained as a hardware-aware simulation study without any reduction of outputs to inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No free parameters, axioms, or invented entities are introduced; the study relies on standard expressibility and trainability metrics applied to existing ansatz families.

pith-pipeline@v0.9.1-grok · 5755 in / 1144 out tokens · 30328 ms · 2026-06-29T21:50:26.061237+00:00 · methodology

discussion (0)

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Reference graph

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