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REVIEW 3 major objections 8 minor 31 references

RISC-V vector extension addresses 128 qubits in one instruction

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-07-09 12:44 UTC pith:ITQ42I4D

load-bearing objection Solid ISA + microarchitecture contribution; the headline speedup number is fragile because it assumes an unrealistically short measurement latency. the 3 major comments →

arxiv 2607.07372 v1 pith:ITQ42I4D submitted 2026-07-08 cs.AR quant-ph

Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems

Xiaorang Guo , Kun Qin , Yanbin Chen , Carsten Trinitis , Martin Schulz This is my paper
classification cs.AR quant-ph
keywords quantum control processorRISC-V vector extensioninstruction set architecturemid-circuit measurementfault-tolerant quantum computingFPGAqubit addressingquantum error correction
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper argues that the RISC-V Vector (RVV) instruction set, extended with just four custom quantum instructions, can serve as a complete and scalable quantum control processor (QCP) without requiring a bespoke instruction set architecture. The authors pack qubit indices as 8-bit elements into standard vector registers, leveraging RVV's LMUL register-grouping mechanism to address up to 128 qubits per instruction—scaling from 8 to 128 qubits by changing a single configuration register, with no architectural redesign. They introduce QV.SINGLE and QV.PAIR for single- and two-qubit gate dispatch, and QV.ROT.G and QV.ROT.V for parameterized rotations, the latter handling mixed-precision operands (8-bit indices paired with 32-bit rotation angles) within a single instruction. For mid-circuit measurement—a primitive essential to quantum error correction and adaptive algorithms—they implement a hardware halt-resume protocol that drains the active quantum stream, waits for an external ADC readout, and resumes pipeline execution within 80 ns of receiving the measurement result. The entire design is implemented in RTL on a Xilinx ZCU216 FPGA, evaluated against 12 benchmark circuits, and achieves up to 2.52× speedup over the authors' prior custom-ISA design (HiSEP-Q 1.0), while consuming under 3.5% of FPGA resources. The central claim is that by building on the standard RISC-V ecosystem rather than replacing it, a QCP can inherit mature compiler infrastructure, formal verification tools, and open-source processor cores, while still achieving the parallelism, low-latency feedback, and scalability that fault-tolerant quantum computing will demand.

Core claim

The core object is the quantum vector instruction overlay on the RVV ISA. The paper's central discovery is that qubit addressing and gate dispatch can be mapped directly onto the RVV element-wise execution model: qubit indices become vector elements, LMUL grouping provides scalable parallelism (8–128 qubits per instruction through register grouping alone), and the standard vsetvli configuration instruction controls the operating point at runtime. The second key object is the hardware halt-resume protocol for mid-circuit measurement, which manages the measurement boundary entirely in microarchitecture rather than in software, avoiding the need for compiler-inserted delay or NOP instructions.

What carries the argument

Four quantum vector instructions (QV.SINGLE, QV.PAIR, QV.ROT.G, QV.ROT.V) encoded in reserved RVV opcode space; LMUL-based qubit addressing scaling from 8 to 128 qubits per instruction; mixed-precision operand handling for QV.ROT.V (8-bit indices in vs1, 32-bit angles in vs2 with implicit 4× LMUL scaling); hardware halt-resume protocol with Synchronizer and Quantum Adapter modules; per-qubit timed FIFOs in the Quantum Dispatcher with linear resource scaling (~90 LUTs and 263 FFs per qubit); Ibex RV32IMC scalar core coupled to Vicuna vector coprocessor via CORE-V XIF interface.

Load-bearing premise

The performance and scalability claims rest on FPGA synthesis at 100 MHz with simulated measurement latency, evaluated only against the authors' own prior design rather than against other contemporary quantum control processors, and the fault-tolerance readiness is extrapolated from resource scaling without testing error-correction workloads.

What would settle it

If, when implemented on real quantum hardware with actual AWG/ADC latencies and at production clock speeds, the 80 ns halt-resume time cannot be maintained or the LMUL-based dispatch fails to meet cycle-accurate timing requirements for multi-qubit gate synchronization, the core architectural advantage would not hold in practice.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • If the RVV overlay approach is correct, future QCP designs need not invest in custom ISA development or dedicated compiler infrastructure—the RISC-V ecosystem (LLVM, GNU toolchain, open-source cores) can be directly inherited, reducing the engineering cost of building quantum control systems.
  • The linear hardware scaling of the Quantum Dispatcher (~90 LUTs/qubit) suggests that a single RFSoC device could control hundreds of qubits, which is the scale at which quantum error correction becomes feasible.
  • The 80 ns halt-resume latency, if it holds in production hardware, is well within typical qubit coherence windows, making hardware-managed mid-circuit measurement practical for adaptive algorithms and error-correction syndrome extraction.
  • The mixed-precision operand mechanism in QV.ROT.V demonstrates that the RVV framework can handle semantically paired data streams of different widths within a single instruction, a pattern that may generalize to other domain-specific RVV extensions beyond quantum control.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The speedup results are measured exclusively against the authors' own prior work (HiSEP-Q 1.0), so the 2.52× figure demonstrates improvement within a single research lineage; comparison against other contemporary QCPs (e.g., QubiC 2.0, Qtenon, RISC-Q) would be needed to establish relative standing in the field.
  • The 100 MHz FPGA clock is substantially slower than production quantum control systems, and the evaluation uses a simulated 50 ns measurement latency rather than real ADC hardware; actual performance with physical qubit readout and real AWG/ADC latencies remains unquantified.
  • The FTQC-readiness claim rests on resource-scaling extrapolation and ISA encoding capacity analysis (1024 encodable gates), but no circuits with realistic error-correction depth or syndrome-extraction workloads were tested; the largest benchmark used 32 qubits.
  • The QV.ROT.V instruction's legal configurations are limited to LMUL mf2, m1, and m2 (8–32 qubits), which means per-qubit variable rotations cannot reach the full 128-qubit parallelism available to other instruction types—a constraint that may matter for variational algorithms with large qubit counts.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 8 minor

Summary. This paper presents HiSEP-Q 2.0, a quantum control processor (QCP) built as an extension to the RISC-V Vector (RVV) ISA. The design introduces four quantum vector instructions (QV.SINGLE, QV.PAIR, QV.ROT.G, QV.ROT.V) that leverage RVV's LMUL grouping to address up to 128 qubits in a single instruction. A hardware halt-resume protocol handles mid-circuit measurement (MCM) feedback, with a reported 80 ns resume latency. The design is implemented in RTL on a Xilinx ZCU216 FPGA and evaluated against the authors' prior work (HiSEP-Q 1.0) across 12 MQT Bench circuits, reporting a geometric-mean speedup of 1.32x (peak 2.52x). The approach of mapping quantum gate dispatch onto a standard vector extension is architecturally sound and the ISA encoding is internally consistent.

Significance. The primary contribution is the demonstration that quantum gate dispatch can be cleanly integrated into the standard RISC-V Vector extension framework, inheriting mature toolchain support (LLVM, GNU) while achieving scalable parallel qubit addressing. The four-instruction extension is compact and the mixed-precision operand handling for QV.ROT.V (8-bit indices, 32-bit angles) is a neat reuse of RVV semantics. The RTL implementation is open-source, and the resource analysis (Fig. 6) showing strictly linear scaling of the Quantum Dispatcher (~90 LUTs/qubit) is a concrete, falsifiable result. The end-to-end Bell-state verification (Listing 3) traces 32 events and 40 firings with zero FIFO errors, confirming functional correctness.

major comments (3)
  1. §V.C, Fig. 4: The headline speedup numbers (geomean 1.32x, peak 2.52x) are computed assuming a 50 ns backend measurement duration. This parameter is load-bearing because both HiSEP-Q 1.0 and 2.0 incur the same measurement wait time — the vectorization benefit only reduces the instruction-dispatch portion. Listing 3 confirms that of 177 total cycles, 124 are measurement wait. With a 50 ns (5-cycle) measurement, the speedup is dominated by the computation difference. However, typical superconducting qubit readout times are 500 ns–2 us (50–200 cycles at 100 MHz), which would substantially dilute the reported speedup. A back-of-envelope calculation using the paper's own cycle counts suggests the peak speedup drops from ~2.5x to ~1.3–1.5x at realistic readout latencies. The paper provides no sensitivity analysis for this parameter. This directly undermines the quantitative performance claim.
  2. §V.C, Fig. 4: All speedup comparisons are exclusively against HiSEP-Q 1.0 (ref [14]), authored by the same group. While this is a legitimate within-lineage comparison, the paper does not benchmark against any other contemporary QCP (e.g., QubiC 2.0 [12], Qtenon [9], RISC-Q [11]). The Related Work (§VI) discusses these systems but provides no quantitative comparison. This limits the reader's ability to assess the design's competitive standing. At minimum, the paper should explicitly acknowledge this scope limitation in the evaluation section rather than claiming general superiority.
  3. §V.F: The claim that 'HiSEP-Q 2.0 is ready for FTQC-scale qubit counts without architectural redesign' rests on resource-scaling extrapolation (Fig. 6, up to 128 qubits) and ISA-encoding capacity arguments. However, no workloads beyond 32 qubits or circuits with realistic QEC depth (e.g., surface code syndrome extraction) are tested. The linear resource scaling is necessary but not sufficient for FTQC-readiness; timing closure, dispatch throughput under deep circuit depth, and interaction with real AWG/ADC latencies at scale are unaddressed. This claim should be qualified.
minor comments (8)
  1. §I: The abstract states 'geometric-mean speedup of 1.32x' while §V.C states 'geometric-mean speedup of 1.26x'. These should be reconciled.
  2. Table V: The total LUT count is listed as 14,887 in the table but 14,888 in the text (§V.E). Similarly, FFs are 15,472 in the table vs. 15,492 in the text. Please correct.
  3. §III.C.4, Eq. (2): The implicit LMUL scaling rule (LMUL_vs2 = 4 × LMUL_vs1) is described clearly, but it would help to note in Table IV that the 'Elements' column counts per-instruction elements, not per-register elements, to avoid confusion.
  4. §V.D, Eq. (3): The throughput metric definition is reasonable but the specific values of B_dyn and B_meta for each instruction type are not tabulated. A small table showing these values per instruction would make the throughput results in Fig. 5b reproducible.
  5. §V.B, Listing 3: The trace shows cycle 31 for qvsg_meas assertion and cycle 106 for AWG MEAS firing. The 75-cycle gap between commit and AWG firing is not explained. A brief note on this delay would clarify the timing model.
  6. Fig. 4: The y-axis label 'Speedup' should specify 'over HiSEP-Q 1.0' for standalone clarity.
  7. §V.F: The statement that 2^7 = 128 distinct gate encodings per funct3 subclass is 'more than sufficient to cover any foreseeable logical or physical gate set' is strong. A brief citation or examples of gate set sizes in existing QEC proposals would strengthen this claim.
  8. References: Ref [4] (Bluvstein et al., Nature 2026) and Ref [19] (Ibex, 2026) have future dates. If these are accepted/in-press, please verify the final publication details.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for a thorough and constructive report. The referee raises three major concerns: (1) the sensitivity of reported speedups to the assumed measurement duration, (2) the absence of comparisons beyond our own prior work, and (3) the strength of FTQC-readiness claims given the evaluation scope. We agree that all three points identify legitimate gaps between what the data supports and what the manuscript claims. We will revise the manuscript accordingly: adding a sensitivity analysis for measurement latency, explicitly acknowledging the scope limitation of the comparison baseline, and qualifying the FTQC-readiness claim. No standing objections remain.

read point-by-point responses

  1. Referee: The headline speedup numbers are computed assuming a 50 ns backend measurement duration. Typical superconducting qubit readout times are 500 ns–2 us, which would substantially dilute the reported speedup. The paper provides no sensitivity analysis for this parameter.

    Authors: The referee is correct. The 50 ns (5-cycle) measurement duration used in our speedup calculations is not representative of typical superconducting qubit readout latencies, and the absence of a sensitivity analysis is a genuine gap. We acknowledge that at realistic readout latencies (500 ns–2 us, i.e., 50–200 cycles at 100 MHz), the measurement wait time dominates total execution time and the relative speedup from vectorized instruction dispatch is compressed. The referee's back-of-envelope estimate that the peak speedup drops to approximately 1.3–1.5x at realistic latencies is consistent with our own cycle counts: in the Bell-8 benchmark, 124 of 177 total cycles are measurement wait, so increasing the wait from 5 to 50–200 cycles would substantially dilute the 2.52x figure. We will revise the manuscript to: (1) add a sensitivity analysis plotting speedup as a function of measurement duration across the 50 ns–2 us range, (2) report both the optimistic (50 ns) and realistic (500 ns–2 us) speedup figures, and (3) add a discussion clarifying that the vectorization benefit applies specifically to the instruction-dispatch portion of execution, not to the measurement wait. We will also adjust the abstract to avoid presenting the 2.52x figure without this context. revision: yes

  2. Referee: All speedup comparisons are exclusively against HiSEP-Q 1.0, authored by the same group. No benchmarking against other contemporary QCPs (e.g., QubiC 2.0, Qtenon, RISC-Q) is provided. The paper should explicitly acknowledge this scope limitation rather than claiming general superiority.

    Authors: The referee is correct that the evaluation is limited to a within-lineage comparison against HiSEP-Q 1.0. We did not benchmark against QubiC 2.0, Qtenon, RISC-Q, or other contemporary QCPs, and the manuscript should not be read as claiming general superiority over all alternatives. A direct cross-architecture comparison would require implementing equivalent benchmark circuits on each target platform's toolchain and hardware, which we have not done. We will revise the evaluation section to explicitly state that the speedup figures are specific to the HiSEP-Q 1.0 vs. 2.0 comparison and do not constitute a competitive assessment against other QCPs. We will also clarify in the Related Work section that the quantitative comparison is scoped to our own design lineage, while the qualitative advantages we claim (toolchain inheritance from RISC-V, ISA compactness, linear resource scaling) are architectural properties rather than measured performance advantages over external systems. revision: yes

  3. Referee: The claim that HiSEP-Q 2.0 is ready for FTQC-scale qubit counts without architectural redesign rests on resource-scaling extrapolation and ISA-encoding capacity arguments. No workloads beyond 32 qubits or circuits with realistic QEC depth are tested. The claim should be qualified.

    Authors: The referee is correct. The claim that HiSEP-Q 2.0 is 'ready for FTQC-scale qubit counts without architectural redesign' is stronger than what our evaluation supports. Our evidence consists of: (1) linear resource scaling up to 128 qubits on FPGA (Fig. 6), and (2) ISA-encoding capacity arguments (1024 encodable gates, configurable SEW for larger qubit spaces). However, we have not tested workloads beyond 32 qubits, have not evaluated surface code syndrome extraction or other realistic QEC circuits, have not demonstrated timing closure at scale, and have not validated dispatch throughput under deep circuit depth or interaction with real AWG/ADC latencies at scale. These are necessary but unaddressed conditions for FTQC-readiness. We will revise Section V.F to qualify the claim as follows: the linear resource scaling and ISA-encoding capacity demonstrate that no architectural redesign is required to scale to larger qubit counts, but we do not claim FTQC-readiness in the full sense, which would require validation of timing closure, dispatch throughput under QEC-depth circuits, and integration with realistic readout latencies at scale. We will also note the absence of QEC-depth workload evaluation as an explicit limitation. revision: yes

Circularity Check

0 steps flagged

No significant circularity; one self-citation serves as comparison baseline, not as a load-bearing premise.

full rationale

The paper's central claims—ISA design, halt-resume protocol, speedup measurements, and resource utilization—are derived from an independent RTL implementation synthesized on FPGA, not from self-referential definitions or fitted-then-predicted parameters. The primary self-citation is to HiSEP-Q 1.0 [14] (same author group: Guo, Qin, Schulz), which serves as the performance baseline. However, this is a standard systems-paper practice of comparing against prior work; the speedup numbers (Fig. 4) are empirical cycle-count measurements from two different RTL implementations, not quantities derived from HiSEP-Q 1.0's own claims or equations. Equation (1) (qubits per instruction) follows directly from the standard RVV specification [17], not from the authors' prior work. The linear resource scaling (Fig. 6) is measured from synthesis and compared against RTL structural expectations—standard verification, not circular reasoning. The 50 ns measurement-duration assumption (§V.C) is a modeling parameter that affects the magnitude of reported speedups, but this is a correctness/sensitivity concern, not circularity: the speedup is computed from measured cycle counts, not from a parameter fitted to the output and then presented as a prediction. No uniqueness theorem, no ansatz smuggled through self-citation, and no renaming of known results as novel derivation were found. The self-citation to [14] is minor and non-load-bearing for the paper's independent architectural contributions.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 3 invented entities

The design has 5 free parameters (VLEN, SEW, clock, measurement duration, Blk_imm width), 5 axioms (3 standard/domain, 1 ad-hoc FTQC extrapolation), and 3 invented entities all backed by RTL implementation and FPGA verification. The main concern is the ad-hoc FTQC-readiness claim based on 128-qubit scaling data.

free parameters (5)
  • VLEN = 128 = 128 bits
    Set as the vector register width for the implementation; determines max qubits per instruction via Eq. 1. Stated in §III.B and Table III.
  • SEW = 8 = 8 bits
    Qubit index width; chosen to track up to 256 qubits. Stated in §III.B. Configurable but fixed for evaluation.
  • Clock frequency = 100 MHz = 100 MHz
    FPGA synthesis clock; determines the 80 ns halt-resume latency (8 cycles). Stated in §V.A.
  • Backend measurement duration = 50 ns = 50 ns
    Assumed for Fig. 4 speedup calculations. Stated in §V.C without physical justification or sensitivity analysis.
  • Blk_imm field = 5 bits = 5-bit immediate
    Encodes delay interval between gate operations. Stated in §III.B as a design choice.
axioms (5)
  • standard math RISC-V Vector Extension specification [17] is correct and stable
    The entire ISA extension is built on the RVV spec. Invoked throughout §III.
  • domain assumption CORE-V XIF interface [18] correctly couples scalar host to vector coprocessor
    The QXIF interface transports offloaded instructions between Ibex and QVCP. Invoked in §IV.B.
  • domain assumption Per-qubit timed FIFO queues are sufficient for correct gate scheduling
    The Quantum Dispatcher uses per-qubit FIFOs with timing controllers. Invoked in §IV.B. No analysis of FIFO depth requirements or overflow conditions under realistic workloads.
  • domain assumption 8-bit qubit indices are sufficient for foreseeable qubit counts
    SEW=8 is used throughout evaluation. §V.F notes SEW can be reconfigured but does not evaluate larger configurations.
  • ad hoc to paper Linear resource scaling at 128 qubits implies feasibility at FTQC scale (hundreds to thousands)
    §V.F extrapolates from 128-qubit FPGA results to FTQC readiness without testing beyond 128 qubits or considering routing, timing closure, or memory bandwidth at scale.
invented entities (3)
  • QV.SINGLE / QV.PAIR / QV.ROT.G / QV.ROT.V instructions independent evidence
    purpose: Quantum gate dispatch via RISC-V Vector encoding
    Implemented in open-source RTL, verified on FPGA with Bell-state circuit trace (Listing 3), and benchmarked on 12 MQT Bench circuits. Falsifiable: incorrect encoding or dispatch would show in the per-qubit trace.
  • Hardware halt-resume protocol (Synchronizer module) independent evidence
    purpose: Manage mid-circuit measurement pause/resume without software delays
    Implemented in RTL, measured at 8 cycles (80 ns) resume latency. Falsifiable: if the protocol fails, the pipeline would deadlock or miss measurement-dependent branches.
  • Quantum Dispatcher with per-qubit timed_fifo independent evidence
    purpose: Convert vector event stream into per-qubit time-scheduled pulses
    Implemented and measured for resource scaling (Fig. 6). Falsifiable: FIFO overflow or timing skew would manifest as incorrect gate dispatch.

pith-pipeline@v1.1.0-glm · 19515 in / 3807 out tokens · 449644 ms · 2026-07-09T12:44:59.797570+00:00 · methodology

0 comments
read the original abstract

The Quantum Control Processor (QCP) bridges the gap between compiler toolchains and control electronics, and is responsible for translating compiled quantum circuits into executable instructions that directly manipulate qubits and handle measurement feedback. However, existing designs rely primarily on customized instruction sets, limiting design reuse and requiring significant effort to build supporting toolchains. Furthermore, efficiently addressing qubits and scheduling operations in highly scalable scenarios remains a critical challenge. In this work, we present a vectorized quantum control approach built upon the RISC-V Vector (RVV) engine with a quantum-oriented extension. Leveraging the high parallelism of RVV, our approach can address up to 128 qubits in a single instruction. We also embed parameterized rotation information into the instruction set, enabling dynamic tuning of gate rotations in hybrid quantum-classical programs. To support mid-circuit measurements, we design a hardware-based halt-resume protocol that resumes pipeline execution within 80 $ns$ of receiving the measurement result. Comprehensive evaluation using both RISC-V toolchains and FPGA prototypes demonstrates that our design achieves up to 2.52$\times$ speedup over the baseline in program execution time, with excellent scalability.

Figures

Figures reproduced from arXiv: 2607.07372 by Carsten Trinitis, Kun Qin, Martin Schulz, Xiaorang Guo, Yanbin Chen.

Figure 1
Figure 1. Figure 1: HiSEP-Q 2.0 in the quantum software stack. The [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Overall architecture of the Ibex-coupled quantum vector engine and its execution back end. [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Main blocks of QVCP Core. Quantum instructions use a dedicated sideband export path to expose the quantum elements to the QVCP Back-end. sideband in parallel through the QVCP Back-end block. This path carries the externally visible quantum payload fields, including valid, op_type, id, and quantum payloads, together with the associated qualifiers and measurement￾related control signals. Hence, the quantum-e… view at source ↗
Figure 4
Figure 4. Figure 4: Execution time speedup compared to HiSEP-Q 1.0 (Baseline) [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Latency and throughput of the new quantum instruc [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Resource scalability (LUT&FF) of HiSEP-Q 2.0 versus [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

discussion (0)

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