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REVIEW 3 major objections 5 minor 58 references

HybridQC, a hardware-grounded simulator, claims that controllers and schedulers—not QPUs alone—set hybrid workload performance, predicting 2.19–3.42× speedup from balanced 10× scaling and up to 1.80× makespan swings from scheduling policy.

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2026-08-02 05:24 UTC pith:JSK6P7ZT

load-bearing objection A genuinely useful simulator idea with an honest architectural argument, but the headline accuracy and scaling claims outrun the evidence: the abstract mixes training and validation fits, and the 100x forecasts are extrapolations of linear service models beyond anything validated. the 3 major comments →

arxiv 2607.13352 v1 pith:JSK6P7ZT submitted 2026-07-15 cs.PF quant-ph

HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou , Shuwen Kan , Ying Mao This is my paper
classification cs.PF quant-ph
keywords hybrid quantum-classical systemsdiscrete-event simulationtopology-aware modelingquantum annealingdigital quantum circuitsworkload scalingscheduling policiesperformance bottleneck prediction
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper introduces HybridQC, a discrete-event simulator that treats a tightly coupled hybrid quantum-classical machine as a graph of classical processors, memories, controllers, quantum annealers, digital quantum processors, and explicit communication links. Its central claim is that end-to-end hybrid workload performance is set by contention across the whole topology—controllers, links, and schedulers—rather than by quantum execution alone. To make that claim concrete, HybridQC calibrates backend-specific service-time models on live D-Wave and IBM measurements, separating physical QPU occupancy from cloud wall-clock overhead, and reports mean absolute percentage errors of 3.92–8.04% for D-Wave QPU access time and 5.26–19.01% for IBM quantum seconds. Using those grounded models, it forecasts that balanced 10× hardware scaling improves makespan by only 2.19–3.42×, that scheduling-policy choice changes a 20-job mixed workload's makespan by up to 1.80×, and that scaling along different workload axes produces very different bottlenecks. The paper cites scope and extrapolation as its main limitations: the large 100× scaling numbers are a controlled stress test under configured resource constraints, not a validated prediction for uncharted hardware regimes.

Core claim

On the paper's own terms, HybridQC's discovery is that the critical path in a hybrid workload runs through controllers, transfer links, and classical reconstruction stages as much as through the QPU itself. Given a user-defined HCU topology and lowered workload DAGs, the simulator reproduces measured D-Wave QPU access time and IBM-reported quantum seconds well enough (3.92–8.04% and 5.26–19.01% MAPE) to forecast bottleneck migration. Its headline predictions: balanced 10× topology scaling yields 2.19–3.42× makespan improvement; QA-controller replication raises throughput from 2.85 to 9.75 jobs/s while DQC-controller replication cuts p95 completion time from 7601 s to 6348 s; scheduling polic

What carries the argument

The central object is the HCU resource graph: a directed graph of finite-capacity CPU/GPU pools, memories, QA devices, DQC devices, controllers, and optional accelerators, connected by links with latency, bandwidth, and chunking limits. Workloads are lowered into typed stage DAGs—preprocessing, embedding/transpilation, controller programming and readout, QA/DQC execution, transfer, reconstruction, postprocessing—so that every job explicitly reserves the topology it needs. Two mechanisms carry the analysis. First, physical QPU occupancy is separated from provider wall time: QA stages are grounded in measured D-Wave QPU access time and DQC stages in IBM-reported quantum seconds, keeping cloud

Load-bearing premise

The load-bearing premise is that the fitted linear service-time models remain valid when extrapolated to 100× larger circuits, shots, and depths than the calibrated range (up to depth ~2,000 calibrated vs. 200,000 forecast), since the headline scaling numbers are direct outputs of that extrapolation and the paper does not validate beyond the tested range.

What would settle it

Run a small subset of the 100× circuits-shots-depth DQC workload (e.g., the VQE or transmission-switching family at scaled depth and shot count) on an actual IBM backend and compare the reported quantum seconds to the fitted linear model's prediction; if the measured error grows substantially beyond the 5–19% MAPE range, the extrapolated scaling numbers are artifacts of the linear service-time assumption rather than stable predictions. The same check can be done for D-Wave QPU access time under 100× reads.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • A future HCU should provision controllers and links together with QPUs: adding DQC devices alone changes average throughput by about 1%, while QA-controller replication gives a 3.43× throughput gain and DQC-controller replication a 16.5% tail-latency reduction.
  • Scheduling policy is a first-class architectural knob: in a 20-job mixed workload HOBA completes in 3812.66 s versus FIFO's 6862.32 s (1.80×), so policy choice should be co-designed with the topology and workload mix.
  • Scaling studies must report the growth axis: 100× data-only scaling stays near 306 s median runtime, while 100× joint circuits-shots-depth scaling reaches 4.806×10^7 s on the fixed HCU.
  • Cloud wall time should not be treated as physical QPU service: QA-only cloud-proxy rows inflate makespan by 2.5–4.5× depending on backend and scale, whereas DQC-heavy rows are nearly unaffected.
  • Balanced capacity growth helps but is sublinear: the 10× larger HCU improves median runtime for 100× workloads by 2.31–4.62× depending on the scaling axis, not 10×.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: because the IBM and D-Wave service models are fitted linear forms, the 100× forecasts assume the same linear coefficients hold at depth 200,000 and at large shot counts; validating one representative large-DQC row on real hardware (or on a non-linear model) would show whether the 4.806×10^7 s number is a lower or upper bound.
  • Editorial inference: the simulator's separation of provider overhead from physical occupancy makes it straightforward to test the economic case for local accelerator deployment: run the same workload in cloud-proxy mode versus integrated mode and compare makespan, which the appendix's V2 table begins to do.
  • Editorial inference: the QA load-shedding curves, grounded in 453 D-Wave SampleSet runs, yield a testable rule—amplify QA reads only when the measured 1% energy-gap hit probability is low enough that extra attempts pay for themselves; the paper's break-even formula gives the threshold.
  • Editorial inference: the graph-extension sweep could be turned into an automated design search that chooses controller, link, and capacity increments to meet a makespan target, rather than the fixed x1–x4 sweeps evaluated here; nothing in the simulator design prevents that, but the paper does not claim it.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. HybridQC is a discrete-event simulator for tightly integrated hybrid quantum-classical compute units. Workloads are lowered into typed stage DAGs and executed on a configurable graph of CPUs, GPUs, controllers, QA/DQC devices, memory, and links under interchangeable scheduling policies. Backend service-time models are calibrated from D-Wave (Advantage 1/2) QPU access times and IBM (Kingston, Marrakesh, Fez) quantum-seconds measurements, separating physical occupancy from cloud wall time. The paper reports 3.92–8.04% MAPE for D-Wave and 5.26–19.01% for IBM, then uses the calibrated models to study topology replica scaling, scheduling policies, and 10×/100× workload-scaling axes. It concludes that balanced topology scaling yields sublinear speedups, policy choice can change mixed-workload makespan by up to 1.80×, and joint circuit/shots/depth growth produces extreme saturation.

Significance. The paper addresses a real gap: most quantum-performance tools model kernels or cloud queues, not the classical control, communication, and scheduling topology of integrated hybrid systems. The explicit resource-graph abstraction, typed stage DAGs, and separation of QPU occupancy from provider wall time are useful design choices, and the appendices provide an unusually detailed audit trail of hardware campaigns, fit coefficients, policy rules, and scaling rows. The D-Wave and IBM calibration campaigns are genuine empirical grounding. However, the headline claims currently overstate the evidence: the abstract mixes training and validation fits, the 100× scaling forecasts are unvalidated linear extrapolations of fitted service models with no uncertainty bands, and the full simulator's topology/policy conclusions are not end-to-end validated. The framework is promising, and the issues identified are addressable within the manuscript's scope.

major comments (3)
  1. [Abstract, §5.5, Table 4, Appendix Table 16] The headline accuracy range mixes training and validation fits. Table 4 reports D-Wave Adv.-2 at 3.92% MAPE (263 rows) and Adv.-1 at 8.04% (240 rows); Appendix Table 16 shows the Adv.-2 figure is the embedding-aware training fit, while the same backend's workload-validation split is 25.17% MAPE on 240 rows, and Adv.-1 training is 15.72% MAPE. IBM Fez's 5.26% is a 7-row seed fit, not a held-out validation. The abstract's "3.92%–8.04%" and "5.26%–19.01%" therefore report best-case training and seed fits as if they formed one validation range. Because hardware grounding is the paper's first contribution, training/validation splits must be reported consistently and the abstract should state which numbers are prospective validation.
  2. [§5.8, Appendix B Eq. (5), Table 17] The 100× scaling forecasts are unvalidated linear extrapolations. The service model q = a + bN + cS/1000 + d(ΣD)S/1e6 + e(ΣQD)S/1e8 is fit on calibration rows whose logical depth reaches about 2,000 (Appendix Tables 12, 14), and the coefficients in Table 17 carry 5–19% MAPE. Section 5.8 then feeds 100× circuits, shots, and depth into the same linear equation, producing 4.806×10^7 s. This evaluates terms such as (ΣD)·S at feature products never observed, with no uncertainty propagation from the underlying fits. Section 6 correctly labels workload scaling a "controlled stress test," not universal predictions, but the abstract and §5.8 present the extrapolated values as headline results. Add uncertainty intervals, validate at intermediate scales or with holdout data, and state in the abstract that these are model extrapolations.
  3. [§5.1–§5.8, §6, Appendix J.2] The validation evidence is component-level only. V1 (Table 4) validates the QA/DQC service-time fits, but the E1/E2/S1 results are produced entirely by the discrete-event simulator; there is no comparison of a simulated full-workload makespan or throughput against a measured end-to-end run on any physical system. The paper's own Section 6 acknowledges that scaling is a stress test, but the abstract's "systematic framework for evaluating…" and contribution 1's "hardware-grounded" wording imply more. A cloud-proxy comparison using the retained wall-time fields (Table 20) or a measured single-job end-to-end trace would substantially increase confidence that the scheduler/topology conclusions follow from the model rather than from unvalidated stage-service assumptions.
minor comments (5)
  1. [Table 4] Add a "split" column with explicit Training/Validation labels (and row counts per split). The main text labels two D-Wave rows, but the table itself does not, making it easy for the abstract to mix them.
  2. [Appendix B, Eq. (5)] Define N, S, D_i, Q_i immediately before the equation, and state the units of all coefficients in Table 17. The Fez qubit-depth coefficient is negative (-2.573 s) and likely reflects the 7-row seed; a bootstrap confidence interval would help readers judge overfitting.
  3. [Figure 4] The abbreviation "DQC" is overloaded in the legend ("Fixed HCU DQC" / "10x HCU DQC"). Use "DQC service demand" and "DQC utilization" explicitly to avoid confusion between panels (a) and (b).
  4. [§5.7] The exact HOBA/Max-Pressure/FIFO times for the 20-job case should reference the named workload mix and repetition seed in Appendix J.4, since the main text currently presents a single set of point values without the underlying experimental context.
  5. [Reproducibility] The paper does not include an artifact availability statement. Given the detailed appendix tables, a link to the Rust/Python implementation and datasets would materially strengthen the reproducibility claim.

Circularity Check

0 steps flagged

No significant circularity: workload forecasts are extrapolations of externally calibrated service models, and the paper explicitly labels them as stress tests rather than independent predictions.

full rationale

The claimed derivation chain is: (1) measure D-Wave QPU access time and IBM-reported quantum seconds on real hardware; (2) fit backend-specific service models (Appendix B, Eq. 5: q = a + bN + cS/1000 + d(sum D_i)S/1e6 + e(sum Q_iD_i)S/1e8) to those measurements; (3) feed the calibrated service times into a discrete-event HCU simulator with explicit topology, controllers, links, and scheduling; (4) evaluate scaled workloads (Section 5.8, Figure 4, Appendix J.3). Each stage is an application of a fitted model, not a re-statement of the fitted parameters. The headline 4.806e7 s for 100x circuits-shots-depth is the value of Eq. 5 evaluated at 100x scaled features, summed through the simulator; that is extrapolation, not circularity. The paper does not fit any parameter to the 100x results, and Section 6 explicitly says 'Workload scaling is therefore a controlled stress test ... not universal predictions.' The D-Wave and IBM grounding is external (Ocean SampleSets, Qiskit/Runtime artifacts), with no self-citations or imported uniqueness theorems. One reporting weakness exists: the abstract's MAPE range includes a training fit (Advantage 2, 3.92%, per Appendix Table 16), while Section 5.5 labels it 'training fit'; this is a validation-quality concern, not a circular derivation, because the scaling forecast does not depend on the MAPE being out-of-sample. No step reduces by definition to its inputs.

Axiom & Free-Parameter Ledger

7 free parameters · 5 axioms · 0 invented entities

The central claims rest on fitted backend service-time coefficients (IBM and D-Wave), an ad hoc output payload multiplier, and an empirically fitted QA success probability, plus standard queuing and transfer-model assumptions. No new physical entities (particles, forces, etc.) are introduced; the HCU is a configurable graph abstraction, not a new physical system.

free parameters (7)
  • IBM Kingston quantum-seconds coefficients (a,b,c,d,e) = -4.205, 0.953, 1.131, 0.212, 2.548
    Fit to IBM-reported quantum seconds for 80 jobs (Table 17); used in the DQC service model and all DQC-heavy workload scaling results.
  • IBM Marrakesh quantum-seconds coefficients (a,b,c,d,e) = -1.708, 0.666, 1.065, 0.269, 1.356
    Fit to 21 jobs (Table 17); DQC service model for Marrakesh backend.
  • IBM Fez quantum-seconds coefficients (a,b,c,d,e) = -7.828, 1.456, 1.992, 0.211, -2.573
    Fit to only 7 jobs (Table 17); DQC service model for Fez; statistically weak support for the 5.26% MAPE.
  • D-Wave Advantage 1 QA access coefficients (program, per-read, readout delay) = 16952.0 μs, 125.94 μs/read, 20.58 μs/read
    Calibrated QA access-time model from hardware rows (Table 17); used as physical QA occupancy in simulations.
  • D-Wave Advantage 2 QA access coefficients = 35795.5 μs, 74.23 μs/read, 60.57 μs/read
    Calibrated QA access-time model from hardware rows (Table 17); used as physical QA occupancy.
  • Output payload scale factor = 16×
    Appendix E Table 8 note: 'Output payloads scale QA/DQC result bytes by 16× to represent multiple measurement data.' This ad hoc factor affects data-only scaling results and transfer-link contention.
  • QA load-shedding hit probability p̂_ε per QUBO size/degree group = Empirical from 453 D-Wave SampleSet runs, 926,900 samples at 1% energy gap
    Used in Appendix B Eqs. (6)-(8) for QA amplification and DQC fallback calculations; grounded in the hardware campaign but still an empirical fitted probability.
axioms (5)
  • domain assumption IBM-reported quantum seconds is a valid physical QPU occupancy target for DQC service
    Section 4.4.2 and Appendix I assert that quantum seconds represent true device occupancy. If provider-reported quantum seconds include hidden overhead or vary with queue state, the calibration target itself is biased.
  • domain assumption D-Wave QPU access time (not wall time) is a valid physical occupancy target for QA service
    Section 4.4.2 separates QPU access time from cloud wall time; the QA service model is fit to QPU access time. This is a defensible but domain-specific assumption.
  • standard math Chunked transfer model T_edge(B)=ceil(B/C)ℓ+B/β (Eq. 1) captures end-to-end data movement cost
    Section 3.5 defines transfer time as latency plus bandwidth, with per-chunk latency when buffers are limited. This is a standard analytical model but an idealization of real interconnects.
  • domain assumption Discrete-event queueing semantics faithfully represent real HCU resource contention
    Section 4.5: the simulator models stages, queues, and finite capacities. The calibration validates individual service-time components, but the full contention/scheduling model is not validated against any real HCU (none exists).
  • domain assumption Workload families in Appendix Table 8 (sampled uniformly per job) are representative of real hybrid quantum-classical applications
    The generality of the scaling and scheduling conclusions depends on the workload parameter ranges and uniform sampling in Table 8; real workloads may have different distributions.

pith-pipeline@v1.3.0-alltime-deepseek · 32213 in / 13251 out tokens · 132041 ms · 2026-08-02T05:24:14.523323+00:00 · methodology

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read the original abstract

Hybrid quantum-classical application performance is increasingly limited by classical control, host-to-QPU communication, and scheduling rather than quantum execution. Existing simulators and runtime interfaces analyze individual kernels but fail to address system-topology questions, such as controller bottlenecks, diminishing returns of QPU capacity, or resource contention under heterogeneous workloads. We introduce HybridQC, a topology-aware discrete-event simulator for tightly coupled hybrid compute units (HCUs). HybridQC models HCUs as configurable graphs of classical processors, memory, controllers, quantum annealing (QA) and digital quantum computing (DQC) devices, and communication links. It decomposes jobs into typed, directed acyclic graphs of stages, ranging from input preparation to classical postprocessing, executed under interchangeable scheduling policies. Calibrated with live measurements from D-Wave (Advantage 1 and 2) and IBM (Kingston, Marrakesh, and Fez) processors, HybridQC distinguishes physical QPU occupancy from cloud wall-clock latency. The models achieve mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds measurements. Workload experiments reveal that a balanced 10x HCU scaling improves makespan by only 2.19x-3.42x, while altering scheduling policies shifts makespan by up to 1.80x for a 20-job workload. Scalability varies heavily by workload dimension: a 100x input data increase yields a 306 s median runtime, whereas a 100x joint increase in circuit count, shot count, and circuit depth drives runtime to 4.806x10^7 s on an unchanged HCU. HybridQC offers a systematic framework for evaluating the topology, scheduling, and scaling limits of hybrid architectures prior to physical deployment.

Figures

Figures reproduced from arXiv: 2607.13352 by Panayiotis Christou, Shuwen Kan, Ying Mao.

Figure 1
Figure 1. Figure 1: Configurable HCU topology modeled by HybridQC. Users define an HCU as classical and quantum compute nodes connected by explicit data/control links. HybridQC then simulates stage-by-stage data flow, resource utilization, and contention across that topology. end-to-end behavior is shaped by the stages around that ker￾nel: input construction, embedding or transpilation, transfer, QPU execution, result collect… view at source ↗
Figure 2
Figure 2. Figure 2: System-level multi-stage view used by HybridQC. Logical workloads are lowered into stage graphs, scheduled across heterogeneous classical and quantum compute nodes and explicit links, and analyzed through data movement, utilization, bottleneck movement, run makespan, job-completion summaries, and throughput metrics [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Topology and policy effects in the true workload suite. (a) Replica scaling payoff: x1–x4 denotes the total instance count of the swept resource class, box height summarizes p95 job-completion time, and numbers inside boxes report average throughput in jobs/s. (b) Policy frontier for p95 job-completion time and throughput, regenerated from the current Rust experiment outputs. only −2 s. Replicating DQC dev… view at source ↗
Figure 4
Figure 4. Figure 4: Workload-scaling analysis. (a) 100× scaling by growth axis. Solid curves use the left log-runtime axis and dashed curves use the right utilization axis. (b) Bottleneck migration under fixed and 10× larger HCUs. (c) Median-runtime speedup from moving 100× workloads to the 10× larger HCU. The dashed line marks ideal 10× improvement. Abbreviations: data = payload/memory, shots = reads/shots, c = circuits, c+s… view at source ↗
Figure 5
Figure 5. Figure 5: Measured QA hit probability versus reads for a 1% energy-gap target at a 20 𝜇s anneal. The bands show the interquartile range across QUBO size/degree groups. Model component Grounding source Use QA amplification D-Wave SampleSets DQC fallback/load-shedding threshold [PITH_FULL_IMAGE:figures/full_fig_p019_5.png] view at source ↗
Figure 8
Figure 8. Figure 8: Policy-dependent completion time with CPF￾diagnostic decomposition, regenerated from the Rust HCU experiment batch. The stacked components show why the schedulers differ: they change which resource class dom￾inates active-wall bottleneck pressure rather than merely changing one queue. cloud/provider overhead. QA-only rows are most sensitive to this overhead. DQC-dominated rows are largely governed by DQC s… view at source ↗
Figure 7
Figure 7. Figure 7: Bottleneck migration as resource replicas change. The plot separates the completion-time payoff from the controller-share movement so this diagnostic can be in￾spected independently from the main-text topology sum￾mary. be useful for calibration without being the right model for a local accelerator deployment. The simulator needs two execution semantics. In cloud￾grounded mode, wall time and provider overh… view at source ↗

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