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Paper Citation Record · LEDGER

Hardware Design and Security in the Era of Chiplets and LLMs

As of 8 August 2026, this Paper Citation Record lists 76 of 76 outbound references and 0 inbound Pith citation observations for arXiv:2608.05063.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2608.05063 v1

Coverage vector

measured 76 of 76 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-06T10:13:23.040038Z

measured 76 of 76 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

76 of 76 outbound references displayed

  • verified exact2
  • verified fuzzy51
  • unresolved23
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 4d634498-161a-4edd-8cbe-d528687d0700 · outbound

This paper cites Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor families: Industrial product,.

Hardware Design and Security in the Era of Chiplets and LLMs Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor families: Industrial product,

Reference 1

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:32.452943Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.041398Z digest=sha256:a78fdf89ad4d082bcf8a0c52a0e51a7b699e29d484555e020753cb61eda86e1e

Observation e4abcbf4-281a-4790-b3db-eae037c0af44 · outbound

This paper cites [Online].

Hardware Design and Security in the Era of Chiplets and LLMs [Online]

Reference 2

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:32.219491Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.070906Z digest=sha256:827fd081bb8b628d0c1c9eab9ac2b20731176edf7e679ca2f0b76d2bc2066635

Observation 36c33d17-c6d7-4ece-85ad-90a6b05f976c · outbound

This paper cites Sapphire rapids: The next-generation Intel Xeon scalable processor,.

Hardware Design and Security in the Era of Chiplets and LLMs Sapphire rapids: The next-generation Intel Xeon scalable processor,

Reference 3

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:31.959421Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.126346Z digest=sha256:c73e0fad2b7a1c65a4d39faaacc063cf4183a4b99fe5e96c9a4c980ff1c967b5

Observation 2f79e9d0-1678-4590-b7fa-a21ef3a632e3 · outbound

This paper cites 2.5D root of trust: Secure system-level integration of untrusted chiplets,.

Hardware Design and Security in the Era of Chiplets and LLMs 2.5D root of trust: Secure system-level integration of untrusted chiplets,

Reference 4

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:31.704837Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.204432Z digest=sha256:ccf4320c3d8ba07ec9ebb1ced07270fd51de138172205eed513f7e26bcf164c9

Observation a810296a-0d24-4c7e-968f-00159c5ae657 · outbound

This paper cites Coherence attacks and countermeasures in interposer-based chiplet systems,.

Hardware Design and Security in the Era of Chiplets and LLMs Coherence attacks and countermeasures in interposer-based chiplet systems,

Reference 5

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:31.371081Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.264403Z digest=sha256:d5d7fc81ab56b1d197f6bcca7f6897d6caf60244d520a86d0f7abf1142b5f795

Observation 7e9f9df6-ff79-4323-870c-525b1bb37b71 · outbound

This paper cites On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and innovations,.

Hardware Design and Security in the Era of Chiplets and LLMs On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and innovations,

Reference 6

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:31.125012Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.357029Z digest=sha256:b8fc963c96f1a27cb2d70f77a957fa0f4ec0087747ada08f410833daf96a94e1

Observation 786d4075-d51f-4234-8f78-9a7ef5461c38 · outbound

This paper cites Cambricon-LLM: A chiplet-based hybrid architecture for on-device inference of 70B LLM,.

Hardware Design and Security in the Era of Chiplets and LLMs Cambricon-LLM: A chiplet-based hybrid architecture for on-device inference of 70B LLM,

Reference 7

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:30.986545Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.402382Z digest=sha256:8dafb2ea35970d58456dfb506fd4412362ea4fc1fe541d7540f3412f9cd440dc

Observation b9b2ab81-4977-4928-8df0-47be3e9fb641 · outbound

This paper cites Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models.

Hardware Design and Security in the Era of Chiplets and LLMs Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models

Reference 8

Resolution
verified exact
local_arxiv, observed 2026-08-06T10:13:24.223943Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.503814Z digest=sha256:3bfdbc7c961aa2677dbec0fe8e4208f625a8e835e5b2e36fe8b7ffcfd9434ea4

Observation 08a6fc24-31d5-48fd-8809-ceca4df77300 · outbound

This paper cites CHIME: Chiplet-based heterogeneous near-memory acceleration for edge multimodal LLM inference,.

Hardware Design and Security in the Era of Chiplets and LLMs CHIME: Chiplet-based heterogeneous near-memory acceleration for edge multimodal LLM inference,

Reference 9

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:16.585770Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:16.585770Z digest=sha256:428074fc7a9a8041c334e803e8077e4c999d10cc98415600059dab5d969ea285

Observation f80af512-f00b-4374-a759-00f85ec6404d · outbound

This paper cites LLMs and the future of chip design: Unveiling security risks and building trust,.

Hardware Design and Security in the Era of Chiplets and LLMs LLMs and the future of chip design: Unveiling security risks and building trust,

Reference 10

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:30.811237Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.663453Z digest=sha256:d25732add0b3ad868410840a71982ab28649e6a346e40443067e6e3c3334a715

Observation b6790aa9-5559-4100-b6ab-ab9273f2148f · outbound

This paper cites LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges.

Hardware Design and Security in the Era of Chiplets and LLMs LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

Reference 11

Resolution
verified exact
local_arxiv, observed 2026-08-06T10:13:24.005507Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.735595Z digest=sha256:6bf0b32fac5273c3e348172cabea5fe8a663e4cbded8a2fd64072afc21dd56c1

Observation 054426a6-4336-4f4e-aec7-295914ef2602 · outbound

This paper cites Large language models (LLMs) for electronic design automation (EDA): Special session paper,.

Hardware Design and Security in the Era of Chiplets and LLMs Large language models (LLMs) for electronic design automation (EDA): Special session paper,

Reference 12

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:30.683612Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.833185Z digest=sha256:47241396f42be341fed62847598766573a6b39017824fc5018d940ca627e0313

Observation 9fde4eef-98f2-4774-8d0e-5e3d6e623745 · outbound

This paper cites VeriGen: A large language model for Verilog code generation,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriGen: A large language model for Verilog code generation,

Reference 13

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:30.481644Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.903022Z digest=sha256:0d1cb33ae6969ef1bfabefbd316349778d27dd683288f1599492d87d5dbf6299

Observation 20b9cd47-21b8-463a-a352-2edfe95a0560 · outbound

This paper cites Automatically improving LLM-based Verilog generation using EDA tool feedback,.

Hardware Design and Security in the Era of Chiplets and LLMs Automatically improving LLM-based Verilog generation using EDA tool feedback,

Reference 14

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:30.308733Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.960808Z digest=sha256:6a5bbf96d37d3067ef4c9bd4689fffb693e33628cd2ee0dd397dfe6405bf93d8

Observation ea41fb18-92f0-40d5-8927-5fe9d757f53d · outbound

This paper cites VeriLeaky: Navigating IP protection vs utility in fine-tuning for LLM-driven Verilog coding,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriLeaky: Navigating IP protection vs utility in fine-tuning for LLM-driven Verilog coding,

Reference 15

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:30.143815Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:16.992853Z digest=sha256:4845d887118fd44388f176aa28825a070eed1f6c331b3d3eda5cd8e5255b271e

Observation c4a9b193-1270-4ab9-be15-591265617355 · outbound

This paper cites RTL-Breaker: Assessing the security of LLMs against backdoor attacks on HDL code generation,.

Hardware Design and Security in the Era of Chiplets and LLMs RTL-Breaker: Assessing the security of LLMs against backdoor attacks on HDL code generation,

Reference 16

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:29.987146Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.081690Z digest=sha256:93dcceca454787f1334dce193e5ca7fe1423442fc8d6856134315cbf901143e4

Observation bc8cca33-9443-4c69-ad5e-fb8c58697ad5 · outbound

This paper cites VeriContaminated: Assessing LLM-driven Verilog coding for data contamination,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriContaminated: Assessing LLM-driven Verilog coding for data contamination,

Reference 17

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:29.824125Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.149531Z digest=sha256:5c37d67eb2411b1ebead386555bc91fce8d74df1fec78d3bf8bbdf428de91537

Observation d6452aaa-3181-4bc0-b65d-dec8010692fe · outbound

This paper cites (Security) assertions by large language models,.

Hardware Design and Security in the Era of Chiplets and LLMs (Security) assertions by large language models,

Reference 18

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:29.698704Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.227068Z digest=sha256:8d450931a8e7ce4d5d019bd83cd3ccb04beb8a3ae928fec9cf7b3e56481bc652

Observation d743f4ab-e7f0-4933-9969-29796e18bd98 · outbound

This paper cites an unresolved cited work.

Hardware Design and Security in the Era of Chiplets and LLMs Unresolved cited work

Reference 19

Resolution
unresolved
raw_fallback, observed 2026-08-06T10:13:29.541347Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.304066Z digest=sha256:0b0484d02b23943808f799c7a82a40f0aef4ee8f923fef9c8bf0fbea537e0a1f

Observation f71d4e40-f0c0-43d4-86c3-dc8590f9dc78 · outbound

This paper cites Pioneering chiplet technology and design for the AMD EPYC and Ryzen processor families: Industrial product,.

Hardware Design and Security in the Era of Chiplets and LLMs Pioneering chiplet technology and design for the AMD EPYC and Ryzen processor families: Industrial product,

Reference 20

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:29.374484Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.410646Z digest=sha256:aced99479e5faaaec53ef54d9e7ae6dfb917985400acc150e1c12e19b0efe2d3

Observation 05ce852c-8297-4bc0-ad7e-f0a7287bf98f · outbound

This paper cites 3D integration: Another dimension toward hardware security,.

Hardware Design and Security in the Era of Chiplets and LLMs 3D integration: Another dimension toward hardware security,

Reference 21

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:29.256098Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.487276Z digest=sha256:88a2fab0ba069dd1fee1ca8970dce8e5428f8fca5e428798f69e520ef82ddd14

Observation 0e5a113f-da4b-465a-aa52-49677289c69c · outbound

This paper cites NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?.

Hardware Design and Security in the Era of Chiplets and LLMs NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?

Reference 22

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:29.056676Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.580520Z digest=sha256:dbf037bebe4f28dd0a403bcad38c30c2c6cbed0164a69f1b63e984f8f1743569

Observation 624d05b7-fc8e-4a10-81b9-d96276680fc1 · outbound

This paper cites Modular routing design for chiplet-based systems,.

Hardware Design and Security in the Era of Chiplets and LLMs Modular routing design for chiplet-based systems,

Reference 23

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.959580Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:17.657075Z digest=sha256:a0be0197deaacfc7b9c3293c904e6e4f0d1a175bd96a222aa4bc722f58b4a1e6

Observation 41c6e913-4222-4abc-a9c7-06c2a20c5e47 · outbound

This paper cites Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS.

Hardware Design and Security in the Era of Chiplets and LLMs Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

Reference 24

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:17.736131Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:17.736131Z digest=sha256:17d483b5648af974465f45b58895e6aaebe3c5b6d3d68993566b858ee1940f9e

Observation 131e0f3f-42b4-4827-9e2e-60af759f201d · outbound

This paper cites VeriThoughts: Enabling automated Verilog code generation using reasoning and formal verification,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriThoughts: Enabling automated Verilog code generation using reasoning and formal verification,

Reference 25

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:17.821573Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:17.821573Z digest=sha256:3aeea6c117a8ba90c70122e854a779b62618459e18c7199beac1cc4d33da21e2

Observation 71b7d99d-004a-4262-9df9-42e197c64547 · outbound

This paper cites From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design.

Hardware Design and Security in the Era of Chiplets and LLMs From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design

Reference 26

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:17.918881Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:17.918881Z digest=sha256:d5639beca6a15c7a988b8c5ff9bef1b8193dc85bfa1a248f604303a615d27cf6

Observation 4c5da9ec-064d-4d1e-bd74-135f2d44a36d · outbound

This paper cites C2HLSC: Leveraging large language models to bridge the software-to-hardware design gap,.

Hardware Design and Security in the Era of Chiplets and LLMs C2HLSC: Leveraging large language models to bridge the software-to-hardware design gap,

Reference 27

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.825331Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:18.040496Z digest=sha256:b5c70422c7d7fcdd2ebfff742725dfdba714162718ef82afb0bb2abc613205cc

Observation 5450b29b-9a2e-40a1-9035-4666e03b7a1f · outbound

This paper cites LLM-driven code generation for neural networks on FPGAs: Bridging Python and HLS,.

Hardware Design and Security in the Era of Chiplets and LLMs LLM-driven code generation for neural networks on FPGAs: Bridging Python and HLS,

Reference 28

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.626046Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:18.129230Z digest=sha256:61a44c57d6a5612a796b6ec0eececaaa3ab53e711054f8e5eff36afbc9e5a762

Observation c255d8b9-0d72-447b-8e95-137867ab2117 · outbound

This paper cites RTL++: Graph-enhanced LLM for RTL Code Generation.

Hardware Design and Security in the Era of Chiplets and LLMs RTL++: Graph-enhanced LLM for RTL Code Generation

Reference 29

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.224348Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.224348Z digest=sha256:53cda0fa041144c9ca06c2467422d506c461cd4872d93cda34fddff49f27e3da

Observation 8e692ef7-9cb4-445f-863e-eae7c319f237 · outbound

This paper cites Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form.

Hardware Design and Security in the Era of Chiplets and LLMs Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form

Reference 30

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.327854Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.327854Z digest=sha256:1a2dcaa9decaeecb12daa2b3ece036acd9094eb5418d8d864de81d44e8bb91ec

Observation 28dc7789-2f18-4267-8e9d-86bbf56aa139 · outbound

This paper cites Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification.

Hardware Design and Security in the Era of Chiplets and LLMs Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification

Reference 31

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.402301Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.402301Z digest=sha256:1cba8023aff034b21f1bb425845f1f18e459a4793304be924fcaa3f8fc052312

Observation f56ec65f-5b5a-4593-8622-190a76c3905c · outbound

This paper cites Hybrid-NL2SV A: Integrating RAG and finetuning for LLM-based NL2SV A,.

Hardware Design and Security in the Era of Chiplets and LLMs Hybrid-NL2SV A: Integrating RAG and finetuning for LLM-based NL2SV A,

Reference 32

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.516976Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:18.499516Z digest=sha256:5ac9fdb8e379615d5603317bf810cebc2ae904f3030f2fab0b59dcdef90b6b49

Observation 4c21de54-efd4-44e0-815b-302a87e7ace9 · outbound

This paper cites LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines.

Hardware Design and Security in the Era of Chiplets and LLMs LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 33

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.606997Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.606997Z digest=sha256:622e9e6782a6cb407838f335de46a30cfb60a04bfa024e658c7efe8861898628

Observation ff414ed6-b988-4f9a-9212-2de49ca84737 · outbound

This paper cites VeriDispatcher: Multi-model dispatching through pre-inference difficulty prediction for RTL generation optimization,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriDispatcher: Multi-model dispatching through pre-inference difficulty prediction for RTL generation optimization,

Reference 34

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.692047Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.692047Z digest=sha256:a79240d500444dc610634ca0e1c9558b8801f46d1884a4c8ea2495ed13ba339e

Observation e0fbc683-6024-4ec1-be9f-851537562a2d · outbound

This paper cites Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes.

Hardware Design and Security in the Era of Chiplets and LLMs Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes

Reference 35

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.864533Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.864533Z digest=sha256:1ec66fe9484dc76e30f103f1c7f3d3251a32bbaef015b38c69619e85e5085c81

Observation 9cd7485e-a228-4d98-a93c-a32d44d48d36 · outbound

This paper cites Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation.

Hardware Design and Security in the Era of Chiplets and LLMs Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation

Reference 36

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.970784Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.970784Z digest=sha256:90bd533d762e849ba21743f4aaef862a30c55e9ddb10ef5d3325898dd9d8d7e5

Observation b86133c5-290e-4f1d-835f-20eb2d894686 · outbound

This paper cites A survey of network-on-chip security attacks and countermea- sures,.

Hardware Design and Security in the Era of Chiplets and LLMs A survey of network-on-chip security attacks and countermea- sures,

Reference 37

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.394319Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:19.069475Z digest=sha256:a832800610fbefa09127aed7426804e43398c617769cf55cfdc00fdf4453f02d

Observation e8da0dda-ae5b-4e22-8496-72e332ceddda · outbound

This paper cites Cache hierarchy and memory subsystem of the AMD Opteron processor,.

Hardware Design and Security in the Era of Chiplets and LLMs Cache hierarchy and memory subsystem of the AMD Opteron processor,

Reference 38

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.219998Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:19.191588Z digest=sha256:7f9522d2d4a98cf5388b50e56dc66a882d0ded039b26b7c3a7ec0d29f0420144

Observation 572c2f29-cea5-4623-b71c-db6094945f64 · outbound

This paper cites Hardware Trojan threats to cache coherence in modern 2.5D chiplet systems,.

Hardware Design and Security in the Era of Chiplets and LLMs Hardware Trojan threats to cache coherence in modern 2.5D chiplet systems,

Reference 39

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.105654Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:19.313301Z digest=sha256:57439c4c61ec44bf98a92e11853f2665ce449ca6994ce124da51eaf50fa8908b

Observation 397f0e9c-f7fc-4b4a-ab93-aa38acfe3a10 · outbound

This paper cites Cache me, catch you: Cache related security threats in LLM serving frameworks,.

Hardware Design and Security in the Era of Chiplets and LLMs Cache me, catch you: Cache related security threats in LLM serving frameworks,

Reference 40

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:28.002665Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:19.422190Z digest=sha256:e7f45c6cb5f12995ffbba718c6433e7a0da1c96676d8e3b6929d65f3bb14cfec

Observation b03ad7f7-1e83-4f77-9bd6-bccbb3692d3b · outbound

This paper cites I know what you said: Unveiling hardware cache side-channels in local large language model inference,.

Hardware Design and Security in the Era of Chiplets and LLMs I know what you said: Unveiling hardware cache side-channels in local large language model inference,

Reference 41

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.879714Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:19.577125Z digest=sha256:3b1569674b42b29feb209d6575227661220cd35144f6d91ab3ed41053c55165d

Observation 4fb4439f-95df-450e-8e6c-9aea6e7d7be2 · outbound

This paper cites Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing,.

Hardware Design and Security in the Era of Chiplets and LLMs Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing,

Reference 42

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.731491Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:19.750419Z digest=sha256:7d3064e1306e7a869c60638d8c02a3bd91b8ef0f0cee93e5ac60c20255faa3d2

Observation d14ff061-f4c2-49fe-b0af-cadf9d99640a · outbound

This paper cites Meltdown.

Hardware Design and Security in the Era of Chiplets and LLMs Meltdown

Reference 43

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:19.866165Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:19.866165Z digest=sha256:8a0075cba5ca3cf97d484c0f4c042f92f4c802200a96a29debdc0460785df27d

Observation e491a1f5-15af-47e4-a52f-dd529ca03f56 · outbound

This paper cites BADFET: Defeating modern secure boot using second-order pulsed electromagnetic fault injection,.

Hardware Design and Security in the Era of Chiplets and LLMs BADFET: Defeating modern secure boot using second-order pulsed electromagnetic fault injection,

Reference 44

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.612968Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.035310Z digest=sha256:053f75854b937c47c2f30e5df5fe0d410c68023e3f1fd8379c187ef0ac0aa34e

Observation 73c56f4d-3d5c-44b6-839b-1a7ddf81128a · outbound

This paper cites Drammer: Deterministic Rowhammer attacks on mobile platforms,.

Hardware Design and Security in the Era of Chiplets and LLMs Drammer: Deterministic Rowhammer attacks on mobile platforms,

Reference 45

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.474753Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.152786Z digest=sha256:7765979be2db3fc3ff1d800fadc470b5984b088b7ff0a11ca560c2aa1429ded7

Observation bee647bf-871d-49c8-a5c4-e5bdbfe1a2a6 · outbound

This paper cites Probing attacks on integrated circuits: Challenges and research opportunities,.

Hardware Design and Security in the Era of Chiplets and LLMs Probing attacks on integrated circuits: Challenges and research opportunities,

Reference 46

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.343240Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.245373Z digest=sha256:64a2e73197db8bd08746934d612f5e3d1506853a6edc1757d45a98be276367ea

Observation 4c5ff5be-7353-4893-b020-44ebf0e884b5 · outbound

This paper cites Can transformer memory be corrupted? investigating cache- side vulnerabilities in large language models,.

Hardware Design and Security in the Era of Chiplets and LLMs Can transformer memory be corrupted? investigating cache- side vulnerabilities in large language models,

Reference 47

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:20.297286Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:20.297286Z digest=sha256:35b55afc16dc2346d22183a575837a76817c15087dcf758f46272d561b9e11fa

Observation b01987eb-19a9-4b14-bfce-aee50b4ec5f1 · outbound

This paper cites GhostWriter: Exploiting GPU-cache contention to steal and steer multi-tenant large-language-model inference,.

Hardware Design and Security in the Era of Chiplets and LLMs GhostWriter: Exploiting GPU-cache contention to steal and steer multi-tenant large-language-model inference,

Reference 48

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.182596Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.393985Z digest=sha256:ed5040fb9b8a60ebe0edcd652a0e86e448c48ef579348dff523701b2b14b83df

Observation 1d74bd1d-1678-402f-b574-067915e0b2ed · outbound

This paper cites Liu et al.,Securing system-on-chips: Hardware protection in the age of chiplets, PUFsecurity, 2023.

Hardware Design and Security in the Era of Chiplets and LLMs Liu et al.,Securing system-on-chips: Hardware protection in the age of chiplets, PUFsecurity, 2023

Reference 49

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:27.078598Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.466743Z digest=sha256:73d8ba8e84ba85e4e06a214d6e3b80abc52101f2fa76bc98bb6ade6b19fe72eb

Observation 94a44021-a288-438d-af35-0d435d010b08 · outbound

This paper cites Concerted wire lifting: Enabling secure and cost-effective split manufacturing,.

Hardware Design and Security in the Era of Chiplets and LLMs Concerted wire lifting: Enabling secure and cost-effective split manufacturing,

Reference 50

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:26.940814Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.557422Z digest=sha256:a5e79e4ded680155e976d1c9ab16f98fa7cf717a757419d5767044f3caab8e46

Observation 37b3a9f7-d21a-430a-8331-aa4abe8a2cbb · outbound

This paper cites A modern approach to IP protection and Trojan prevention: Split manufacturing for 3D ICs and obfuscation of vertical interconnects,.

Hardware Design and Security in the Era of Chiplets and LLMs A modern approach to IP protection and Trojan prevention: Split manufacturing for 3D ICs and obfuscation of vertical interconnects,

Reference 51

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:26.778316Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.720719Z digest=sha256:f8c606974af37562b6ce261fcf8674d62e830b9ce6622ba6c41183be56097fa0

Observation 6b008847-d6ab-4554-96f8-44997b298cbe · outbound

This paper cites Security-aware 2.5D integrated circuit design flow against hardware IP piracy,.

Hardware Design and Security in the Era of Chiplets and LLMs Security-aware 2.5D integrated circuit design flow against hardware IP piracy,

Reference 52

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:26.612315Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.820553Z digest=sha256:987b0b1df12f1fe6f2f4b99ff9b7641640ef94b2660ba628abcd703d019fc461

Observation c59300a8-cae2-4d14-b40a-9f105693c8cf · outbound

This paper cites Design flow for active interposer-based 2.5D ICs and study of RISC-V architecture with secure NoC,.

Hardware Design and Security in the Era of Chiplets and LLMs Design flow for active interposer-based 2.5D ICs and study of RISC-V architecture with secure NoC,

Reference 53

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:26.440337Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:20.931096Z digest=sha256:620940323451e2b045b2b6b0d0d00e5b263727cbb34cd1767f9888f3cb8eb851

Observation fddf765f-799a-44db-9491-2ced51a6afc7 · outbound

This paper cites Physical attack protection techniques for IC chip level hardware security,.

Hardware Design and Security in the Era of Chiplets and LLMs Physical attack protection techniques for IC chip level hardware security,

Reference 54

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:26.236428Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.042476Z digest=sha256:877c08ae4335a87686b976c4dbdf3a4bdc32412a019c67a20c4d4dc0971df814

Observation f37b96b6-4a83-43f4-8240-98678508c576 · outbound

This paper cites SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation.

Hardware Design and Security in the Era of Chiplets and LLMs SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation

Reference 55

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:21.159302Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:21.159302Z digest=sha256:c44b19aa8630338481aede8fcb85782dc1da7866896fafe8c7ce8688a6aa53b3

Observation be6d7725-de18-4db3-8967-38e201974582 · outbound

This paper cites Semantic consensus decoding: Backdoor defense for Verilog code generation,.

Hardware Design and Security in the Era of Chiplets and LLMs Semantic consensus decoding: Backdoor defense for Verilog code generation,

Reference 56

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:21.265040Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:21.265040Z digest=sha256:7288e80489fbbe091b57d1644f936e8717a24c0e069c2b5282539007e278ae1c

Observation f40016cb-1284-422b-992c-764b85394b22 · outbound

This paper cites Benchmarking large language models under data contamination: A survey from static to dynamic evaluation,.

Hardware Design and Security in the Era of Chiplets and LLMs Benchmarking large language models under data contamination: A survey from static to dynamic evaluation,

Reference 57

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:26.101804Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.402289Z digest=sha256:ebbadab9be6fc8d30d7ce561a2eb80d00b327893452c4648b0e02c1fe759fdbb

Observation 3dfbaee4-9144-42f8-8e30-935378321a95 · outbound

This paper cites SALAD: Systematic assessment of machine unlearning on LLM- aided hardware design,.

Hardware Design and Security in the Era of Chiplets and LLMs SALAD: Systematic assessment of machine unlearning on LLM- aided hardware design,

Reference 58

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.917756Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.500017Z digest=sha256:da5f74ad2cfe9f35e2a941d7dacf6fb97de98b163df17681ec61dfe1a4732230

Observation cd228115-3081-49b9-8cb1-a2ac1c14aa5a · outbound

This paper cites Prompt injection attacks in large language models and AI agent systems: A comprehensive review of vulnerabilities, attack vectors, and defense mechanisms,.

Hardware Design and Security in the Era of Chiplets and LLMs Prompt injection attacks in large language models and AI agent systems: A comprehensive review of vulnerabilities, attack vectors, and defense mechanisms,

Reference 59

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.786906Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.599057Z digest=sha256:f0a13cc761a9d57721ef3b16ed25aacbefd28f88111f6eaf1b45de61d2ef55f7

Observation 511e8cd4-d376-47d9-9d82-361be59f1e02 · outbound

This paper cites HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking.

Hardware Design and Security in the Era of Chiplets and LLMs HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking

Reference 60

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:21.678239Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:21.678239Z digest=sha256:ec75304933ffa61e26fa9dd9886340321f0fe9e00e4dfeebf107376fe9cb0079

Observation 890564ea-19d8-4293-99ad-d42dd1496b44 · outbound

This paper cites CircuitGuard: Mitigating LLM memorization in RTL code generation against IP leakage,.

Hardware Design and Security in the Era of Chiplets and LLMs CircuitGuard: Mitigating LLM memorization in RTL code generation against IP leakage,

Reference 61

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.624260Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.753057Z digest=sha256:94b38d680500596589311fff1ae04ffcffd3b526b477808374ddf46cf1550906

Observation e4c16fed-333a-4763-8155-f92ebebd19ba · outbound

This paper cites GLLaMoR: Graph-based logic locking by large language models for enhanced robustness,.

Hardware Design and Security in the Era of Chiplets and LLMs GLLaMoR: Graph-based logic locking by large language models for enhanced robustness,

Reference 62

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.488121Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.849283Z digest=sha256:dee9d043fb67e99fc4d4aeb4bd36e6b32f738f31c92550b22c6209481f13d1b4

Observation ed559d4a-0057-490f-b2bc-0b08680c5f15 · outbound

This paper cites LockForge: Automating paper-to-code for logic locking with multi-agent reasoning LLMs,.

Hardware Design and Security in the Era of Chiplets and LLMs LockForge: Automating paper-to-code for logic locking with multi-agent reasoning LLMs,

Reference 63

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.340538Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:21.926504Z digest=sha256:5d3b7d6488fd3fb256544bd3b7668bd95d2dc5aec7d52eb014672fca7f84fd7b

Observation 2cfc3532-9737-40c4-badd-1d11d29bfeb8 · outbound

This paper cites Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection.

Hardware Design and Security in the Era of Chiplets and LLMs Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection

Reference 64

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:22.030650Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:22.030650Z digest=sha256:b30e52ecc1253e4016a92388b26bdbfd80617d4a9f4b47a0154506710a9f60fc

Observation b6ca95a5-3924-4bdf-a166-74c30bbd68b9 · outbound

This paper cites ARIANNA: An automatic design flow for fabric customization and eFPGA redaction,.

Hardware Design and Security in the Era of Chiplets and LLMs ARIANNA: An automatic design flow for fabric customization and eFPGA redaction,

Reference 65

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.204272Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:22.116066Z digest=sha256:30e93c6a334cae5041aa0ad07a058a67279ccec0b50e872f0e32b21a9456b312

Observation 303b1c26-c606-42a2-a35b-bcf0a2435219 · outbound

This paper cites Netlist whisperer: Extensive analysis of circuit leakage using LLMs,.

Hardware Design and Security in the Era of Chiplets and LLMs Netlist whisperer: Extensive analysis of circuit leakage using LLMs,

Reference 66

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:25.070225Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:22.197812Z digest=sha256:4fc1a59441ce1fc3b2440a9934eb6cfe51ce8f53f93c755db6d700ad8fb62962

Observation d727b3cd-dc0b-4541-8ae8-5db991db0d3e · outbound

This paper cites LLM4PQC - accurate and efficient synthesis of PQC cores by feedback-driven LLMs,.

Hardware Design and Security in the Era of Chiplets and LLMs LLM4PQC - accurate and efficient synthesis of PQC cores by feedback-driven LLMs,

Reference 67

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:24.953479Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:22.264260Z digest=sha256:559cfa54470203b0e66626d31a8058614983fe97ec1b1f78a9a3f7a30504a5b8

Observation 823dea83-b0fe-4fd5-82d6-f5ab4f65d0e1 · outbound

This paper cites LLM4SecurePQC: LLM-driven and side-channel resilient hardware synthesis of PQC cores,.

Hardware Design and Security in the Era of Chiplets and LLMs LLM4SecurePQC: LLM-driven and side-channel resilient hardware synthesis of PQC cores,

Reference 68

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:24.819028Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:22.342579Z digest=sha256:e66e81e68f34b83a17d5987e2cf383bf1c70987bcfb6a4fe6fee58c069234132

Observation f49f9f5c-f7d9-468d-8ffb-45d0f4a6eadf · outbound

This paper cites Graph neural networks for integrated circuit design, reliability, and security: Survey and tool,.

Hardware Design and Security in the Era of Chiplets and LLMs Graph neural networks for integrated circuit design, reliability, and security: Survey and tool,

Reference 69

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:24.668783Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:22.427532Z digest=sha256:3bfc806f14f2e69076dd4ec6cb456c86493e134a04571e2a7850366b5b830ce5

Observation a3a390e9-c3b7-413a-8895-5bb0950ed4a8 · outbound

This paper cites TrojanLoC: Fine-grained hardware Trojan detection from Verilog code,.

Hardware Design and Security in the Era of Chiplets and LLMs TrojanLoC: Fine-grained hardware Trojan detection from Verilog code,

Reference 70

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:22.492453Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:22.492453Z digest=sha256:719734b3c97feef777f62a07f1453bc5eccfdc162c4f497341a2ee7f76209610

Observation a3f4bbf6-95a0-45cf-8c28-cd8f71529c6c · outbound

This paper cites NetDeTox: Adversarial and efficient evasion of hardware-security GNNs via RL-LLM orchestration,.

Hardware Design and Security in the Era of Chiplets and LLMs NetDeTox: Adversarial and efficient evasion of hardware-security GNNs via RL-LLM orchestration,

Reference 71

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:24.495279Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:22.587719Z digest=sha256:5e09a6c22d562d979816b9c4498d67cc589d7eb9e0877540c04a3ee50f12f25c

Observation 596b3393-bc63-4202-910b-a7718bb178f9 · outbound

This paper cites TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion.

Hardware Design and Security in the Era of Chiplets and LLMs TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion

Reference 72

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:22.669056Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:22.669056Z digest=sha256:82a56129e649c2091e9e0029a53bad3a23ca31cf26f0e33332db4c8ed8c1a999

Observation b4d1be42-47ae-485a-b5ea-936c59467dad · outbound

This paper cites VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog.

Hardware Design and Security in the Era of Chiplets and LLMs VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog

Reference 73

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:22.805325Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:22.805325Z digest=sha256:f7d759f7d0655b35f90b18eafb3b68f94a3c8124419ecf2910cd7aca5b8269c7

Observation 80c254fc-6eda-4d6b-8c88-9eb7a5df8ae5 · outbound

This paper cites LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs.

Hardware Design and Security in the Era of Chiplets and LLMs LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 74

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:22.905355Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:22.905355Z digest=sha256:2b4406f67844d1d6044ebd458bad169c7c6e2827b0f558fdfa7fd7289d077b49

Observation a45f71e7-7366-43f9-957b-0d8b27b3b4f5 · outbound

This paper cites MARVEL: Multi-agent RTL vulnerability extraction using large language models,.

Hardware Design and Security in the Era of Chiplets and LLMs MARVEL: Multi-agent RTL vulnerability extraction using large language models,

Reference 75

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:22.981251Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:22.981251Z digest=sha256:7960b69c24dedc9e78a93841f178ecf38ab2f1f35c3866e35a869f0da0803518

Observation b73d2b68-1814-48f1-aafb-23ce83a8c049 · outbound

This paper cites FLAG: Finding line anomalies (in RTL code) with generative AI,.

Hardware Design and Security in the Era of Chiplets and LLMs FLAG: Finding line anomalies (in RTL code) with generative AI,

Reference 76

Resolution
verified fuzzy
raw_fallback, observed 2026-08-06T10:13:24.347268Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

source=pdf_text observed=2026-08-06T10:13:23.040038Z digest=sha256:ca97e4c57388a00a06068891a05e62f8d66489fbe493bd92922311a513df1871

Pith citing papers

No inbound Pith citation observations are available.