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REVIEW 2 major objections 4 minor 43 references

Flip-chip integrated superconducting qubits using electroplated bump bonds

T0 review · 2 major / 4 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read A flip-chip transmon using electroplated indium bumps reaches qubit quality factors around $10^6$, with the gold contact layer—not the indium—identified as the dominant loss source.

desk verdict Solid engineering demonstration that electroplated indium flip-chip bumps give transmons with Qi ~1e6; the Au-metal-air loss attribution is plausible but not fully proven for the qubit itself. read the letter →

arxiv 2608.07306 v1 pith:ELKUAKBL submitted 2026-08-07 quant-ph

Yen-An Shih , Rebecca Gharibaan , Barka Khan , Dhananjay Joshi , Siddharth Singh , Martijn F. S. Zwanenburg , Eugene Y. Huang , Nataliia Zhurbina
show 4 more authors
Figen Yilmaz Lukas Johannes Splitthoff Srijit Goswami Christian Kraglund Andersen
This is my paper · ORCID
classification quant-ph
keywords flip-chipintegrationelectroplatedindiumbumpssuperconductingtransmonqubitsurfacelossqualityfactor3Dhybridsemiconductor-superconductordevicesNbTiN
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Superconducting quantum processors are running out of room on a single chip, and connecting chips without adding loss is a key packaging problem. This paper shows that electroplated indium bumps, a fast and scalable bonding method, can form the superconducting connection of a transmon qubit while keeping internal quality factors around $10^6$. The transmon is split across two bonded substrates so that roughly half of the electric-field energy lives in each chip and almost none touches the indium bump. A step-by-step resonator study then points to the thin ex-situ gold film used to contact the indium as the main source of the remaining loss, not the bump bond or the electroplating process. That distinction matters because it isolates a specific, replaceable layer as the next target for improving coherence.

What carries the argument

The load-bearing object is the flip-transmon geometry: a transmon whose charge island is formed jointly by a pad on the bottom chip and a matching island on the top chip, galvanically connected through a square electroplated indium bump. Because the bump sits at a point of near-zero electric field, its surface energy participation is almost nil, and the field divides about equally between the two substrates. The second load-bearing element is the surface-participation model: finite-element simulations in which all bulk materials are lossless and the only lossy interfaces are the metal-air surfaces, each represented as a uniform 5 nm dielectric layer with $\varepsilon_r=10$. Comparing the simulated gold-metal-air participation ratio $P_{\mathrm{Au,MA}}$ to measured $Q_i$ values across resonators, flip-resonators, and transmons is what lets the paper separate loss at the bump bond from loss at the gold surface.

What would settle it

Fabricate a flip-transmon in which the gold film is removed from the capacitor surfaces (or deposited in-situ with the NbTiN) while keeping the electroplated indium bump, and measure its internal quality factor; the paper's model predicts a clear rise above roughly $10^6$, whereas a flat $Q_i$ would show that another interface governs the decay.

Watch

Extended reading notes

Core claim

The paper's central claim is that a three-dimensional transmon with an electroplated indium bump placed directly on the charge island can deliver $Q_i \sim 10^6$ while keeping the bump interface nearly loss-free. In this flip-transmon, the shunt capacitor is distributed between the two bonded chips: the simulated field participation is about 49\% in each silicon substrate and close to zero at the indium bump surface. Four qubits on two chips show internal quality factors mostly between $0.5\times10^6$ and $1.5\times10^6$. The qubits outperform coplanar-waveguide resonators fabricated through the same process, and resonators taken through the full electroplating-and-bonding sequence behave like gold-coated resonators rather than worse, indicating the electroplating itself is not the bottleneck. Adding the 5 nm gold layer lowers resonator quality factors, and selectively etching that gold layer away raises them above $10^6$; combining those measurements with finite-element surface-participation simulations places all three device classes on a common loss curve with an effective gold metal-air loss tangent between roughly $5\times10^{-2}$ and $10^{-1}$. The conclusion is that the gold-covered metal-air interface, not the indium bump, limits the measured coherence.

Load-bearing premise

The loss attribution assumes the only significant lossy interfaces are the exposed metal-air surfaces, modeled as a uniform 5 nm dielectric film; if the metal-substrate or substrate-air interfaces lose energy at a comparable rate, the gold layer may not be the true dominant loss channel.

Editorial extensions

If this is right

  • Electroplated indium bump bonding is demonstrated as compatible with $Q_i\sim10^6$ transmons, making it a viable interconnect for multi-chip superconducting processors.
  • Because the qubit field barely touches the bump, the architecture can tolerate loss at the bump interface while field participation in each substrate is engineered, which suits hybrid semiconductor-superconductor integration.
  • The dominant loss is the ex-situ gold metal-air interface, so replacing that gold layer (for example by in-situ deposition) is the immediate route to higher coherence in this platform.
  • The electroplating process itself does not add measurable loss in the tested resonators, so bump height and array size can be scaled for larger chip separations without an added coherence penalty.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • We would extend the paper's logic by predicting that a flip-transmon built with an in-situ encapsulated or entirely removed gold layer should push $Q_i$ substantially above $10^6$; that is a direct test the paper has not performed.
  • The near-equal field sharing between substrates could serve as a design rule for hybrid qubits: place the lossy semiconductor or quantum-dot material on one substrate where its participation is engineered away from the Josephson junction, rather than trying to make the semiconductor lossless.
  • One open question the data leave is whether the gold loss tangent inferred here is intrinsic to gold or caused by the ex-situ transfer and surface contamination; surface analysis of the Au-NbTiN interface could separate those possibilities.
  • The process-split resonator methodology used here transfers directly to other bump metals and bonding schemes, offering a general way to attribute qubit loss to interconnect steps versus surface preparations.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The paper reports a flip-chip transmon architecture in which electroplated indium bumps provide the galvanic connection between two silicon substrates, with the qubit electric field split nearly equally between the chips and low participation at the indium-bump interface. Four transmons on two identically processed chips show internal quality factors around 0.5–1.4×10^6, establishing that electroplated indium interconnects are compatible with reasonably high-coherence superconducting circuits. To identify the dominant loss, the authors fabricate coplanar-waveguide resonators at successive process steps (bare NbTiN, NbTiN+Au, full flip-chip processing) and measure their internal quality factors; an Au-removal control shows a large improvement in resonator Q. Finite-element participation-ratio simulations are then used to argue that the exposed gold metal-air interface is the dominant loss channel, both for resonators and for the qubits.

Significance. The fabrication result is significant and well supported: qubit quality factors near 10^6 are reproducible across two chips, and the resonator process study with a Au-removal control is a clean, quantitative demonstration that the ex-situ gold layer dominates loss in the coplanar waveguide resonators. If the qubit-level attribution were also established, the paper would provide clear guidance for flip-chip and hybrid integration, and the data/code availability statements are commendable. However, the central qubit-level loss claim is not uniquely determined by the presented evidence, because the qubit stores 98.6% of its field energy in the substrates, which are assumed lossless in the simulations. This gap, together with an internal inconsistency in the quoted loss tangent, prevents me from endorsing the primary-loss attribution in its current form.

major comments (2)
  1. [Appendix D, Table II] The claim that the Au metal-air interface is the primary qubit loss channel is underdetermined. The simulations in Appendix D assume all materials except the 5 nm metal-air layers are lossless, yet Table II shows that 98.6% of the transmon electric energy resides in the silicon substrates, with the remainder split equally between top and bottom chips. The Au-removed Step 2 resonators reach Qi values above 1e6 with roughly 92% substrate participation; this bounds the substrate loss tangent at approximately 1e-6. Applying that same substrate loss tangent to the transmon's 98.6% substrate participation gives a substrate-limited qubit Qi of about 1e6, equal to the measured values. Thus the measured qubit lifetimes are fully consistent with substrate-dominated loss, and the Au-removal experiment, while conclusive for the resonators, does not by itself demonstrate that the qubit is Au-limited. Please add a quantitative upper bound on substrate and substrate-air losses from the no-Au resonators, or soften the qubit-level attribution accordingly.
  2. [Section IV, Fig. 4] The quoted effective Au MA loss tangent range is inconsistent with the transmon data. From Table II, the flip-transmon has p_Au,MA = 1.5×10^-6; with the measured Qi ≈ 1×10^6, a purely Au-MA-limited qubit would require tanδ_MA ≈ 0.67, not the quoted 5×10^-2 to 10^-1. With tanδ = 0.05 or 0.1, the predicted qubit Qi is 1.3×10^7 or 6.7×10^6, respectively, far above the measured values. Moreover, the three device classes in Fig. 4 do not collapse onto a single effective tanδ when their Table II participations are combined with the measured Qi values. This quantitative inconsistency must be resolved before the participation analysis can support the conclusion that the Au metal-air interface dominates the qubit decay rate.
minor comments (4)
  1. [Table II] The header 'Au MA (×10−4%)' makes the physical participation fraction difficult to read; please report the dimensionless fraction directly (e.g., 1.5×10^-6) alongside the percentage form.
  2. [Fig. 4] The legend prints 'tan MA = 1×10^2', '1×10^1', and '5×10^1', which appear to be missing negative exponents; as printed these values contradict the text's quoted loss-tangent range and should be corrected.
  3. [Appendix C] The term '6-1-1 vector magnet' is undefined; please specify the magnet configuration or replace it with a standard description.
  4. [Data availability] References [40] and [41] contain no repository identifiers; include DOIs or archive links so the data and code are actually locatable.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: Au-loss claim is independently supported by the Au-removal control; participation simulations serve as a consistency check, not as a fitted prediction.

full rationale

The central claims—electroplated indium bumps are compatible with qubit quality factors near 1e6 and the Au metal-air interface is the dominant loss channel—do not reduce by construction to the paper's inputs. The Au-loss attribution rests primarily on an independent control experiment: a subset of Step 2 resonators had the Au film removed and their internal quality factors increased substantially, reaching values above 1e6 (Fig. 3(f)). This intervention does not rely on the participation model and directly demonstrates that Au introduces the dominant loss in those resonators. The participation simulations in Appendix D are used as a consistency check rather than as a fitted prediction: the energy participation ratios are computed from geometry via Eqs. (D1)-(D2) with all materials assumed lossless, and the measured quality factors are compared to a family of assumed loss-tangent lines (tan delta_MA = 5e-2 to 1e-1) in Fig. 4. The text says the data are 'broadly consistent' with this range, not that tan delta was fitted to the qubit data and then renamed as a prediction. The main modeling limitation is that Appendix D neglects metal-substrate and substrate-air interfaces and assumes Au MA dominance based on the resonator study; because the qubit stores 98.6% of its field energy in the substrates (Table II), the quantitative transfer of the Au-loss attribution from resonators to qubits is underdetermined. That is a correctness or modeling risk, not circularity: there is no equation by which the qubit result equals the simulation input, and the Au-removal control provides external evidence for the Au-loss mechanism. The self-citations present (Refs. [26] and [42]) are fabrication-process references (PECVD deposition rate and the established qubit junction process) and are not load-bearing for the loss-attribution argument. No self-citation chain, imported uniqueness theorem, ansatz-smuggling citation, or renaming of a known result appears. The derivation chain is therefore self-contained with respect to circularity.

Assumptions & free parameters 3 free parameters · 3 assumptions · 0 invented entities

The paper introduces no new physical entities. The loss analysis relies on a small number of model parameters (Au MA layer thickness, permittivity, and loss tangent range) that are chosen rather than independently measured, plus the simplifying assumption that all loss is concentrated at metal-air interfaces.

free parameters (3)
  • Au metal-air interface loss tangent (tan delta_MA) = 5e-2 to 1e-1
    In Fig. 4 the measured data are compared to lines for this range; the range is chosen post hoc to bracket the data, not independently measured.
  • Au MA interface layer thickness = 5 nm
    Chosen in Appendix D for participation simulations; affects the computed participation ratios.
  • Au MA interface effective relative permittivity = 10
    Assigned in Appendix D for the surface layer in simulations; not derived from measurement.
assumptions (3)
  • domain assumption All bulk materials (NbTiN, Si, In) and non-MA interfaces are lossless; only metal-air interfaces contribute to microwave loss.
    Appendix D states this simplification, justified by the resonator process study but not directly measured.
  • ad hoc to paper The MA interface can be represented as a uniform 5 nm dielectric layer with epsilon_r=10 in the electromagnetic simulation.
    Appendix D; these parameters are chosen, not measured, and affect the computed participation ratios.
  • domain assumption The flip-chip bond provides a galvanic superconducting connection between the two substrates.
    Validated indirectly through resonator magnetic-field response in Appendix C, but the contact resistance is not directly measured.

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Pith. "Pith review of Flip-chip integrated superconducting qubits using electroplated bump bonds." pith.science (2026). https://pith.science/paper/ELKUAKBL

@misc{pith2026260807306,
  author       = {Pith},
  title        = {Pith review of: Flip-chip integrated superconducting qubits using electroplated bump bonds},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ELKUAKBL}},
  note         = {Machine review of arXiv:2608.07306}
}
abstract

Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around $10^6$. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.

Figures

Figures reproduced from arXiv: 2608.07306 by the authors.

Figure 1
Figure 1. FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. (b) and (c). We later also remove the Au film from a subset of Step 2 resonators using the same Au wet etch used to define the transmon islands and resonators on the flip-transmon chips. Finally, Step 3 includes the full additional processing required for the 3D-integrated de￾vices, including the initial deposition and patterning of the SiOx hard stops, electroplating of the indium bumps, and bonding to a blank top … view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: (a.7). For the top chip, a high-resistivity silicon wafer is first cleaned in nitric acid for 7 minutes, followed by a 6 minute dip in a (40%) HF solution. The wafer then un￾dergoes the same NbTiN and Au deposition processes used for the bottom chip, as shown in [PITH…
Figure 7
Figure 7. Figure 7: FIG. 7 [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]
Figure 6
Figure 6. Figure 6: FIG. 6 [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 8
Figure 8. Figure 8: FIG. 8 [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]

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Reviewed August 10, 2026 · model on record in the stance chip above.