Pith. sign in

REVIEW 4 major objections 6 minor 38 references

LGNNIC: Acceleration of Large-Scale GNN Training using SmartNICs

T0 review · 4 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Offloading neighbor sampling and quantization to SmartNICs at the memory node reduces bytes sent over the network and accelerates end-to-end GNN training, with measured speedups up to 62.4x for socket-based and 17.5x for DMA-based transfer.

desk verdict Solid per-node offloading proof-of-concept, but the headline speedups are intra-card PCIe transfers, not inter-node network effects, so the central scaling claim is unproven. read the letter →

arxiv 2608.07733 v1 pith:5BQ4U5IM submitted 2026-08-07 cs.DC cs.AIcs.ARcs.LGcs.PF

Liad Gerstman , Aditya Dhakal , Dejan Milojicic , Avi Mendelson This is my paper · ORCID
classification cs.DCcs.AIcs.ARcs.LGcs.PF
keywords GraphNeuralNetworksneighborsamplingSmartNICoffloadingquantizationdistributedGNNtrainingnetworkbottleneckBlueField-2DPUDOCA-DMA
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Large-scale GNN training on distributed graphs is bottlenecked by the network: sampled mini-batches must cross from remote memory to compute nodes. This paper claims that moving two preprocessing steps—neighbor sampling and tensor quantization—onto SmartNICs co-located with remote memory nodes shrinks the data volume enough to overcome the SmartNIC's slower compute. In a single-pair proof of concept, the paper reports up to 62.4x and 17.5x total training speedups with socket-based and DOCA-DMA synchronization, respectively, with the gains coming mostly from reduced transaction time. Quantization alone adds up to 3.6x (sockets) and 1.3x (DMA) speedup, with test accuracy changing by no more than about one percentage point. If the result transfers to full multi-node deployments, it would make remote-memory GNN training practical without changing the graph or the model.

What carries the argument

The load-bearing machinery is a SmartNIC-side preprocessing pipeline that runs neighbor sampling and FP16 quantization in the remote node's DRAM, followed by a chunked DMA synchronization protocol between the SmartNIC and the compute node's host memory. The protocol exists because DOCA-DMA buffers are capped at 1 MB and cannot be reallocated without reinitializing the process, so tensors are split into header-bearing chunks and transferred with ACK-based ordering; the design allows the next mini-batch to be sampled while the current one is in transit. The sampling step is the primary volume reducer: for hyperparameters such as [25,10], each two-layer computational tree is pruned to at most 25 then 10 neighbors per node, which shrinks both the feature tensor and the adjacency tensor. Quantization then halves feature bytes but is secondary. The paper's argument is that reduced data volume, not raw sampling speed, is what determines end-to-end training time in network-bound settings.

What would settle it

Run LGNNIC on a graph split across two or more remote memory nodes with sampling hyperparameters that cross partition boundaries, and measure end-to-end training time and bytes transferred per mini-batch against the same graph stored on a single node. If the multi-node version's per-batch transfer volume or total time does not improve relative to CPU-side sampling on the compute node, the central claim fails.

Watch

Extended reading notes

Core claim

The paper's central claim is that the communication bottleneck in distributed GNN training can be attacked at the memory side rather than the compute side. LGNNIC stores graph partitions on remote-memory nodes, each carrying a BlueField-2 SmartNIC, and runs GraphSAGE-style neighbor sampling plus FP32-to-FP16 feature quantization on that SmartNIC before any tensor crosses the network. Because sampling prunes each mini-batch's computational tree and quantization halves the feature tensor bytes, the bytes-per-batch drop dramatically, and transaction time falls even though the SmartNIC itself samples 2–10x slower than the host CPU. Measured on Reddit, OGBN-Products, and OGBN-MAG with both a high-overhead socket mechanism and a low-overhead DOCA-DMA mechanism, the paper reports total training speedups up to 62.4x (sockets) and 17.5x (DOCA-DMA) for sampling, and additional 3.6x/1.3x speedups from quantization. The authors frame this as establishing per-node SmartNIC offloading as a feasible building block for larger distributed systems.

Load-bearing premise

The proof-of-concept keeps all sampled neighbors inside the one remote node's graph partition, so the SmartNIC never has to fetch neighbors from other partitions; if a real distributed graph makes cross-partition neighbor fetches necessary, the measured speedups would not automatically carry over.

Editorial extensions

If this is right

  • In network-bound settings, moving sampling to the memory side can yield larger total speedups than improving sampling throughput on the compute node.
  • The speedup is greatest for graphs with high edge-to-node ratios and for high-overhead transports like Ethernet, because transfer volume dominates there.
  • Quantizing feature tensors from FP32 to FP16 on the SmartNIC is nearly free in accuracy while cutting transfer time, and it can be stacked on top of sampling.
  • The DOCA-DMA chunking and ACK overhead shows that fixed small DMA buffer limits are a real constraint; increasing the buffer size or allowing reallocation would likely make the DMA-based speedups even larger.
  • Commonly used sampling hyperparameters that barely change test accuracy are precisely the ones that deliver the largest communication reductions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If cross-partition neighbor sampling is handled by fetching only the missing boundary nodes, the per-node sampling-time penalty may still be worthwhile when network overhead is high, but the 62.4x number should not be extrapolated to a full multi-node deployment without direct measurement.
  • The same memory-side reduction principle could apply to other per-batch preprocessing operators, such as feature normalization, deduplication, or subgraph sampling, as long as they are stateless enough to fit in the SmartNIC's memory budget.
  • A testable extension is to vary the DOCA-DMA buffer size in simulation; the paper's own numbers imply that removing the 1 MB chunking and the extra host-side copy would shift the DOCA-DMA speedups toward the socket-based ceiling.
  • Comparing against a CPU-side baseline that also quantizes to FP16 before transmission would isolate how much of the speedup comes from the SmartNIC's location rather than from the data reduction itself.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. This manuscript proposes LGNNIC, a SmartNIC-based architecture for distributed GNN training in which remote memory nodes offload neighbor sampling and FP32-to-FP16 tensor quantization to co-located BlueField-2 SmartNICs before mini-batches are transferred to compute nodes. The authors implement a proof-of-concept on an NVIDIA A100X converged card, with graph data in BlueField-2 DRAM, and compare a DOCA-DMA-based synchronization mechanism with a socket-based benchmark. Across Reddit, OGBN-Products, and OGBN-MAG, they report end-to-end training speedups from neighbor sampling up to 62.4x (Sockets) and 17.5x (DOCA-DMA), and additional quantization speedups, with small accuracy changes. The paper explicitly restricts the PoC to a single remote-memory-node/compute-node pair and defers cross-partition sampling, multi-node routing, and peer-to-peer DOCA-RDMA over Ethernet to future work.

Significance. The work addresses a real bottleneck in disaggregated GNN training, and the idea of pushing sampling and quantization onto the network device is well motivated. The paper's strengths are its careful phase-level profiling, use of three standard workloads with several sampling configurations, two synchronization mechanisms, repeated accuracy runs, and transparent discussion of BlueField-2/DOCA limitations such as the 1 MB DOCA-DMA buffer constraint and CPU-affinity memory blowup. If the speedups were measured on an actual inter-node network, the results would be an important engineering contribution. As it stands, however, the headline claims concern network-congestion relief while the experiments exercise only an intra-card PCIe path, so the significance depends on a generalization that is not demonstrated.

major comments (4)
  1. [§5.1, Fig. 3, §8] The PoC never transmits data over an inter-node network. Graph data is stored in BlueField-2 DRAM and transferred to the host CPU over the A100X's internal PCIe path, using DOCA-DMA or sockets; no Ethernet or InfiniBand link between a remote memory node and a compute node is involved. Consequently, the up to 62.4x and 17.5x speedups in Table 2 measure reductions in PCIe transfer volume and per-chunk protocol overhead, not relief of network congestion. The paper's own conclusion defers peer-to-peer DOCA-RDMA over Ethernet to future work, confirming that the architecture's network data path is unmeasured. The abstract and introduction should be revised to claim acceleration of the local data-movement path, or a real inter-node experiment must be added.
  2. [§5.3.2, Table 2] The headline 'total training speedup' compares a heavily sampled remote configuration with a minimally sampled remote configuration ([-1,-1] or [-1,256]) under the same transfer mechanism. It is not a comparison against a conventional local CPU-GPU pipeline or against a remote configuration that transfers full graph data without SmartNIC sampling. For example, Reddit DOCA-DMA [25,10] total speedup exceeds its transaction speedup (17.46x vs 5.10x), so the end-to-end gain includes reductions in preprocessing and GPU training due to sampling itself, not only communication reduction. The paper should present a baseline that isolates the SmartNIC-offloading contribution and should qualify the speedups accordingly.
  3. [§5.2, §5.3.2] The socket-based mechanism is deliberately configured with 1 MB buffers and ACK-based chunking, and it runs over the same intra-card path; the paper calls it a benchmark for a 'high-overhead network' such as Ethernet, but no Ethernet path is measured. Thus the 62.4x Sockets result is partly an artifact of an artificially constrained local socket implementation and cannot be used as evidence about actual network behavior. The text should either measure a real network protocol or present the Sockets numbers only as a protocol-overhead comparison within the PoC.
  4. [§5.1, §8] The paper acknowledges that the PoC isolates effects 'without introducing cross-partition sampling, remote-node coordination, or multi-node routing overheads' and leaves multi-node scaling to future work. This is an honest limitation, but it means the proposed distributed architecture, in which graph partitions require cross-partition neighbor access, is not validated. The central claim that LGNNIC is an 'inter-node system architecture' is therefore unsupported by the evidence; the paper should either add a multi-node experiment, even with two nodes, or restrict the claim to single-node SmartNIC offloading.
minor comments (6)
  1. [Abstract vs. Table 2] The abstract's 'up to 73.6x and 5.1x' transaction speedups do not match Table 2, which reports transaction speedups up to 472.08x for Sockets and 47.65x for DOCA-DMA; please reconcile these numbers.
  2. [Table 3] The paper reports average test accuracy over four runs without standard deviations or statistical tests, so claims of 'small changes in test accuracy' are not fully supported; adding variances would strengthen the accuracy discussion.
  3. [Fig. 5] The text says some non-negligible transfer times are omitted from the figure for space, but all transfers are included in the totals; a supplementary table listing all per-tensor transfer times would improve reproducibility.
  4. [§6.1] The expectations about larger graphs and high-overhead networks are speculative and not supported by the PoC data; they should be clearly marked as hypotheses rather than conclusions.
  5. [§5.3.1] When describing the memory exhaustion for [-1,-1] on the SmartNIC, the paper states that the corresponding runs did not complete and were excluded; specifying the number of workers and the observed memory limit would help readers reproduce the failure mode.
  6. [§5.4.2, Table 4] Several DOCA-DMA execution speedups from quantization are close to 1.0 (e.g., 1.02, 1.03, 1.05), so the statement that quantization 'consistently delivers significant speedups in total training time' overstates the low-overhead-path results; the text should distinguish statistically meaningful gains from marginal ones.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity; the reported speedups are measured ratios, and the only author-overlap citation is non-load-bearing related work.

full rationale

The paper's central claims are empirical timing measurements, not derived predictions. The speedups in Table 2 compare measured total transaction and training times under extensive neighbor sampling against the same mechanisms with minimal sampling, and the quantization speedups in Table 4 compare measured FP32 versus FP16 transfer and execution times with sampling hyperparameters held constant. These are ratios of recorded timings, not fitted parameters, and they are not forced by definition: sampling reduces data volume, but whether the reduction in transfer time outweighs the SmartNIC's slower preprocessing is an empirical question that the paper answers by measurement. The PoC limitation that no actual inter-node network is exercised (Section 5.1, using a converged A100X card with transfers over PCIe or sockets) is an external-validity concern about whether the measured local data-movement speedups transfer to a real distributed setting; it is not a circularity. The only author-overlap citation is Farview [30], which includes co-author Milojicic and is mentioned in Related Work as prior offloading work; it is not load-bearing for any claim or derivation in this paper. There are no uniqueness theorems, no ansatz smuggled in via citation, and no renaming of known results. The work is benchmarked against standard PyG workloads and datasets, and its conclusions rest on controlled measurements rather than on self-referential logic. Accordingly, no circular step is identified; the score reflects only the minor, non-load-bearing self-citation in related work.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central claim rests on hardware assumptions about SmartNIC memory, I/O paths, and the representativeness of the single-node PoC, not on fitted parameters or invented entities. No mathematical derivation is attempted; the experiments carry the argument. The main untested premise is that the single-node PoC generalizes to multi-node graphs.

assumptions (4)
  • domain assumption Graph data and sampling state fit within BlueField-2 DRAM.
    The architecture requires the SmartNIC to store and sample the graph; Section 5.3.1 reports memory exhaustion for unconstrained sampling with multiple workers, making this assumption load-bearing.
  • ad hoc to paper A single remote-node PoC with PCIe paths approximates an inter-node distributed system.
    Section 5.1 states the PoC 'differs from the proposed system' and omits cross-partition sampling, remote-node coordination, and multi-node routing; the headline speedups depend on this approximation.
  • ad hoc to paper Socket-based transfer with 1 MB buffers represents a high-overhead network bottleneck.
    Section 5.2 sets the Sockets buffer to 1 MB for consistency with DOCA-DMA and uses it as a high-overhead benchmark; no real Ethernet or InfiniBand path is measured.
  • domain assumption Neighbor sampling preserves accuracy sufficiently under the tested hyperparameters.
    Table 3 checks accuracy for the three datasets, but the architecture assumes the chosen sampling hyperparameters are representative for larger graphs and other workloads.

how reviews work

0 comments
Cite this review

Pith. "Pith review of LGNNIC: Acceleration of Large-Scale GNN Training using SmartNICs." pith.science (2026). https://pith.science/paper/5BQ4U5IM

@misc{pith2026260807733,
  author       = {Pith},
  title        = {Pith review of: LGNNIC: Acceleration of Large-Scale GNN Training using SmartNICs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5BQ4U5IM}},
  note         = {Machine review of arXiv:2608.07733}
}
read the original abstract

Graph Neural Networks (GNNs) are widely used across domains such as natural sciences, social network analysis, chip design, and recommendation systems. However, as graph sizes grow, storing and processing them entirely on a single-node CPU-GPU system becomes increasingly impractical. A promising approach is to distribute the graph across multiple remote memory nodes, though this introduces a major bottleneck: inter-node network congestion during training. To address this, we propose LGNNIC, a novel inter-node system architecture that leverages SmartNICs co-located with remote memory nodes-a configuration already available in modern systems-to reduce communication overhead in distributed GNN training. LGNNIC offloads key preprocessing tasks to SmartNICs, reducing the volume of data transferred to computational (training) nodes and alleviating network congestion. We introduce two complementary techniques executed on the SmartNICs during the preprocessing phase: Neighbor Sampling, which performs mini-batch sampling, and Quantization of the sampled batches. To evaluate LGNNIC under different communication infrastructures, we designed both an optimized low-overhead DMA-based synchronization mechanism and a high-overhead socket-based alternative used as a benchmark. We evaluate the core SmartNIC offloading mechanisms across standard GNN workloads and sampling hyperparameters using a proof-of-concept (PoC) system comprising one remote-memory node with an NVIDIA BlueField-2 SmartNIC and one compute node with an A100 GPU. Both Neighbor Sampling and Quantization on the remote node demonstrated substantial training speedups in most configurations. Neighbor Sampling achieved up to 62.4x and 17.5x speedups with Sockets and DOCA-DMA, respectively, primarily due to reduced data transaction time. Quantization provided additional speedups of up to 3.6x and 1.3x, respectively, by reducing data transfer.

Figures

Figures reproduced from arXiv: 2608.07733 by the authors.

Figure 1
Figure 1. Average execution times for key training phases on a baseline CPU-GPU node across all datasets. [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. LGNNIC, our proposed SmartNIC-based system architecture, comprises multiple computational (local) nodes and [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Our proof-of-concept system was designed to measure the execution times of key training phases using either our [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Impact of in-layer Neighbor Sampling on preprocessing performance, comparing execution on the host CPU versus [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Average execution time comparison across all datasets. Key mini-batch training phases are analyzed using various [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

38 extracted references · 23 canonical work pages

  1. [1]

    Semi-supervised classification with graph convolu- tional networks,

    T. N. Kipf and M. Welling, “Semi-supervised classification with graph convolu- tional networks, ” 2017

    work page 2017

  2. [2]

    Graph attention networks,

    P. Veličković, G. Cucurull, A. Casanova, A. Romero, P. Liò, and Y. Bengio, “Graph attention networks, ” 2018

    work page 2018

  3. [3]

    Inductive representation learning on large graphs,

    W. Hamilton, Z. Ying, and J. Leskovec, “Inductive representation learning on large graphs, ” inAdvances in Neural Information Processing Systems, I. Guyon, U. V. Luxburg, S. Bengio, H. Wallach, R. Fergus, S. Vish- wanathan, and R. Garnett, Eds., vol. 30. Curran Associates, Inc., 2017. [Online]. Available: https://proceedings.neurips.cc/paper_files/paper/2...

    work page 2017

  4. [4]

    How powerful are graph neural networks?

    K. Xu, W. Hu, J. Leskovec, and S. Jegelka, “How powerful are graph neural networks?” 2019

    2019

  5. [5]

    Ogb-lsc: A large- scale challenge for machine learning on graphs,

    W. Hu, M. Fey, H. Ren, M. Nakata, Y. Dong, and J. Leskovec, “Ogb-lsc: A large- scale challenge for machine learning on graphs, ”arXiv preprint arXiv:2103.09430, 2021

    arXiv 2021

  6. [6]

    NVIDIA, https://docs.nvidia.com/doca/sdk/doca+dma/index.html, 2024

    work page 2024

  7. [7]

    Fast graph representation learning with PyTorch Geo- metric,

    M. Fey and J. E. Lenssen, “Fast graph representation learning with PyTorch Geo- metric, ” inICLR Workshop on Representation Learning on Graphs and Manifolds, 2019

    work page 2019

  8. [8]

    Deep graph library: A graph- centric, highly-performant package for graph neural networks,

    M. Wang, D. Zheng, Z. Ye, Q. Gan, M. Li, X. Song, J. Zhou, C. Ma, L. Yu, Y. Gai, T. Xiao, T. He, G. Karypis, J. Li, and Z. Zhang, “Deep graph library: A graph- centric, highly-performant package for graph neural networks, ” 2020

    work page 2020

Show all 38 references
  1. [9]

    Cluster-gcn: An efficient algorithm for training deep and large graph convolutional networks,

    W.-L. Chiang, X. Liu, S. Si, Y. Li, S. Bengio, and C.-J. Hsieh, “Cluster-gcn: An efficient algorithm for training deep and large graph convolutional networks, ” ser. KDD ’19. New York, NY, USA: Association for Computing Machinery, 2019, p. 257–266. [Online]. Available: https:/...

    2019

  2. [10]

    Smartsage: Training large-scale graph neural networks using in-storage processing architectures,

    Y. Lee, J. Chung, and M. Rhu, “Smartsage: Training large-scale graph neural networks using in-storage processing architectures, ” 2022

    2022

  3. [11]

    Open graph benchmark: Datasets for machine learning on graphs,

    W. Hu, M. Fey, M. Zitnik, Y. Dong, H. Ren, B. Liu, M. Catasta, and J. Leskovec, “Open graph benchmark: Datasets for machine learning on graphs, ”arXiv preprint arXiv:2005.00687, 2020

    2005 arXiv

  4. [12]

    Improving the speed of neural networks on cpus,

    V. Vanhoucke, A. Senior, and M. Z. Mao, “Improving the speed of neural networks on cpus, ” inDeep Learning and Unsupervised Feature Learning Workshop, NIPS 2011, 2011

    2011

  5. [13]

    Binarized neural networks,

    I. Hubara, M. Courbariaux, D. Soudry, R. El-Yaniv, and Y. Bengio, “Binarized neural networks, ” inAdvances in Neural Information Processing Systems, D. Lee, M. Sugiyama, U. Luxburg, I. Guyon, and R. Garnett, Eds., vol. 29. Curran Associates, Inc., 2016. [Online]. Available: ht...

    2016

  6. [14]

    Deep compression: Compressing deep neural network with pruning, trained quantization and huffman coding,

    S. Han, H. Mao, and W. J. Dally, “Deep compression: Compressing deep neural network with pruning, trained quantization and huffman coding, ” in4th International Conference on Learning Representations, ICLR 2016, San Juan, Puerto Rico, May 2-4, 2016, Conference Track Proceeding...

    2016

  7. [15]

    Quantizing deep convolutional networks for efficient inference: A whitepaper,

    R. Krishnamoorthi, “Quantizing deep convolutional networks for efficient inference: A whitepaper, ”CoRR, vol. abs/1806.08342, 2018. [Online]. Available: http://arxiv.org/abs/1806.08342

    2018 arXiv

  8. [16]

    Tango: re-thinking quantization for graph neural network training on gpus,

    S. Chen, D. Zheng, C. Ding, C. Huan, Y. Ji, and H. Liu, “Tango: re-thinking quantization for graph neural network training on gpus, ” inProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, ser. SC ’23. New York, NY, USA:...

    2023

  9. [17]

    Approximation- and quantization- aware training for graph neural networks,

    R. Novkin, F. Klemme, and H. Amrouch, “Approximation- and quantization- aware training for graph neural networks, ”IEEE Transactions on Computers, vol. 73, no. 2, pp. 599–612, 2024

    2024

  10. [18]

    Low-bit quantization for deep graph neural networks with smoothness-aware message propagation,

    S. Wang, B. Eravci, R. Guliyev, and H. Ferhatosmanoglu, “Low-bit quantization for deep graph neural networks with smoothness-aware message propagation, ” inProceedings of the 32nd ACM International Conference on Information and Knowledge Management, ser. CIKM ’23. New York, NY...

    2023

  11. [19]

    NVIDIA BLUEFIELD-2 DPU Data Center Infrastructure on a Chip,

    NVIDIA, “NVIDIA BLUEFIELD-2 DPU Data Center Infrastructure on a Chip, ” https://resources.nvidia.com/en-us-accelerated-networking-resource- library/bluefield-2-dpu-datasheet, NVIDIA, 2021

    2021

  12. [20]

    Nvidia doca,

    ——, “Nvidia doca, ” https://developer.nvidia.com/networking/doca, NVIDIA De- veloper, 2024, accessed: 2024-01-11

    2024

  13. [21]

    Stochastic training of graph convolutional networks with variance reduction,

    J. Chen, J. Zhu, and L. Song, “Stochastic training of graph convolutional networks with variance reduction, ” 2018. [Online]. Available: https://arxiv.org/ abs/1710.10568

    2018 arXiv

  14. [22]

    Graph convolutional neural networks for web-scale recommender systems,

    R. Ying, R. He, K. Chen, P. Eksombatchai, W. L. Hamilton, and J. Leskovec, “Graph convolutional neural networks for web-scale recommender systems, ” inProceedings of the 24th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining, ser. KDD ’18. New York, NY, ...

    2018

  15. [23]

    Fastgcn: Fast learning with graph convolutional networks via importance sampling,

    J. Chen, T. Ma, and C. Xiao, “Fastgcn: Fast learning with graph convolutional networks via importance sampling, ”CoRR, vol. abs/1801.10247, 2018. [Online]. Available: http://arxiv.org/abs/1801.10247

    2018 arXiv

  16. [24]

    Adaptive sampling towards fast graph representation learning,

    W. Huang, T. Zhang, Y. Rong, and J. Huang, “Adaptive sampling towards fast graph representation learning, ” inAdvances in Neural Information Processing Systems, S. Bengio, H. Wallach, H. Larochelle, K. Grauman, N. Cesa-Bianchi, and R. Garnett, Eds., vol. 31. Curran Associates,...

    2018

  17. [25]

    Layer-dependent importance sampling for training deep and large graph convolutional networks,

    D. Zou, Z. Hu, Y. Wang, S. Jiang, Y. Sun, and Q. Gu, “Layer-dependent importance sampling for training deep and large graph convolutional networks, ” inAdvances in Neural Information Processing Systems, H. Wallach, H. Larochelle, A. Beygelzimer, F. d'Alché-Buc, E. Fox, and R. ...

    2019

  18. [26]

    Graphsaint: Graph sampling based inductive learning method,

    H. Zeng, H. Zhou, A. Srivastava, R. Kannan, and V. K. Prasanna, “Graphsaint: Graph sampling based inductive learning method, ”ArXiv, vol. abs/1907.04931,

    1907 arXiv

  19. [27]

    Ripple walk training: A subgraph-based training framework for large and deep graph neural network,

    J. Bai, Y. Ren, and J. Zhang, “Ripple walk training: A subgraph-based training framework for large and deep graph neural network, ” in2021 International Joint Conference on Neural Networks (IJCNN), 2021, pp. 1–8

    2021

  20. [28]

    Fast random walk with restart and its applications,

    H. Tong, C. Faloutsos, and J.-y. Pan, “Fast random walk with restart and its applications, ” inSixth International Conference on Data Mining (ICDM’06), 2006, pp. 613–622

    2006

  21. [29]

    Simplifying graph convolutional networks,

    F. Wu, A. Souza, T. Zhang, C. Fifty, T. Yu, and K. Weinberger, “Simplifying graph convolutional networks, ” inProceedings of the 36th International Conference on Machine Learning, ser. Proceedings of Machine Learning Research, K. Chaudhuri and R. Salakhutdinov, Eds., vol. 97. ...

    2019

  22. [30]

    Farview: Disaggregated memory with operator off-loading for database engines,

    D. Korolija, D. Koutsoukos, K. Keeton, K. Taranov, D. Milojičić, and G. Alonso, “Farview: Disaggregated memory with operator off-loading for database engines, ” 2021

    2021

  23. [31]

    DGCL: An efficient communication library for distributed GNN training,

    Z. Cai, X. Yan, Y. Wu, K. Ma, J. Cheng, and F. Yu, “DGCL: An efficient communication library for distributed GNN training, ” inProceedings of the Sixteenth European Conference on Computer Systems, ser. EuroSys ’21. New York, NY, USA: Association for Computing Machinery, 2021, ...

    2021

  24. [32]

    Sequential aggregation and rematerialization: Distributed full- batch training of graph neural networks on large graphs,

    H. Mostafa, “Sequential aggregation and rematerialization: Distributed full- batch training of graph neural networks on large graphs, ”arXiv preprint arXiv:2111.06483, 2022. [Online]. Available: https://arxiv.org/abs/2111.06483

    2022 arXiv

  25. [33]

    GNNear: Accelerating full-batch training of graph neural networks with near-memory processing,

    Z. Zhou, C. Li, X. Wei, X. Wang, and G. Sun, “GNNear: Accelerating full-batch training of graph neural networks with near-memory processing, ”arXiv preprint LGNNIC: Acceleration of Large-Scale GNN Training using SmartNICs arXiv:2111.00680, 2022. [Online]. Available: https://ar...

    2022 arXiv

  26. [34]

    Efficient neighbor- sampling-based gnn training on cpu-fpga heterogeneous platform,

    B. Zhang, S. R. Kuppannagari, R. Kannan, and V. Prasanna, “Efficient neighbor- sampling-based gnn training on cpu-fpga heterogeneous platform, ” in2021 IEEE High Performance Extreme Computing Conference (HPEC), 2021, pp. 1–7

    2021

  27. [35]

    Hardware acceleration of sampling algorithms in sample and aggregate graph neural networks,

    Y. Gui, B. Wei, W. Yuan, and X. Jin, “Hardware acceleration of sampling algorithms in sample and aggregate graph neural networks, ”arXiv preprint arXiv:2209.02916, 2022. [Online]. Available: https://arxiv.org/abs/2209.02916

    2022 arXiv

  28. [36]

    HitGNN: High-throughput GNN training framework on cpu+multi-fpga heterogeneous platform,

    Y.-C. Lin, B. Zhang, and V. Prasanna, “HitGNN: High-throughput GNN training framework on cpu+multi-fpga heterogeneous platform, ”arXiv preprint arXiv:2303.01568, 2023. [Online]. Available: https://arxiv.org/abs/2303.01568 A Appendix A.1 Neighbor Sampling With PyG In PyG’s mini...

    2023 arXiv

  29. [2016]

    Available: http://arxiv.org/abs/1510.00149

    [Online]. Available: http://arxiv.org/abs/1510.00149

    arXiv

  30. [2019]

    Available: https://api.semanticscholar.org/CorpusID:195886159

    [Online]. Available: https://api.semanticscholar.org/CorpusID:195886159

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.