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REVIEW 4 major objections 6 minor 25 references

A High Gain Preamplifier Board for Low Charge Semiconductor Detectors

T0 review · 4 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A three-stage transimpedance preamplifier board achieves 115.27 mV·ns/fC charge gain and sub-100 ps timing with LGAD, PIN, and 3D silicon detectors, down to 0.09 fC equivalent noise charge.

desk verdict A genuinely useful low-charge preamplifier board, but the headline 3D timing result is internally inconsistent and needs to be revisited before the paper is used as a reference. read the letter →

arxiv 2608.07963 v1 pith:ZTXR3ANL submitted 2026-08-08 physics.ins-det

De Zhang , Kuo Ma , Juzheng Zhang , Jiajin Ge , Yanwen Liu , Hao Liang This is my paper · ORCID
classification physics.ins-det
keywords front-endelectronicsfordetectorreadoutlow-gainavalanchedetectors3Dsilicontransimpedanceamplifiertimingresolutionequivalentnoisecharge4Dtrackinggain
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports a laboratory front-end preamplifier board that can read out the very small charge signals from LGAD, PIN, and 3D silicon detectors with one circuit design. The board reaches a charge gain of 115.27 mV·ns/fC, stays linear from 0.5 fC to 25 fC, and has a -3 dB bandwidth of 34.0 MHz to 594.3 MHz. Coupled to detectors under a 90Sr beta source, it achieves time resolutions of 36.41 ps with an LGAD, 76.10 ps with a PIN diode, and 39.40 ps with a 3D detector, with equivalent noise charges of 0.18 fC, 0.11 fC, and 0.09 fC. The significance is that existing discrete readout boards do not work reliably below about 1 fC, so this design provides a practical bench tool for characterizing 4D tracking sensors and a starting point for an ASIC.

What carries the argument

The load-bearing element is the three-stage amplifier chain. Stage one is a transimpedance amplifier (TIA) with a 1.3 kΩ feedback resistor built around a discrete BFP840FESD SiGe:C NPN transistor with 85 GHz transition frequency; the TIA converts the detector current to a voltage and preserves pulse shape. Stages two and three are resistive-feedback amplifiers using LTC6431 chips (20.8 dB gain, 2 GHz bandwidth) that raise the voltage to an easily measured level. The bandwidth target comes from the TIA relation $f_{-3\,\mathrm{dB}} = \sqrt{\mathrm{GBWP} / (2\pi R_f C_\mathrm{in})}$, and the discrete transistor is what allows a larger $R_f$ than a commercial amplifier could sustain at the same bandwidth. Low-noise regulators, a shielding enclosure, and a calibration port with a 1 pF injection capacitor complete the design.

What would settle it

Inject calibrated test pulses with different rise times (e.g., 200 ps versus 1 ns) through the 1 pF injection port and compare the output pulse integral; if the derived charge gain shifts by more than the stated 1.1% integral nonlinearity, the reported ENC values for LGAD, PIN, and 3D detectors would move accordingly.

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Extended reading notes

Core claim

The central claim is that a three-stage transimpedance preamplifier, using a discrete SiGe:C bipolar transistor front-end followed by two LTC6431 gain stages, provides enough gain and bandwidth to resolve charges from a few tenths of a femtocoulomb up to 25 fC without changing the detector technology. This makes the board the first discrete readout in the comparison set to give usable signals below 1 fC: the PIN and 3D tests produced sub-femtocoulomb collected charges (0.61 fC and 0.58 fC most probable values) at usable signal-to-noise ratios, while the reference USTC-V1 board could not reliably discriminate such signals. The paper also reports a six-channel version of the same architecture with mean charge gain 115.90 mV·ns/fC, channel-to-channel spread 1.66 mV·ns/fC, and no measurable inter-channel crosstalk in calibration or laser-spot tests.

Load-bearing premise

The reported charge gain and noise figures assume the test pulse injected through the 1 pF calibration capacitor reproduces the shape of a real detector's current pulse; the paper itself notes the gain still depends on pulse shape.

Editorial extensions

If this is right

  • The same board can characterize LGAD, PIN, and 3D detectors without modification, so a single lab setup covers the main fast-timing sensor technologies.
  • Sub-femtocoulomb charges (0.58 fC from the 3D detector) are measurable with an equivalent noise charge around 0.09 fC, opening laboratory testing of small-pitch 3D sensors that previous discrete designs could not read out.
  • With the six-channel variant, a multi-pad detector array can be read out for position-sensitive measurements, since gain uniformity is at the percent level and crosstalk was not observed.
  • The measurements identify electronic jitter as the dominant timing contribution below 1 fC, telling future ASIC designers where to spend noise budget.
  • Baseline shift from the AC-coupled chain will require active baseline correction for high-rate operation, though it did not affect these low-rate tests.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the calibration-shape dependence is corrected in a future iteration, the reported ENC numbers may move; a detector-like current source with a sub-200 ps rise time would make the charge-gain calibration directly traceable to real signals.
  • The discrete TIA design could be pushed to even lower charges by raising the feedback resistor or using a faster input transistor, at the cost of bandwidth, with the bandwidth-gain trade-off in Equation (2.1) giving a quantitative path.
  • A similar topology with active baseline restoration could extend the board from laboratory characterization toward the higher-rate environment of future collider experiments.
  • The observed 3D-detector timing tail, attributed to non-uniform electric field, suggests that combining this readout with detailed sensor simulations could separate electronics jitter from sensor effects.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. This manuscript presents the design and characterization of a three-stage discrete preamplifier board intended for low-charge semiconductor detectors (LGAD, PIN, and 3D silicon sensors). The board is reported to achieve a charge gain of 115.27 mV·ns/fC over an injected-charge range of 0.5–25 fC, a -3 dB bandwidth from 34.0 MHz to 594.3 MHz, and timing resolutions of 36.41 ps, 76.10 ps, and 39.40 ps with ENC values of 0.18 fC, 0.11 fC, and 0.09 fC for the three detector types, respectively. A six-channel variant is also described and tested for gain uniformity and crosstalk. The central claims are that the board is suitable for laboratory-based 4D tracking detector characterization and that it significantly outperforms the authors' previous USTC-V1 reference design.

Significance. The board fills a practical niche: a discrete, high-bandwidth, low-noise readout that can be coupled to both gain-enhanced and non-gain detectors, with a documented dynamic range and a multi-channel extension. The paper's strengths include a concrete circuit architecture, direct measurements of gain, linearity, and bandwidth, a comparison against an existing USTC-V1 design, and crosstalk checks on the multi-channel board. If the timing and ENC numbers survive reanalysis, this would be a useful reference for laboratory 4D tracking characterization and a stepping stone toward a dedicated ASIC. However, the 3D timing result currently appears internally inconsistent with the reported bandwidth and SNR, and the unquantified pulse-shape dependence of the calibration affects the absolute charge scale, so the quantitative headline claims are not yet established.

major comments (4)
  1. [§3.2.3 and Eq. (3.4)] The 3D detector timing result is internally inconsistent. With an RMS noise of 11.24 mV, an amplitude MPV of 72.66 mV, and SNR = 6.46, the reported total timing resolution of 39.40 ps cannot be smaller than the electronic jitter component. Using the measured -3 dB bandwidth of 594.3 MHz gives a single-pole time constant τ = 1/(2π·594.3 MHz) ≈ 0.268 ns; Eq. (3.4) then yields an electronic jitter of about 41 ps if one uses τ/SNR, or about 91 ps if one uses the 10–90% output rise time (0.59 ns) in the same formula. The quoted jitter of 31.1 ps implies t_r ≈ 0.20 ns, which is the detector rise time rather than the amplifier-limited output rise time. This claim must be reanalyzed, ideally with a direct measurement of the output rise time and jitter, before the 3D timing result can be accepted.
  2. [§2.2.2 and Eq. (3.1)] The charge calibration is explicitly admitted in Section 2.2.2 to depend on the injected pulse shape, but no uncertainty or cross-check is provided. Because the ENC is computed as Q_MPV/SNR and Q_MPV is derived from the calibrated charge gain, a pulse-shape mismatch changes all ENC values and the comparison with USTC-V1 by a common systematic factor. Please quantify this sensitivity, for example by measuring the gain with different pulse rise times or against a known detector current source, or explicitly state the resulting limitation on the absolute charge scale.
  3. [§3.2.2 vs §2.1] For the PIN measurement, the feedback resistor of the preamplifier stage was changed to 1.13 kΩ, whereas the quoted charge gain of 115.27 mV·ns/fC was measured with the 1.3 kΩ resistor described in Section 2.1. No recalibration of the charge gain for the 1.13 kΩ configuration is reported. Since reducing R_f from 1.3 kΩ to 1.13 kΩ lowers the transimpedance gain by about 13%, the PIN collected charge and ENC values may be on a different absolute scale; please clarify the resistor change and provide the corresponding calibration.
  4. [§3.2] The headline timing resolutions are quoted to two decimal places without systematic uncertainties, and the MCP-PMT reference contribution is mentioned but never subtracted in quadrature. Please report error bars and the quadrature formula used to separate the detector, electronics, and reference contributions, especially since the 3D jitter estimate is intended to be compared with the total resolution.
minor comments (6)
  1. [Abstract and §3.2.2] The abstract states a PIN ENC of 0.10 fC, while Section 3.2.2 reports 0.11 fC; please reconcile these values.
  2. [Fig. 5] The figure reports 'INL: 0.011' while the text states a maximum INL of 1.10%; please clarify whether this is a fractional value or a percentage.
  3. [Eq. (3.4)] Equation (3.4) uses t_r without defining how it was measured or estimated; please define t_r and state the value used for each detector.
  4. [§3.2] The text alternates between 'combined time resolution' and 'detector timing resolution' without an explicit formula; please define these quantities and how the reference contribution is removed.
  5. [§3.3] The crosstalk test states that 'no detectable signal' was observed, but no quantitative limit is given; please provide a numerical bound relative to the baseline noise.
  6. [Throughout] There are minor typographical issues, including 'Ampitude' in figure axis labels and inconsistent use of units (mV·ns/fC vs mV ns/fC); these could be cleaned up in revision.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: the paper reports calibrated measurements against independent references (pulse generator, network analyzer, MCP-PMT, external datasheets).

full rationale

The paper's load-bearing quantities are all experimental outputs tied to independent references, not to the conclusions they support. Charge gain is obtained by injecting a known voltage step through a 1 pF capacitor (Eq. 3.1) and measuring the output pulse integral; detector charge is then read back through this same calibration, which is a standard measurement chain rather than a circular reduction. The ENC values are derived as Q/SNR using measured MPV amplitudes and measured RMS baseline noise, with no fitted parameter renamed as a prediction. Timing resolutions come from Gaussian fits to measured TOA differences against an MCP-PMT whose approximately 10 ps resolution is cited from an external experiment. The electronic-jitter estimates use Eq. (3.4) with measured SNR and waveform rise-time information, and serve as consistency diagnostics; any possible inconsistency between the 3D jitter estimate and the measured bandwidth is a correctness concern, not circularity. The comparison with the USTC-V1 board is a direct side-by-side measurement under identical conditions, so the self-citation to Ref. [22] is merely a label for a physical baseline, not an imported conclusion. The paper explicitly acknowledges the pulse-shape dependence of the injection calibration in Sec. 2.2.2, which is an accuracy limitation rather than a circular step. No derivation step reduces to its own input.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central claims are empirical measurements, not derived from a model. The paper relies on standard approximations (TIA bandwidth, jitter, ENC) that are stated or cited. No free parameters are fitted to make a theory match data; the reported gain is a measurement result, not an adjustable constant. No new physical entities are postulated.

assumptions (4)
  • domain assumption TIA bandwidth approximation: f_{-3dB} = sqrt(GBWP / (2 pi Rf Cin)).
    Used in Section 2.1 to justify the choice of a discrete SiGe BJT front-end; taken from a Texas Instruments application note [17].
  • domain assumption Electronic jitter approximation: sigma_jitter = t_r / SNR.
    Used in Sections 3.2.1 to 3.2.3 to estimate the electronics contribution to timing resolution; cited to [24]. Assumes a noise-slew-rate limited jitter model and ignores other timing jitter sources.
  • domain assumption ENC estimate: ENC = Q_MPV / SNR.
    Used in Sections 3.2.1 to 3.2.3 to derive equivalent noise charge from signal amplitude statistics; a common shortcut that is sensitive to the charge distribution shape.
  • domain assumption The MCP-PMT reference detector has a time resolution of about 10 ps and does not dominate the measured TOA distribution.
    Stated in Section 3.2.1 with citation [21]; used to interpret the measured Delta-TOA sigma as the DUT timing resolution.

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Cite this review

Pith. "Pith review of A High Gain Preamplifier Board for Low Charge Semiconductor Detectors." pith.science (2026). https://pith.science/paper/ZTXR3ANL

@misc{pith2026260807963,
  author       = {Pith},
  title        = {Pith review of: A High Gain Preamplifier Board for Low Charge Semiconductor Detectors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZTXR3ANL}},
  note         = {Machine review of arXiv:2608.07963}
}
read the original abstract

We present a high-gain, low-noise preamplifier board designed for reading out low-charge semiconductor detectors--specifically Low-Gain Avalanche Detectors (LGADs) and three-dimensional (3D) silicon sensors--in high-energy physics applications. The circuit employs a three-stage architecture featuring a discrete SiGe:C bipolar junction transistor (BJT)-based transimpedance amplifier (TIA) front-end followed by two resistive feedback amplification stages using LTC6431 chips. This configuration achieves a charge gain of 115.27 mV ns/fC with excellent linearity over an input range of 0.5 fC to 25 fC and a wide bandwidth spanning from 34.0 MHz to 594.3 MHz. Experimental evaluations coupled with LGAD detectors demonstrate a time resolution of 36.41 ps and an equivalent noise charge (ENC) of 0.18 fC at 20 {\deg}C. Furthermore, tests with conventional PIN sensors without a gain layer yield a timing resolution of 76.10 ps with an ENC of 0.10 fC, and tests with the 3D silicon detector yield 39.40 ps with an ENC of 0.09 fC, all measured under the same thermal condition. All configurations confirm the board's capability in low-signal regimes, significantly outperforming previous reference designs. A six-channel variant of the board has also been developed to support position-sensitive measurements. These findings demonstrate the board's suitability for laboratory-based 4D tracking detector characterisation, while simultaneously providing the groundwork for dedicated ASIC development.

Figures

Figures reproduced from arXiv: 2608.07963 by the authors.

Figure 1
Figure 1. Simplified schematic of the preamplifier [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Photography of single-channel preamplifier. 2.3 Multi-channel preamplifier board For applications requiring position resolution, a detector array comprising multiple pads is essential, wherein data from multiple channels must be processed to determine the particle’s position through fitting algorithms [19]. Additionally, temporal resolution can be improved by employing multiple channels in conjunction with position-… view at source ↗
Figure 3
Figure 3. Photography of 6-channel preamplifier. 3 Test Results 3.1 Small-signal AC parameter test Prior to performing joint testing with the sensor, it is essential to evaluate the performance characteristics of the amplification board independently. 3.1.1 Charge gain and linearity The initial phase involves comprehensive testing of charge gain, linearity, and dynamic range. For this purpose, an arbitrary waveform generator … view at source ↗
Figures from the paper (9 more)
Figure 4
Figure 4. Figure 4: Setup of the charge gain and linearity test [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Integration of the averaged output waveform versus equivalent injected charge. sampling rate in 2-channel operation mode). To mitigate noise interference, 1000 waveform samples were collected at each voltage point, followed by signal acquisition at various output ampli…
Figure 6
Figure 6. Figure 6: Setup for measuring frequency response. To ensure proper operation of the sensor on the preamplifier board, it is essential to characterize the frequency response across the entire operational bandwidth, thereby verifying that the target signal frequency falls within t…
Figure 7
Figure 7. Figure 7: Frequency response curve of the single-channel preamplifier. 3.2 𝛽-scope tests 3.2.1 Test results with LGAD To evaluate the timing performance and SNR under practical operating conditions, a USTC￾fabricated [20] sensor was bump-bonded to our electronics board and chara…
Figure 8
Figure 8. Figure 8: Setup of 𝛽 scope test. All waveform data were acquired using the HDO9404 oscilloscope, algorithms processed the dual-channel waveforms to extract three critical parameters: collected charge, particle time-of-arrival (TOA), and TOA difference (ΔTOA). Timing determinatio…
Figure 9
Figure 9. Figure 9: One representative output waveform from preamplifier and MCP-PMT. Representative waveforms obtained under these conditions are presented in [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 10
Figure 10. Figure 10: Distributions of output amplitude (a), collected charges (b), RMS noises (c), and ΔTOA (d) measured with our single-channel boards and corresponding results (e-h) are measured with USTC-V1 boards. timing resolution contains the MCP-PMT reference detector’s contributio…
Figure 11
Figure 11. Figure 11: Distributions of output amplitude (a), collected charges (b), RMS noise (c), and ΔTOA (d) measured with our single-channel boards, and corresponding results (e-h) are measured with USTC-V1 boards. Quantitative analysis of the acquired data yielded a MPV of the pulse a…
Figure 12
Figure 12. Figure 12: Distributions of output amplitude (a), collected charges (b), RMS noise (c), and ΔTOA (d) measured with amplification board and a USTC 3D silicon detector at −70 V bias and 20 ◦C. side of the Gaussian peak is observed in the figure, which is believed to arise from the…

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Reference graph

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Reviewed August 12, 2026 · model on record in the stance chip above.