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REVIEW 3 major objections 5 minor 31 references

BearingNAS claims that a small convolutional network inside a vibration sensor's processor can diagnose bearing faults at 99.50% accuracy, and that the search for it completes on a laptop CPU in under an hour.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · deepseek-v4-flash

2026-08-02 09:20 UTC pith:2A45L7G7

load-bearing objection Useful, incremental NAS extension to ISPU targets, but the 'demonstrated in-sensor execution' claim rests on cloud measurements, not physical silicon — fixable, but needs to be flagged in review. the 3 major comments →

arxiv 2607.18287 v1 pith:2A45L7G7 submitted 2026-06-30 cs.LG cs.AI

BearingNAS: Obtaining In-Sensor Intelligent Fault Diagnosis Systems for Bearings Using a Laptop

Andrea Mattia Garavagno , Edoardo Ragusa , Paolo Gastaldo , Antonio Frisoli , Rodolfo Zunino This is my paper
classification cs.LG cs.AI
keywords neural architecture searchhardware-aware NASin-sensor computingbearing fault diagnosistinyMLedge AIconstrained optimization
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

BearingNAS addresses whether deep-learning fault diagnosis can be moved entirely into the sensor die itself, rather than running on a nearby microcontroller or cloud. The authors frame architecture search as a constrained optimization problem in which RAM, Flash, and multiply-accumulate (MAC) counts are hard limits, and they design a search that runs on a laptop CPU without a discrete GPU. On a standard 10-class bearing-fault benchmark, the best architecture found for the LSM6DSO16IS sensor's in-sensor processor uses 97.9k MACs, 7 kiB RAM, and 9.64 kiB Flash, reaches 99.50% test accuracy, and the search converges in under 52 minutes. The paper's broader claim is that in-sensor intelligence can match near-sensor edge models without sacrificing diagnostic accuracy, enabling low-cost, large-scale deployment.

Core claim

The central claim is that a linear stack of 1×3 convolutions with a decaying kernel-growth rule can fit the micro-budgets of an in-sensor processing unit while matching the accuracy of much larger edge models. BearingNAS frames the search as a constrained optimization problem bounded by RAM, Flash, and MACs; each candidate is described by a tuple (k, c), where k is the number of initial kernels and c is the number of repeated cells. The decaying growth rule n_c = n_{c-1} + ⌊2^{1-c} n_{c-1}⌋ keeps the parameter count from exploding as depth increases. The derivative-free search uses an exhaustive inner loop over depth and a variable-increment outer loop over width, with validation loss rather

What carries the argument

The central machinery is a single data-flow search space defined by (k, c): an initial 1×3 convolution with k kernels, followed by c cells, each containing 1×2 max-pooling, batch normalization, and a 1×3 convolution with n_c kernels, ending in global average pooling and a softmax dense layer. The number of kernels per cell follows the decaying growth rule n_c = n_{c-1} + ⌊2^{1-c} n_{c-1}⌋, which prevents the parameter and activation memory explosion that typically blocks deep networks on microcontrollers. The search strategy is derivative-free: an inner loop exhaustively explores depth for a fixed width, while an outer loop varies the initial kernel count with a decreasing increment; the obj

Load-bearing premise

The claim that in-sensor execution has been demonstrated rests on latency measured with a cloud-based estimator rather than on a physical LSM6DSO16IS chip; if that estimate is not faithful to real silicon timing, memory, and instruction support, the central differentiator is unsupported.

What would settle it

Flash the BearingNAS-found architecture onto a physical LSM6DSO16IS ISPU, feed it the same 512-sample, 12 kHz vibration segments, and measure end-to-end latency, actual RAM/Flash usage, and classification accuracy. If the measured latency exceeds 624.6 ms, the memory exceeds 7 kiB RAM / 9.64 kiB Flash, or accuracy falls below 99.50%, the paper's central claim of demonstrated in-sensor execution fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Only the final diagnostic label needs to leave the sensor, eliminating the power and latency cost of streaming raw 12 kHz vibration data over a digital bus.
  • The same constrained-search method can be re-targeted to any microcontroller or ISPU by plugging in its RAM/Flash/MAC budgets; the search automatically scales depth and width to the available memory.
  • Because the search finishes in under an hour on a laptop CPU, hardware-aware NAS no longer requires GPU clusters, lowering the barrier for producing custom in-sensor models in industrial settings.
  • For the tightest 4 kiB RAM target, accuracy drops to 85.25%, making the trade-off between memory and diagnostic accuracy explicit and engineer-controllable through the constraints.
  • The comparison with prior edge models implies that in-sensor execution is a distinct capability, not just a smaller model, since the closest accuracy competitor requires a larger memory footprint and a host microcontroller.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A natural next test is to flash the found architecture onto a physical LSM6DSO16IS chip and measure latency, memory, and accuracy; the paper reports latency from a cloud-based estimator, so the 'demonstrated in-sensor execution' claim should be verified on silicon before production adoption.
  • The linear single-data-flow search space is deliberately simple; a search over branching or residual topologies might find higher accuracy within the same memory envelope, at the cost of more search time.
  • The benchmark uses clean, single-motor, low-speed data; moving to variable-speed or noisy industrial recordings would test whether the in-sensor network generalizes beyond the laboratory setting.
  • The decaying kernel-growth schedule is one of many possible growth rules; an ablation that sweeps different decay schedules (e.g., exponential or Fibonacci-like) could reveal whether the specific formula is load-bearing for the accuracy-per-kilobyte result.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper introduces BearingNAS, a hardware-aware neural architecture search (HW-NAS) framework targeting ultra-low-power microcontrollers and the LSM6DSO16IS intelligent sensor processing unit (ISPU). The search space is a single data-flow stack of 1×3 convolutional, pooling, and batch-normalization layers, parameterized by a tuple (k, c), with a decaying kernel growth formula. The search strategy is derivative-free, runs on a laptop CPU, and optimizes validation loss subject to RAM, Flash, and MAC constraints. The authors evaluate on the CWRU 10-class bearing dataset with a chronological 70/10/20 split and report three final architectures: for the STM32F030F4P6, STM32C011F6P6, and LSM6DSO16IS. The ISPU-targeted model achieves 99.50% test accuracy with 97.9k MACs, 7 kiB RAM, 9.64 kiB Flash, and 624.6 ms latency, with the search converging in under 52 minutes. The paper claims that this is the first demonstrated in-sensor execution for bearing fault diagnosis.

Significance. If the results hold, the contribution is practically valuable: BearingNAS is inexpensive (laptop CPU only), avoids test-set leakage through a chronological split and validation-based search, and the search-space design is simple and transparent. The authors provide code, which aids reproducibility, and the comparison with prior NanoNAS/ColabNAS work is clearly drawn. The reported search costs and resource footprints, if reproducible on physical hardware, would advance the TinyML and condition-monitoring communities. However, the headline claim—'demonstrated in-sensor execution'—currently rests on cloud-based profiling rather than physical silicon, and the accuracy claims lack statistical confidence intervals. These gaps are load-bearing and need to be addressed before the central contribution is established.

major comments (3)
  1. [§IV, Table IV, §VI] The paper's central differentiator is that BearingNAS is 'the only one for which in-sensor execution has been demonstrated' (Table IV) and enables 'true in-sensor execution' (Conclusion). However, Section IV states that latency was 'measured on the LSM6DSO16IS using the ST Edge AI Developer Cloud with ST Edge AI Core 4.0.1', and Flash/RAM are measured with X-CUBE-AI 9.1.0. These are cloud-based estimates, not measurements on a physical ISPU. If the cloud tool's timing model, memory allocation, or instruction interpretation differs from the actual 5 MHz ISPU, the 'demonstrated execution' claim is unsupported. The authors should either provide physical on-sensor measurements (e.g., using STEVAL-MKI230KA or similar with actual ISPU) or explicitly qualify all resource/latency numbers as estimates from vendor tools and remove the word 'demonstrated' from the claim in Table IV and the Conclusi
  2. [Table II] Table II reports single-run accuracies (85.25%, 98.75%, 99.50%) with no error bars, no number of seeds, and no statistical significance testing. The search and training processes are stochastic (Adam with random initialization), so the observed differences between targets could be partially due to training noise. Given that the paper claims a 'highly competitive accuracy of 99.50%' and compares against state-of-the-art methods, the lack of variance information is a significant gap. The authors should repeat the search/training multiple times or at least report standard deviations for the selected architectures, and specify the random seeds used.
  3. [Table IV and §V-D] The comparison with state-of-the-art methods in Table IV is not apples-to-apples. Different papers use different train/test splits, preprocessing, and input representations, and the authors even note that 'results from the literature may use different train/test protocols.' Yet the table and text still treat these accuracies as directly comparable, leading to the claim that BearingNAS is 'highly competitive.' The 'near-sensor' column is also based on the authors' subjective assessment of each method's architecture complexity, not on measured deployment. To support the comparative positioning, the authors should either restrict the quantitative comparison to methods evaluated under a common protocol or clearly state that the comparison is qualitative and that accuracy numbers are not directly comparable.
minor comments (5)
  1. [§IV] The sentence 'we measure the latency ... using the ST Edge AI Developer Cloud' is ambiguous: 'measure' on a cloud service should be reworded to 'estimate' or 'profile' to avoid implying physical measurement.
  2. [§III-C] Algorithm 1 uses variable names (β, γ) that are not defined in the text; define their meanings clearly. Also, the phrase 'the search converges' is more accurately 'the search terminates when the variable increment reaches zero.'
  3. [§IV] The MAC upper bound is set as CoreMark×10^4, borrowing from NanoNAS [27]. This proxy may be hardware-specific and is not validated for the ISPU. The selected ISPU architecture uses only 97.9k MACs, far below the ~1.14M bound, so the proxy is not binding, but the justification for using it should still be clarified.
  4. [Table II] The table header uses 'k' for MAC units; this is confusing because 'k' is also used for the number of kernels in the search space. Consider writing 'kMAC' or '×10^3'.
  5. [§V-D] The column labels 'Near-Sensor' and 'In-Sensor' would benefit from a more precise definition in the text or a footnote, since the former is based on a qualitative assessment rather than a measured deployment.

Circularity Check

0 steps flagged

No circularity found; the central derivation is self-contained, with a noted evidence limitation on in-sensor execution metrics.

full rationale

The derivation chain is self-contained. The architecture search minimizes validation loss (Eq. 1, Algorithm 1) subject to hardware constraints; the reported test accuracy is measured on a chronologically held-out 20% test split, so the headline accuracy is not a fitted input or a renamed training objective. The hardware budgets (RAM/Flash/MAC) are imposed as constraints from published device specifications, and the resulting footprints/latencies are outputs, not re-fitted predictions. The self-citations to ColabNAS [25] and NanoNAS [26], [27] are used as inspiration and for the CoreMark-derived MAC bound heuristic; these are not invoked as an external theorem and do not force the central result. The only noteworthy weakness is evidential, not circular: the LSM6DSO16IS latency is measured with the ST Edge AI Developer Cloud / ST Edge AI Core 4.0.1 rather than on physical silicon, so 'demonstrated in-sensor execution' is vulnerable on verification, but this is an unsupported-claim/correctness concern and does not make the derivation equivalent to its inputs. No circular step meets the quote-and-reduction bar.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 0 invented entities

No new physical entities are introduced. The central result depends on hand-chosen search-space and growth formulas, a proxy MAC bound, a cloud-tool latency estimate, and a single operating-condition benchmark; none of these has independent external verification in the paper.

free parameters (5)
  • MAC bound multiplier = 10^4 × CoreMark; ISPU uses STM32C011F6P6 bound as proxy
    Chosen by hand; no justification is given for CoreMark×10^4 as a MAC/latency proxy, and the ISPU has no CoreMark score so its bound is borrowed from another target.
  • Decaying kernel growth constants = n_c = n_{c-1} + floor(2^{1-c} n_{c-1})
    Ad hoc formulation to slow parameter growth; no derivation or optimality guarantee is offered.
  • Variable increment reduction schedule = β, γ, increment = floor(2^{-β} k)
    Hand-designed search scheduling that affects convergence and the final architecture choice.
  • Training protocol = 100 epochs, batch size 16, Adam lr=0.001
    Fixed by hand; the 99.50% accuracy is contingent on this protocol, and no sensitivity analysis is provided.
  • Evaluation data selection = 200 non-overlapping 512-sample segments per class; 10-class, 0 hp drive-end
    Hand-selected subset of CWRU; the reported accuracies apply only to this configuration, limiting generalization claims.
axioms (5)
  • domain assumption CWRU 10-class, 0 hp drive-end setup is a sufficient proxy for production bearing fault diagnosis
    The introduction and conclusion generalize to 'production-scale' deployment, but the evaluation is a single operating condition on a lab benchmark.
  • domain assumption ST Edge AI Developer Cloud latency measurement faithfully represents physical ISPU execution
    The central 'in-sensor execution demonstrated' claim rests on cloud tooling, not measurements on a physical LSM6DSO16IS.
  • ad hoc to paper CoreMark score ×10^4 is a valid upper-bound proxy for MAC/latency constraints
    No source or validation is given, and the ISPU bound is borrowed from a different microcontroller.
  • domain assumption Literature accuracies in Table IV are approximately comparable despite different data splits and protocols
    Table IV mixes heterogeneous evaluation protocols; the paper notes this only in passing.
  • domain assumption Chronological 70/10/20 split prevents data leakage
    Reasonable as stated, but segment origins and the exact chronological ordering are not detailed.

pith-pipeline@v1.3.0-alltime-deepseek · 8422 in / 12762 out tokens · 115278 ms · 2026-08-02T09:20:07.126847+00:00 · methodology

0 comments
read the original abstract

This paper introduces BearingNAS, a Hardware-Aware Neural Architecture Search (HW-NAS) framework designed to shift the intelligence directly onto the sensor die via in-sensor processing. BearingNAS frames the search as a constrained optimization problem targeting extreme micro-budgets (4 to 8 kiB of RAM and 16 to 32 kiB of Flash). To eliminate the reliance on expensive discrete GPUs, we propose a lightweight, derivative-free search strategy paired with a single data-flow search space that leverages a decaying kernel growth formulation to prevent parameter explosion. We evaluate our framework on the Case Western Reserve University (CWRU) bearing benchmark, optimizing architectures for three STMicroelectronics targets: two commodity microcontrollers and the LSM6DSO16IS Intelligent Sensor Processing Unit (ISPU). Running entirely on a laptop CPU, the search converges in less than an hour. The resulting best in-sensor architecture achieves a highly competitive diagnostic accuracy of 99.50\% on the ISPU. These results demonstrate the viability of shifting the machine learning workload inside the sensor package, enabling low-cost, production-scale bearing fault diagnosis.

discussion (0)

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Reference graph

Works this paper leans on

31 extracted references · 1 linked inside Pith

  1. [1]

    A survey on fault diagnosis approaches for rolling bearings of railway vehicles,

    G. Yan, J. Chen, Y . Bai, C. Yu, and C. Yu, “A survey on fault diagnosis approaches for rolling bearings of railway vehicles,”Processes, vol. 10, no. 4, p. 724, 2022

    2022

  2. [2]

    The vibration analysis of the cnc vertical milling machine spindle system considering nonlinear and nonsmooth bearing restoring force,

    H. Miao, C. Li, C. Wang, M. Xu, and Y . Zhang, “The vibration analysis of the cnc vertical milling machine spindle system considering nonlinear and nonsmooth bearing restoring force,”Mechanical Systems and Signal Processing, vol. 161, p. 107970, 2021

    2021

  3. [3]

    From academic to industrial research: A comparative review of advances in rolling element bearings for wind turbine main shaft,

    S. M. Gbashi, O. O. Olatunji, P. A. Adedeji, and N. Madushele, “From academic to industrial research: A comparative review of advances in rolling element bearings for wind turbine main shaft,”Engineering Failure Analysis, vol. 163, p. 108510, 2024

    2024

  4. [4]

    Cross-domain fault diagnosis of rv reducer rolling bearings based on relative shaft synchronous resampling and adaptive gradient freezing transfer learning,

    L. Xue, Y . Huang, C. Wang, H. Luo, X. Zhang, G. Wang, and J. Guan, “Cross-domain fault diagnosis of rv reducer rolling bearings based on relative shaft synchronous resampling and adaptive gradient freezing transfer learning,”Advanced Engineering Informatics, vol. 69, p. 103987, 2026

    2026

  5. [5]

    Bearings in aerospace, application, distress, and life: a review,

    N. Kumar and R. Satapathy, “Bearings in aerospace, application, distress, and life: a review,”Journal of Failure Analysis and Prevention, vol. 23, no. 3, pp. 915–947, 2023

    2023

  6. [6]

    Progress and state-of-the-art on intelligent fault diagnosis of sliding bearings in reactor coolant pumps,

    R. Zhu, H. Qin, Q. Huang, Y . Zhi, X. Meng, and Q. Fu, “Progress and state-of-the-art on intelligent fault diagnosis of sliding bearings in reactor coolant pumps,”Nuclear Engineering and Design, vol. 451, p. 114761, 2026

    2026

  7. [7]

    Advanced deep learning architectures for bearing fault diagnosis in the petroleum industry,

    W. Feng, C. Zhang, J. Liu, Q. Lin, and T. Gang, “Advanced deep learning architectures for bearing fault diagnosis in the petroleum industry,” inProceedings of the 2025 2025 5th International Conference on Automation Control, Algorithm and Intelligent Bionics, 2025, pp. 425– 429

    2025

  8. [8]

    Dcaggcn: A novel method for remaining useful life prediction of bearings,

    D. He, J. Zhao, Z. Jin, C. Huang, C. Yi, and J. Wu, “Dcaggcn: A novel method for remaining useful life prediction of bearings,”Reliability Engineering & System Safety, vol. 260, p. 110978, 2025

    2025

  9. [9]

    A review on data-driven fault severity assessment in rolling bearings,

    M. Cerrada, R.-V . S ´anchez, C. Li, F. Pacheco, D. Cabrera, J. V . De Oliveira, and R. E. V ´asquez, “A review on data-driven fault severity assessment in rolling bearings,”Mechanical Systems and Signal Pro- cessing, vol. 99, pp. 169–196, 2018

    2018

  10. [10]

    Rolling-element bearings,

    B. J. Hamrock and W. J. Anderson, “Rolling-element bearings,” Tech. Rep., 1983

    1983

  11. [11]

    Fault diagnosis of low speed bearing based on relevance vector machine and support vector machine,

    A. Widodo, E. Y . Kim, J.-D. Son, B.-S. Yang, A. C. Tan, D.-S. Gu, B.- K. Choi, and J. Mathew, “Fault diagnosis of low speed bearing based on relevance vector machine and support vector machine,”Expert systems with applications, vol. 36, no. 3, pp. 7252–7261, 2009

    2009

  12. [12]

    A novel weak fault diagnosis method for rolling bearings based on lstm considering quasi- periodicity,

    D. Gao, Y . Zhu, Z. Ren, K. Yan, and W. Kang, “A novel weak fault diagnosis method for rolling bearings based on lstm considering quasi- periodicity,”Knowledge-Based Systems, vol. 231, p. 107413, 2021

    2021

  13. [13]

    Rolling bearing fault diagnosis using time-frequency analysis and deep transfer convolutional neural network,

    Z. Chen, J. Cen, and J. Xiong, “Rolling bearing fault diagnosis using time-frequency analysis and deep transfer convolutional neural network,” Ieee Access, vol. 8, pp. 150 248–150 261, 2020

    2020

  14. [14]

    A novel time–frequency transformer based on self–attention mechanism and its application in fault diagnosis of rolling bearings,

    Y . Ding, M. Jia, Q. Miao, and Y . Cao, “A novel time–frequency transformer based on self–attention mechanism and its application in fault diagnosis of rolling bearings,”Mechanical Systems and Signal Processing, vol. 168, p. 108616, 2022

    2022

  15. [15]

    Fd-mvllm: Fault diagnosis based on multimodal vibration data and large language model for bearing system,

    D. Li, Z. Pang, Y . Chen, K. Yang, J. Shao, Y . Luo, Y . Zeng, C. He, and Y . Gao, “Fd-mvllm: Fault diagnosis based on multimodal vibration data and large language model for bearing system,”Mechanical Systems and Signal Processing, vol. 239, p. 113226, 2025

    2025

  16. [16]

    Deep transfer learning for bearing fault diagnosis: A systematic review since 2016,

    X. Chen, R. Yang, Y . Xue, M. Huang, R. Ferrero, and Z. Wang, “Deep transfer learning for bearing fault diagnosis: A systematic review since 2016,”IEEE Transactions on Instrumentation and Measurement, vol. 72, pp. 1–21, 2023

    2016

  17. [17]

    Lite and efficient deep learning model for bearing fault diagnosis using the cwru dataset,

    Y . Yoo, H. Jo, and S.-W. Ban, “Lite and efficient deep learning model for bearing fault diagnosis using the cwru dataset,”Sensors, vol. 23, no. 6, p. 3157, 2023

    2023

  18. [18]

    Leveraging systems’ non-linearity to tackle the scarcity of data in the design of intelligent fault diagnosis systems,

    G. Santamato, A. M. Garavagno, M. Solazzi, and A. Frisoli, “Leveraging systems’ non-linearity to tackle the scarcity of data in the design of intelligent fault diagnosis systems,”Nonlinear Dynamics, vol. 112, no. 18, pp. 16 153–16 166, 2024

    2024

  19. [19]

    Compression– accuracy co-optimization through hardware-aware neural architecture search for vibration damage detection,

    E. Ragusa, F. Zonzini, L. De Marchi, and R. Zunino, “Compression– accuracy co-optimization through hardware-aware neural architecture search for vibration damage detection,”IEEE Internet of Things Journal, vol. 11, no. 19, pp. 31 745–31 757, 2024

    2024

  20. [20]

    Low-power detection and classification for in-sensor predictive main- tenance based on vibration monitoring,

    P. Vitolo, A. De Vita, L. Di Benedetto, D. Pau, and G. D. Licciardo, “Low-power detection and classification for in-sensor predictive main- tenance based on vibration monitoring,”IEEE Sensors Journal, vol. 22, no. 7, pp. 6942–6951, 2022

    2022

  21. [21]

    Automated neural build for in- sensor inferences,

    S. Tognocchi, M. Marcon, and D. Pau, “Automated neural build for in- sensor inferences,” in2026 IEEE International Conference on Consumer Electronics (ICCE). IEEE, 2026, pp. 1–4

    2026

  22. [22]

    A comprehensive survey on hardware-aware neural architecture search,

    H. Benmeziane, K. E. Maghraoui, H. Ouarnoughi, S. Niar, M. Wistuba, and N. Wang, “A comprehensive survey on hardware-aware neural architecture search,”arXiv preprint arXiv:2101.09336, 2021

    Pith/arXiv arXiv 2021

  23. [23]

    Mnasnet: Platform-aware neural architecture search for mobile,

    M. Tan, B. Chen, R. Pang, V . Vasudevan, M. Sandler, A. Howard, and Q. V . Le, “Mnasnet: Platform-aware neural architecture search for mobile,” inProceedings of the IEEE/CVF conference on computer vision and pattern recognition, 2019, pp. 2820–2828

    2019

  24. [24]

    Mcunet: Tiny deep learning on iot devices,

    J. Lin, W.-M. Chen, Y . Lin, C. Gan, S. Hanet al., “Mcunet: Tiny deep learning on iot devices,”Advances in neural information processing systems, vol. 33, pp. 11 711–11 722, 2020

    2020

  25. [25]

    Colabnas: Obtaining lightweight task-specific convolutional neural networks following oc- cam’s razor,

    A. M. Garavagno, D. Leonardis, and A. Frisoli, “Colabnas: Obtaining lightweight task-specific convolutional neural networks following oc- cam’s razor,”Future Generation Computer Systems, vol. 152, pp. 152– 159, 2024

    2024

  26. [26]

    An affordable hardware-aware neural architecture search for deploying convolutional neural networks on ultra-low-power computing platforms,

    A. M. Garavagno, E. Ragusa, A. Frisoli, and P. Gastaldo, “An affordable hardware-aware neural architecture search for deploying convolutional neural networks on ultra-low-power computing platforms,”IEEE Sen- sors Letters, vol. 8, no. 5, pp. 1–4, 2024

    2024

  27. [27]

    Searching neural architectures for sensor nodes on iot gateways,

    ——, “Searching neural architectures for sensor nodes on iot gateways,” IEEE Internet of Things Journal, 2025

    2025

  28. [28]

    A new data-driven intelligent fault diagnosis by using convolutional neural network,

    L. Wen, L. Gao, X. Li, M. Xie, and G. Li, “A new data-driven intelligent fault diagnosis by using convolutional neural network,” in2017 IEEE international conference on industrial engineering and engineering management (IEEM). IEEE, 2017, pp. 813–817

    2017

  29. [29]

    A convolutional neural network method based on adam optimizer with power-exponential learning rate for bearing fault diagnosis,

    Y . Wang, Z. Xiao, and G. Cao, “A convolutional neural network method based on adam optimizer with power-exponential learning rate for bearing fault diagnosis,”Journal of Vibroengineering, vol. 24, no. 4, pp. 666–678, 2022

    2022

  30. [30]

    An improved fault diagnosis using 1d-convolutional neural network model,

    C.-C. Chen, Z. Liu, G. Yang, C.-C. Wu, and Q. Ye, “An improved fault diagnosis using 1d-convolutional neural network model,”Electronics, vol. 10, no. 1, p. 59, 2020

    2020

  31. [31]

    Debiased contrastive learning with supervision guidance for industrial fault detec- tion,

    R. Cai, W. Gao, L. Peng, Z. Lu, K. Zhang, and Y . Liu, “Debiased contrastive learning with supervision guidance for industrial fault detec- tion,”IEEE Transactions on Industrial Informatics, vol. 20, no. 11, pp. 12 814–12 825, 2024

    2024