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REVIEW 3 major objections 5 minor 48 references

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read This paper claims that splitting a chip into two stacked tiers and hiding the vertical connections with camouflaged vias can protect designs from both untrusted foundries and reverse-engineering end-users.

desk verdict The 3D split-manufacturing flow is a real engineering contribution, but the HT-prevention guarantee is not backed up: the reported k is defined as a sum across tiers and the paper never shows an attacker can't localize a target to one tier, which would double the claimed success probability. read the letter →

arxiv 1908.03925 v1 pith:3RT7GVM4 submitted 2019-08-11 cs.CR cs.ET

Satwik Patnaik , Mohammed Ashraf , Ozgur Sinanoglu , Johann Knechtel This is my paper · ORCID
classification cs.CRcs.ET
keywords 3DICsplitmanufacturinglayoutcamouflaginghardwareTrojanIPprotectionverticalinterconnectsk-securityface-to-facebonding
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Split manufacturing hides a chip's layout from an untrusted foundry, while layout camouflaging hides it from a reverse-engineering end-user; each alone covers only one adversary. This paper claims that both protections can be achieved in a single flow by splitting the design across two face-to-face stacked tiers and obfuscating the vertical interconnects, so that the untrusted foundry sees two tier layouts but not the wiring that gives the design its function. The paper develops a security-driven CAD flow that randomizes and camouflages the redistribution layer between tiers, and reports DRC-clean layouts for multi-million-gate designs with moderate power, performance, and area cost. For Trojans, it adds a synthesis stage that multiplies vulnerable structures into many indistinguishable copies, making targeted insertion a matter of chance even when the attacker already holds the full netlist. If the claims hold, design houses can use advanced but untrusted foundries while protecting both their IP and their chips from malicious modification.

What carries the argument

The obfuscated vertical interconnect is the mechanism that carries the IP-protection argument: randomized F2F via placement, embedded switchboxes that map any of four drivers to any of four sinks, and Mg/MgO vias that oxidize into visually indistinguishable dummies. For Trojan prevention, the load-bearing mechanism is security-driven synthesis: vulnerable structures are re-expressed as custom cells, replicated until many isomorphic copies exist, marked as don't-touch so tools cannot alter them, then decomposed back into standard gates, lifting k-security from a post-layout heuristic to a design-time guarantee.

What would settle it

Delayering a protected face-to-face stack and imaging the redistribution layer with a material-sensitive method, such as electron microscopy with elemental analysis, would show whether real Mg vias can be distinguished from MgO dummies. If an attacker can reliably label which vias conduct, the switchbox mappings become known and the reported correct-connection and netlist-recovery rates would be much higher than the paper's security analysis claims.

Watch

Extended reading notes

Core claim

The central claim is that "3D splitting" is the natural way to combine split manufacturing with layout camouflaging. The design is partitioned into two tiers fabricated by untrusted foundries and later bonded face-to-face; a trusted back-end facility grows a redistribution layer whose vertical vias realize the inter-tier connections. Randomizing the via locations destroys the proximity cues that make 2D split manufacturing attackable, while Mg/MgO vias that become indistinguishable from dummy vias under reverse engineering hide the connectivity from end-users. The same 3D infrastructure, without the camouflage, is used to prevent hardware Trojans: a security-driven synthesis stage creates many isomorphic instantiations of vulnerable gate structures, so a fab-based attacker holding the complete netlist cannot uniquely identify the target, with reported success probabilities as low as 0.25% for benchmark b19.

Load-bearing premise

The scheme assumes the back-end-of-line facility that grows the obfuscated redistribution layer is trustworthy and that the Mg/MgO vias really are indistinguishable after reverse-engineering delayering; if either fails, the IP-protection claim collapses.

Editorial extensions

If this is right

  • Design houses can fabricate at advanced but untrusted foundries while protecting new-version IP from both fabs and end-users, without relying on tamper-proof memories as logic locking does.
  • Targeted hardware Trojan insertion becomes probabilistically difficult even under the strong assumption that the attacker holds the complete gate-level netlist.
  • The reported power, performance, and area costs are often comparable to or better than conventional 2D split manufacturing and layout camouflaging, with footprint savings on large designs.
  • k-security, previously limited to small benchmarks, becomes scalable to multi-million-gate designs through synthesis-level replication and 3D partitioning.
  • SAT-based reverse-engineering attacks time out on the larger protected designs, and even a successful functional recovery of the vertical connections does not give the structural equivalence needed to place Trojans.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the trusted-BEOL assumption holds, the flow could be adopted incrementally by packaging houses already offering face-to-face bonding, since no change to the FEOL process is required.
  • A direct test of the weakest assumption would be to build a small F2F test chip with Mg/MgO vias and run a standard delayering and imaging reverse-engineering flow to measure how often real vias are misclassified as dummies.
  • The paper's proximity attack assumes the attacker resolves all driver-sink pairings except within switchboxes; a natural next question is whether a learning-based attacker using both tier layouts and routing patterns could do better, which would tighten or weaken the reported security margins.
  • The same 3D-splitting idea could be extended to protect against physical attacks such as invasive probing and side-channel leakage, a direction the paper names as future work.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes a security-driven CAD and manufacturing flow for face-to-face 3D integrated circuits that combines split manufacturing (SM) and layout camouflaging (LC). The design netlist is partitioned into two tiers, the vertical interconnects between tiers are randomized and obfuscated using redistribution layers (RDLs) with Mg/MgO vias and switchboxes, and a trusted BEOL facility performs the stacking. Two variants are developed: one for IP protection against untrusted fabs and malicious end-users, and one for hardware-Trojan prevention under a strong threat model where the attacker already holds the complete gate-level netlist. The latter uses a security-driven synthesis stage to create many isomorphic structures and applies k-security notions from prior work. Experiments on DRC-clean layouts of ITC-99, ISCAS-85, DARPA CEP, and OpenCores JPEG benchmarks report PPA overheads, attack results from a newly proposed proximity attack and SAT-based attacks, and a headline claim that for benchmark b19 the attacker has only a 0.25% chance of successful targeted Trojan insertion.

Significance. If the security claims hold, this is a substantial systems contribution: it is one of the first end-to-end flows to combine SM and LC in 3D ICs, applies k-security to multi-million-gate benchmarks for the first time, provides DRC-clean layouts with an industrial tool, reports distributions over randomized runs, and publicly releases the 3D split-manufacturing attack. These are concrete, reproducible strengths. However, the central Trojan-prevention guarantee and the IP-protection claim both rest on security arguments that are asserted rather than demonstrated, and one of the two headline probabilities is tied to an internal inconsistency in the reported security levels. The work is therefore promising but requires substantial additional analysis before the main claims can be accepted.

major comments (3)
  1. [Sec. 7.3 / Sec. 8.2 / Table 12] The claim that the proposed 3D partitioning preserves the k-security notion of [10] is the load-bearing step for the 0.25% HT-insertion figure (b19, Table 12: k=400). The text in Sec. 7.3 asserts that 'the attacker cannot understand which isomorphic instances in the bottom/top tier relate to which in the netlist,' but no analysis or experiment supports this assertion. Under the strong threat model, the attacker holds the complete final netlist and both tier layouts, and the tier assignment is physically visible. Because all gates of a decomposed structure are kept in one tier, the attacker can observe which physical structures lie in which tier and can match their visible intra-tier connectivity against the netlist. The cited k-isomorphism result [45] concerns anonymized graph publication, not a setting where the original netlist is given and the tier partition is partially observed. A concrete test would be to implement the attacker's candidate-set computation: for each target structure, count how many physical structures remain viable after matching tier membership and visible intra-tier nets, and report the minimum as the effective k. Without such an analysis, the 1/k probability does not follow from the presented data.
  2. [Table 10 vs. Table 12 / Sec. 8.2] The reported security levels are not reconciled. Table 10 lists k=1,221 for b19 after five synthesis iterations and k=576 for b18, while Table 12 lists k=400 for b19 and k=345 for b18, despite Sec. 8.2 stating that 'The levels in 3D are the same as in 2D.' The headline probability of 0.25% is exactly 1/400, so readers need to know which k is operative and why the 3D flow changes it. If Table 12's footnote definition (sum of least-occurring structures in the bottom and top tiers) is intended, the paper must justify why this sum equals the attacker's inverse success probability per target; that is not immediate from the k-security definition in [10], which uses the minimum number of isomorphic instances in the FEOL layout. This inconsistency directly affects the paper's central quantitative claim.
  3. [Sec. 4.2 / Sec. 5.3 / Sec. 6.1] The IP-protection half of the paper rests on physical assumptions that are not validated in the manuscript. The RDL obfuscation assumes Mg/MgO vias remain indistinguishable during reverse engineering, citing [40] without additional physical validation or sensitivity analysis for the proposed switchbox implementation, and the layouts model F2F vias as regular M6/M10 vias (an 'optimistic assumption' stated in Sec. 6.1). If the RDL can be imaged or the switchbox connectivity distinguished, the claimed resilience against malicious end-users is not established. The paper should either provide a validation path for these assumptions or clearly frame the security results as conditional on them; as it stands, the security evaluation is conducted on an idealized model of the RDL.
minor comments (5)
  1. [Abstract] The phrase 'entering the third dimension is eminent' appears to be a typo; 'imminent' or 'imperative' would be more appropriate.
  2. [Table 12] The footnote reads 'least occuring structures'; this should be 'least occurring structures.'
  3. [Sec. 1] The statement that 'only our work can readily protect against both threats' is stronger than the evidence presented, since the end-user protection relies on the unvalidated Mg/MgO assumption and the fab-based protection relies on the unproven preservation of k-security; consider softening the claim or adding a comparison table with the assumptions required by each scheme.
  4. [Sec. 7.1.2 / Sec. 8.2] The phrase 'few if any proper attacks on k-security are available yet' is vague; the authors should cite the specific known attacks or explain why existing attacks are inapplicable.
  5. [Fig. 8] The y-axis label 'Norm. Distance for F2F Vias' would be clearer with an explicit statement of what distance is normalized by (e.g., pitch or die dimension) and for which benchmark the distribution is shown.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the PPA results are measured with independent tools, and the security claims rest on external formal foundations rather than on self-referential reductions.

full rationale

The paper's derivation chain is not circular. The IP-protection half is evaluated by measured PPA from Cadence Innovus on DRC-clean layouts (Tables 3, 4, 11, 12) and by a publicly released 3D proximity attack [42]; that attack is an externally reusable artifact, and the evaluation conservatively assumes the attacker already resolves all switchbox pairings correctly, so it is not a fitted input. The HT-prevention half rests on k-security from Imeson et al. [10] and the k-isomorphism result of Cheng et al. [45], both external to the present authors; the authors' own prior lifting cells [18] and interconnect obfuscation [28] are used as reusable tooling, not as load-bearing evidence for the central guarantee. The headline 0.25% figure is the definitional inverse of the reported security level k=400 in Table 12, but the reduction is grounded in the externally stated k-security theorem rather than in a parameter fitted to the claimed outcome. The inconsistency between k=1,221 in Table 10 and k=400 in Table 12, and the unproved assertion that partitioning prevents the attacker from relating tier instances to the netlist, are correctness and validation concerns, not circularity. No step was found where an output equals an input by construction.

Assumptions & free parameters 3 free parameters · 4 assumptions · 1 invented entities

No constants are fitted to data; the central numbers are measured or computed. The main relied-upon inputs are prior formal definitions (k-security and k-isomorphism), physical assumptions about RDL obfuscation, and a trusted BEOL facility, listed as axioms.

free parameters (3)
  • Timing threshold for timing-aware partitioning = not reported
    Sec. 5.1 states a user-defined threshold decides which gates stay in the bottom tier. The reported security versus PPA trade-off in Sec. 6.2.2 depends on this knob, and no single value or sensitivity sweep is given.
  • Fraction of gates treated as vulnerable = 10%
    Sec. 8.1 and Table 10 assume 10% of gates are vulnerable according to [11]. The coverage numbers and k values (30 to 1,221) are computed for this choice.
  • Structure set for security-driven synthesis = 18 explored, 7 used (Fig. 17)
    The choice and number of isomorphic structures is a hand-selected design input. k values in Table 10 are bounded by the least-used structure, e.g., structure (c) limits b14 to k=30.
assumptions (4)
  • domain assumption An attacker in the untrusted FEOL fab holds layouts of both tiers but not the trusted RDL.
    Sec. 6.4.1 states the attacker has no access to the trusted RDL. If false, randomization and switchbox obfuscation are moot.
  • domain assumption Mg/MgO via camouflaging resists reverse engineering as reported by Chen et al. [40].
    Sec. 4.2 relies on this external result; the paper performs no fabrication or physical verification of the vias.
  • domain assumption k-security and k-isomorphism provide a formal guarantee against targeted HT insertion for an attacker holding the final netlist.
    Sec. 7.1 imports [10] and [45]; the paper extends the framework but does not reprove it.
  • domain assumption F2F vias can be modeled as regular M6/M10 vias for PPA estimation.
    Sec. 6.1 says F2F vias are modeled as M6 vias, calling this optimistic, which affects reported power and delay.
invented entities (1)
  • Obfuscated switchbox in the RDL
    purpose: Cloaks which of four driver pins connects to which of four sink pins using Mg/MgO via camouflage.
    Sec. 5.2 and Fig. 9. The switchbox is a new structure, but its physical security is not independently verified here; it inherits the Mg/MgO assumption of [40].

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Cite this review

Pith. "Pith review of A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects." pith.science (2026). https://pith.science/paper/3RT7GVM4

@misc{pith2026190803925,
  author       = {Pith},
  title        = {Pith review of: A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3RT7GVM4}},
  note         = {Machine review of arXiv:1908.03925}
}
read the original abstract

Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security.

Figures

Figures reproduced from arXiv: 1908.03925 by the authors.

Figure 1
Figure 1. Our scheme is based on 3D integration, particularly on face-to [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. PPA cost (%) for look-alike LC [24] (left) and explicit lifting of [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. (a) Current chip version (top) versus new chip version (bottom). [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (15 more)
Figure 5
Figure 5. Figure 5: Two approaches to 3D integration to prevent targeted HT inser [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: Our CAD flow for F2F 3D ICs, implemented in [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: (Left) RDL randomization for switchboxes and F2F vias. (Right) [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 9
Figure 9. Figure 9: Obfuscated switchbox, embedded in two RDL layers, exemplarily [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 10
Figure 10. Figure 10: Layout snapshots of bottom/top tier (left/right) for [PITH_FULL_IMAGE:figures/full_fig_p008_10.png]
Figure 11
Figure 11. Figure 11: Impact of randomly assigning gates on performance (top) and power (bottom). Each boxplot represents ten runs. Note that the same [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 12
Figure 12. Figure 12: Layout cost for maximizing cuts, with 35–50% of the gates [PITH_FULL_IMAGE:figures/full_fig_p009_12.png]
Figure 13
Figure 13. Figure 13: Performance, power cost for timing-aware setup with obfuscated [PITH_FULL_IMAGE:figures/full_fig_p009_13.png]
Figure 14
Figure 14. Figure 14: Percentage of netlist recovery (PNR) [18], Hamming distance (HD), and correct connection rates (CCR), when the benchmarks are [PITH_FULL_IMAGE:figures/full_fig_p012_14.png]
Figure 15
Figure 15. Figure 15: k-security is to apply split manufacturing and purposefully lift wires to the BEOL (indicated by dashed wires) such that FEOL-based attackers cannot uniquely identify some or any parts of the netlist avail￾able to them. Hence, targeted Trojan insertion becomes difficu…
Figure 16
Figure 16. Figure 16: Our CAD flow for F2F 3D ICs, with security-driven steps for [PITH_FULL_IMAGE:figures/full_fig_p013_16.png]
Figure 17
Figure 17. Figure 17: The seven structures considered in this work without loss of generality. They are constructed based on the vulnerability analysis of [11]. [PITH_FULL_IMAGE:figures/full_fig_p014_17.png]
Figure 18
Figure 18. Figure 18: Runtime comparison for regular synthesis and our security [PITH_FULL_IMAGE:figures/full_fig_p015_18.png]
Figure 19
Figure 19. Figure 19: Distribution of layout cost for all 18 different structures we explored on various benchmarks. Top: without any optimization; bottom: with [PITH_FULL_IMAGE:figures/full_fig_p016_19.png]
Figure 20
Figure 20. Figure 20: 2D layout (left), bottom/top tier of the F2F 3D IC (right), both for [PITH_FULL_IMAGE:figures/full_fig_p016_20.png]

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