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REVIEW 3 major objections 6 minor 13 references

Characterisation of analogue MAPS produced in the 65 nm TPSCo process

T0 review · 3 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A monolithic pixel sensor prototype is shown to track particles with sub-2 µm spatial resolution while keeping over 99% efficiency up to a 180-electron seed threshold.

desk verdict First CE-65v2 characterisation data for 65 nm TPSCo MAPS, with a real but fixable gap in how the sub-2 micron resolution is extracted. read the letter →

arxiv 2411.08740 v1 pith:3TUC7KYU submitted 2024-11-13 physics.ins-det hep-ex

Eduardo Ploerer , Hitoshi Baba , Jerome Baudot , Auguste Besson , Szymon Bugiel , Tatsuya Chujo , Claude Colledani , Andrei Dorokhov
show 26 more authors
Ziad El Bitar Mathieu Goffe Taku Gunji Christine Hu-Guo Armin Ilg Kimmo Jaaskelainen Towa Katsuno Alexander Kluge Anhelina Kostina Ajit Kumar Alessandra Lorenzetti Anna Macchiolo Magnus Mager Jonghan Park Shingo Sakai Serhiy Senyukov Hasan Shamas Daito Shibata Walter Snoeys Pavel Stanek Miljenko Suljic Lukas Tomasek Isabelle Valin Reita Wada Yorito Yamaguchi the ALICE Collaboration
This is my paper · ORCID
classification physics.ins-dethep-ex PACS 29.40.Gx29.40.Wk
keywords monolithicactivepixelsensorMAPS65nmCMOSchargesharingspatialresolutiontrackingdetectortestbeamiron-55calibration
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports first characterisation results for a family of small monolithic active pixel sensor test chips built in a 65 nm CMOS imaging process, aimed at the next upgrade of a large experiment's inner tracking system. The authors show that at a 70-electron seed threshold, the standard-process 15 µm-pitch chip reaches about 1.5 µm spatial resolution and the 22.5 µm-pitch chip about 2 µm, while both chips exceed 99% efficiency up to roughly 130 to 150 electrons. A process modification that adds a deep low-dose n-type implant with gaps at pixel edges gives drift-dominated charge collection, raising the 99%-efficiency threshold to about 180 electrons for both pitches at the cost of somewhat worse spatial resolution. Matrix gain uniformity at the few-percent level is demonstrated by iron-55 X-ray spectra. If these results hold, the process is a validated candidate for the planned tracker upgrade and the resolution-versus-operating-range tradeoff becomes a practical design handle.

What carries the argument

The central object is the CE-65v2, a monolithic active pixel sensor test matrix of 1152 pixels with variants spanning two pixel pitches (15 and 22.5 µm) and two collection-layer processes, named Standard and Modified with Gap. The load-bearing mechanism is the difference in charge collection: the Standard process depletes a balloon-shaped region around each n-well electrode, leaving lateral charge to diffuse slowly and share widely; the Modified with Gap process adds a deep low-dose n-type implant with gaps at pixel edges, letting the depletion region extend laterally so collection is drift-dominated and charge stays concentrated. The paper measures the consequences through cluster charge-ordering, giving an accumulated charge ratio, and through efficiency and centre-of-mass resolution as functions of electron threshold.

What would settle it

Reanalyse the stored test-beam data with an explicit, documented deconvolution of the 2.2 µm telescope resolution, for example subtracting the telescope contribution from the residual width in quadrature or fitting the residual distribution with the telescope response folded in, and check whether the extracted device resolution stays below 2 µm at a 70-electron seed threshold. If it does not, the paper's headline claim fails.

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Extended reading notes

Core claim

The central claim is that the CE-65v2 sensor variants meet the performance targets of the planned inner-tracker upgrade: spatial resolution below 2 µm at low seed threshold in the Standard process, and over 99% efficiency up to about 180 electrons in the Modified with Gap process. The controlling mechanism is charge sharing: the Standard process, with diffusion-dominated collection, produces large clusters that give finer centre-of-mass position but lose efficiency quickly as threshold rises; the Modified with Gap process adds a deep n-type implant with edge gaps, making collection drift-dominated, concentrating charge in one or two pixels, stabilising efficiency but degrading resolution. The paper concludes that these measurements validate the 65 nm CMOS process and motivate choosing pitch and process variant according to the radiation and occupancy environment.

Load-bearing premise

The headline sub-2 µm spatial resolution rests on knowing the test telescope's 2.2 µm resolution and on an undescribed deconvolution of the device resolution from the track residual distribution; if that deconvolution is wrong or unaccounted for, the sub-2 µm figure is not reproducible.

Editorial extensions

If this is right

  • Sub-2 µm spatial resolution in a 15 µm-pitch Standard-process chip at a 70-electron seed threshold satisfies the resolution target for the inner-tracker upgrade and for future lepton-collider tracking.
  • The 99%-efficiency operating range extends from roughly 130 to 150 electrons in the Standard process to about 180 electrons in the Modified with Gap process at both pitches, meaning the modified process tolerates higher noise and threshold settings.
  • The Standard process's resolution degrades quickly between 70 and 250 electrons before plateauing near 3 to 4 µm, while the Modified with Gap process trades the best resolution for a flatter, more stable response over threshold.
  • Matrix gain uniformity at the few-percent level in all four variants means full-matrix spectra can be used for energy calibration and pixel-to-pixel corrections are small.
  • The demonstrated performance validates the 65 nm CMOS imaging process as a candidate for wafer-scale bent sensors in the planned tracker upgrade, with the Modified with Gap variant favoured for high-radiation environments.
  • The charge-ordering method gives a direct empirical handle on cluster-size distributions and could be used to tune the reset voltage for optimal charge sharing, a knob the authors say they are exploring.
  • A smaller-pitch Modified with Gap chip, for example one with a 10 µm pitch, might recover much of the lost spatial resolution while keeping the wide operating range, since the resolution loss is dominated by reduced cluster size rather than by pitch.
  • The 18 µm pitch and hexagonal-staggered geometry variants under analysis could interpolate the 15 to 22.5 µm behaviour and test whether a hexagonal arrangement reduces cluster-edge effects.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the same tradeoff holds after irradiation, the Modified with Gap process's concentrated charge collection should make it more resilient to charge trapping; the paper announces radiation studies, so this can be checked directly.
  • A smaller-pitch Modified with Gap chip, for example one with a 10 µm pitch, might recover much of the lost spatial resolution while keeping the wide operating range, since the resolution loss appears dominated by reduced cluster size rather than by pitch.
  • The 18 µm pitch and hexagonal-staggered geometry variants under analysis could interpolate the 15 to 22.5 µm behaviour and test whether a hexagonal arrangement reduces cluster-edge effects.
  • The reported sub-2 µm device resolutions sit below the quoted telescope resolution, so a fuller statement of the resolution-deconvolution procedure would let other groups reproduce the headline number from the same residual distributions.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This paper reports the first characterisation results of the CE-65v2 analogue MAPS test structures fabricated in the 65 nm TPSCo CMOS process, developed in the context of the ALICE ITS3 upgrade. Four chip variants were studied: 15 um and 22.5 um pixel pitch, in the Standard and Modified-with-Gap process versions. Lab measurements with a 55Fe source establish matrix gain uniformity at the O(5%) level, and test-beam measurements at the CERN SPS provide efficiency versus seed threshold, spatial resolution versus threshold, and charge-sharing distributions. The paper reports over 99% efficiency up to about 130-150 e- for the Standard process and about 180 e- for the Modified-with-Gap process, spatial resolution as low as about 1.5 um at low threshold for the 15 um Standard chip, and a wider operating range with faster charge collection for the Modified-with-Gap process. The conclusion argues that these results validate the 65 nm TPSCo process for ITS3 and inform design choices for future detectors.

Significance. If the quantitative claims hold, this is a valuable direct measurement for the 65 nm TPSCo MAPS R&D programme, with direct relevance to ALICE ITS3 and to future experiments such as FCC-ee. The paper benefits from the use of external telescope tracks, energy calibration from the known 55Fe K_alpha line, a systematic comparison of process and pitch variants, and a clear charge-sharing diagnostic. The main quantitative claim, however, is the spatial resolution of 'under 2 um', and the manuscript currently does not describe how that number was extracted from telescope residuals; the abstract also disagrees with the conclusion's 'sub 3 um' wording. These issues must be resolved before the central claim can be accepted as reproducible.

major comments (3)
  1. [Section 3] The spatial-resolution extraction is not described. After stating that 'The telescope resolution was estimated to be 2.2 um using a telescope optimizer', the manuscript reports DUT resolutions as low as ~1.5 um in Figure 5a, but gives no residual estimator (unbiased track residuals, pull distributions, or fitted residual width), no covariance propagation from the telescope, and no deconvolution formula such as sigma_DUT^2 = sigma_resid^2 - sigma_tel^2. For Gaussian residuals, extracting a 1.5 um DUT resolution from a 2.2 um telescope requires a residual width of about 2.66 um, so modest errors in the assumed telescope resolution translate into large relative errors in the DUT value. Without an explicit description of the residual-based method, the abstract's headline 'under 2 um' claim is not reproducible from the text.
  2. [Abstract and Section 4] The quantitative headline is internally inconsistent. The abstract claims 'a spatial resolution of under 2 um during beam tests', while the conclusion says 'sub 3 um spatial resolution obtained in the Standard process for both pitches' and Figure 5a shows the resolution rising to roughly 3-4 um at higher thresholds. The manuscript should state explicitly which estimator, seed threshold, and operating point each claim refers to, and quote a single headline resolution with its operating conditions. As written, the reader cannot determine whether the intended result is 1.5 um at 70 e-, under 2 um somewhere in the threshold scan, or sub 3 um over a range.
  3. [Section 3, Figures 4 and 5] The test-beam efficiency and resolution curves are presented without error bars or numerical uncertainties. The comparisons between variants, such as 'over 99% efficiency up to ~130 e- and ~150 e-' for the Standard process and '~180 e-' for the Modified-with-Gap process, and the resolution values quoted in Figure 5, are therefore not quantitatively supported. Please include statistical uncertainties (at least) on the efficiency and resolution points, and state how the quoted threshold values and their uncertainties are derived.
minor comments (6)
  1. [Introduction] There is a typo in the first sentence: 'Monolitihic' should be 'Monolithic'.
  2. [Introduction] The process name 'TPSco' appears once and should be 'TPSCo' to match the rest of the text.
  3. [Section 2] The sentence 'Figure 2b depicts the main K_alpha peak position for the 15 um Standard process chip' is confusing; Figure 2b appears to show a spectrum, not a peak position. Please clarify what is plotted.
  4. [Section 3] The terms 'electron threshold' and 'seed threshold' are used somewhat interchangeably. Please define both once and state explicitly how the x-axis thresholds of Figures 4 and 5 relate to the 100 e- seed threshold used in cluster building.
  5. [Section 3, Figure 6] The accumulated-charge-ratio metric can exceed 100% due to negative noise contributions after frame subtraction, as acknowledged in the text. Please state how negative pixel values are treated in the charge-ordering and normalization, because this affects the reported central-pixel charge fractions.
  6. [References] Reference [12] is a web page; please provide the version or configuration of the telescope optimizer used for the quoted 2.2 um telescope resolution.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper's central claims are measured against external references (55Fe K_alpha line, ALPIDE telescope tracks) and the cited prior work is cumulative device physics, not an input recycled as a prediction.

full rationale

The paper is a direct characterisation study, and its derivation chain is self-contained against external benchmarks. The energy calibration in Section 2 uses the known 55Fe K_alpha line at 5.9 keV to convert ADUs to energy; this is an external standard, not an output of the model. The efficiency and spatial-resolution results in Section 3 are obtained by associating CE-65v2 clusters to tracks reconstructed from six ALPIDE planes, an external reference telescope. The telescope resolution of 2.2 um is quoted from a telescope optimizer, and the paper does not describe how the DUT spatial resolution was deconvolved from track residuals; however, an omitted or underdocumented extraction procedure is a reproducibility concern, not a circular reduction. No equation in the paper defines the predicted quantity in terms of the measured quantity, and no fitted parameter is renamed as a prediction. The self-citations (Ref. [9] for the process modification, Ref. [12] for the telescope optimizer) are normal cumulative evidence: Ref. [9] describes the device physics used to motivate the chip variants, not the measured performance, and Ref. [12] is an external tool used to estimate telescope resolution. There is no step where the claimed result is equivalent to its input by construction. Therefore the circularity score is 0.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The central claims rest on standard detector physics and analysis assumptions. No free parameters are fitted to produce the headline numbers; the seed and neighbour thresholds are scanned to generate the efficiency and resolution curves. The main assumptions are the 55Fe calibration, the telescope track model and resolution, the 3x3 cluster window, full depletion at 10 V reset, and the process descriptions from prior work.

assumptions (5)
  • domain assumption The 55Fe K_alpha X-ray line at 5.9 keV is a known calibration reference, and the Gaussian fit to its peak position in ADU provides the energy-to-electron conversion used throughout the analysis.
    Section 2 describes mapping ADU to energy by matching the K_alpha and K_beta peak positions; the conversion is then used to express thresholds in electrons in Section 3.
  • domain assumption The six-plane ALPIDE telescope provides an unbiased track estimate with 2.2 µm resolution at the device under test, and a straight-line track model is adequate.
    Section 3 states 'The telescope resolution was estimated to be 2.2 µm using a telescope optimizer' and tracks were reconstructed using a straight-line model requiring hits on all six planes.
  • domain assumption A 3x3 window around the seed pixel contains all or nearly all of the signal charge, with a maximum cluster size of 9, for both efficiency and charge-sharing measurements.
    Section 3: 'Clusters on the CE-65v2 chip were built by summing all pixels in a 3x3 window around a seed pixel'; the accumulated charge ratio is normalized by the total charge in this window.
  • domain assumption A resetting voltage of 10 V fully depletes the epitaxial layer for all studied variants, so the depletion and charge-collection behavior matches the process descriptions.
    Section 1: 'A resetting voltage of 10 V was applied throughout these studies in order to achieve full depletion.'
  • domain assumption Silicon produces about one electron-hole pair per 3.6 eV of deposited energy, so a 5.9 keV X-ray corresponds to roughly 1620 electrons.
    This standard conversion underlies the expression of energies and thresholds in electrons, though the exact value is not stated in the paper.

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Cite this review

Pith. "Pith review of Characterisation of analogue MAPS produced in the 65 nm TPSCo process." pith.science (2026). https://pith.science/paper/3TUC7KYU

@misc{pith2026241108740,
  author       = {Pith},
  title        = {Pith review of: Characterisation of analogue MAPS produced in the 65 nm TPSCo process},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3TUC7KYU}},
  note         = {Machine review of arXiv:2411.08740}
}
abstract

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, \SI{22.5}{\micro\meter}), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on $^{55}$Fe lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the $\mathcal{O}$(5\%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under \SI{2}{\micro\meter} during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the \SI{15}{\micro\meter} and \SI{22.5}{\micro\meter} chips achieving over 99\% efficiency up to a $\sim$180 e$^{-}$ seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

13 extracted references · 11 canonical work pages

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Reviewed August 12, 2026 · model on record in the stance chip above.