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REVIEW 3 major objections 5 minor 33 references

The paper claims that a thin dielectric layer with a selectively etched trench creates deterministic potential minima for single electrons on solid neon, suppressing surface-bound states while preserving the ~6.1 GHz orbital splitting measu

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

T0 review · deepseek-v4-flash

2026-08-02 05:10 UTC pith:3UM5VFWJ

load-bearing objection Fresh design idea, but the model as written cannot produce the reported eigenenergies: a missing image-charge term breaks the quantitative foundation. the 3 major comments →

arxiv 2607.13448 v2 pith:3UM5VFWJ submitted 2026-07-15 quant-ph cond-mat.mes-hall

Deterministic single-electron trapping on solid neon using engineered dielectric surface geometry

classification quant-ph cond-mat.mes-hall
keywords solid neonelectron-on-neon qubitsurface roughnessdielectric spacerdeterministic trappingSchrödinger–Poisson simulationorbital splittinglevitating electron
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Solid-neon electron qubits are attractive because the electron floats in vacuum, but uncontrolled surface roughness can bind electrons accidentally and cause noise. This paper proposes an engineered interface: a dielectric spacer that smooths the substrate, with a shallow trench etched into it where a qubit is intended to sit. Using three-dimensional Schrödinger–Poisson simulations, the authors show that the trench produces a deterministic lateral trap while the smooth spacer suppresses parasitic states. The computed orbital splitting of about 6.1 GHz is close to the published experimental values of 6.43 and 6.39 GHz, indicating the design preserves the low-energy spectrum needed for qubit operation.

Core claim

The central claim is that the combination of global smoothing and local patterning turns the surface geometry of solid neon from a source of disorder into a deterministic confinement tool. In the simulated device, a 10 nm dielectric layer (relative permittivity 3.5) planarizes the template, and a 6 nm-deep elliptical trench, sized at three-quarters of the buried gate, locally thins the dielectric so the gate field penetrates more strongly and creates a closed low-potential region. The resulting ground state is tightly localized above the trench, the first six states form a quantized orbital ladder, and the qubit splitting ΔE = E2 − E1 comes out at 6.105 GHz — within 3% of the smooth-gate bas

What carries the argument

The load-bearing feature is the engineered dielectric stack: a continuous spacer (εr = 3.5, 5 eV barrier, 10 nm thick) that planarizes the growth template, and a 6 nm-deep elliptical trench etched into it, conformally coated by the neon film. The trench locally reduces the dielectric thickness, increasing penetration of the gate field into the neon–vacuum region and forming a lateral potential well; the unetched spacer eliminates curvature-induced bound states elsewhere. The paper's analysis tool is a three-dimensional finite-difference Schrödinger–Poisson solver with divergence-form electrostatics and position-dependent permittivity, which is validated against the smooth-gate device before

Load-bearing premise

The whole design conclusion depends on the assumption that the effective single-electron potential used in the simulations — the material barrier minus the Poisson potential — completely captures the vertical binding of the electron, including the image-charge attraction that holds it above the neon surface; the paper does not state how that image term enters the Hamiltonian.

What would settle it

Run the solver exactly as described in Section II, with Vq(r) = Ec(r) − φ(r) and no additional terms, and compare the ground-state energy: if it comes out near the vacuum-level minimum of ≈ −0.995 eV rather than the reported ≈ −1.188 eV, then the reported spectrum — and the deterministic-trapping conclusion built on it — does not follow from the stated model.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

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If this is right

  • Deterministic, lithographically placed traps would replace probabilistic electron loading, so arrays of identical electron-on-neon qubits become feasible.
  • Because the etched-trench splitting (6.105 GHz) is within a few percent of the smooth-gate baseline and of measured values, existing microwave control and readout protocols should carry over essentially unchanged.
  • Surface roughness is a first-order design issue, not a minor imperfection: 3 nm RMS roughness changes the qubit frequency by roughly 4.4 GHz, so suppression is needed for reproducible devices.
  • Dielectric thickness and permittivity set a trade-off: thicker spacers smooth better but weaken the gate field and shrink the transition dipole, so an optimal device balances noise suppression with charge–photon coupling.
  • The same etch-based patterning could be applied to spin-qubit variants on neon, where reproducible positioning and known field geometry are prerequisites for spin–photon coupling.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the fabrication is realized, the same trench etch could define periodic qubit arrays by lithography alone, since trap position follows the trench rather than random morphology — an extension the paper gestures at but does not test.
  • The reported ground-state energies (≈ −1.188 eV) sit below the gate-defined vacuum-level minimum (≈ −0.995 eV), which implies the simulations depend on an image-charge attraction that the method section does not write down; making that term explicit would let others reproduce the spectrum and the 6.1-GHz splitting.
  • A direct testable prediction: on a device with the dielectric spacer but no trench, the qubit frequency should be close to the 6.2 GHz baseline; on an unplanarized rough device it should scatter to higher values near 10.6 GHz — a signature experimentalists could look for.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes an engineered device stack for solid-neon electron qubits: a smooth dielectric spacer beneath the neon film to suppress roughness-induced parasitic trapping, and a selectively etched elliptical trench in the dielectric to create deterministic single-electron trapping sites. The central numerical evidence comes from a 3D finite-difference Schrödinger–Poisson solver. The baseline smooth-gate geometry gives an orbital splitting ΔE=6.212 GHz, compared with experimental values 6.426 and 6.3915 GHz. Random neon-surface roughness is reported to shift the splitting to ~10.6 GHz, a dielectric spacer is then swept in thickness and permittivity, and an etched-trench geometry is shown to restore a splitting of 6.105 GHz with localized orbital wavefunctions. The abstract and conclusion claim that the combination of global smoothing and local topographic patterning enables deterministic electron trapping without sacrificing the low-energy orbital structure.

Significance. If the reported simulations are correct, this is a timely and experimentally actionable design concept for solid-neon electron qubits. The paper quantifies how realistic nanoscale roughness can perturb the qubit frequency, and it proposes a concrete fabrication-compatible mitigation strategy. The forward-simulation nature of the calculation is a strength: the baseline splitting is not fitted to the experiment, and the etched-trench ΔE=6.105 GHz is a genuine prediction. However, the Hamiltonian as written cannot produce the quoted eigenenergies, and the key roughness-suppression claim is not directly simulated. These issues must be resolved before the central conclusions can be accepted.

major comments (3)
  1. [§II (Eqs. 1–3), Table I] Section II, Eqs. (1)-(3) and Table I: the stated model cannot produce the reported spectrum. With Vq=Ec−φ and φ from the source-free Poisson equation under the stated Dirichlet boundary conditions (bottom 1.0 V, top 0.99 V, sides grounded), φ∈[0,1] V everywhere; in vacuum Ec=0, so Vq∈[−1,0] eV, and no eigenvalue can lie below −1 eV. Table I reports E1=−1.187675 eV, about 0.19 eV below the deepest available potential. The only physically plausible missing ingredient is an electron image-charge attraction, but no such term appears in Eqs. (1)-(3) or the Methods, which explicitly use the single-particle limit without density feedback. If the code silently includes an image term, the text is incomplete; if it does not, Table I cannot be reproduced. The validation and the trench-design conclusions rest on this underspecified Hamiltonian. Please state the full potential and sign convention, an
  2. [§V–§VI, Abstract] The roughness-suppression claim is not tested. Section V shows that a random rough neon surface (σ_rms=3 nm) shifts the orbital splitting from about 6.2 GHz to about 10.6 GHz. Section VI introduces the dielectric spacer and concludes that it planarizes the surface and suppresses parasitic trapping, but the only simulations shown for the spacer are smooth-stack sweeps over dielectric thickness and permittivity (Fig. 8) and a dipole-moment calculation (Fig. 9). The rough-surface protocol of Section V is never rerun with the dielectric present, so there is no numerical evidence that the dielectric suppresses roughness-induced localization or qubit-frequency shifts. Please repeat the Section V rough realization with the dielectric stack and report ΔE and wavefunction localization.
  3. [§VII] The deterministic-trap conclusion is demonstrated for one hand-picked geometry only (trench axes 0.75 times the gate axes, depth 6 nm). Since the paper claims that electrons are ‘reliably captured’ at engineered minima, the argument would be substantially stronger with a small design-space study, e.g., etching-depth variation, lateral misalignment between the trench and the gate, and sensitivity to dielectric/neon thickness. As currently presented, the central ‘deterministic’ claim rests on a single point in parameter space.
minor comments (5)
  1. [Eq. (1)] The notation is internally inconsistent: Vq is called an effective potential energy, but the Hamiltonian contains a factor −e multiplying Vq. If Vq is an energy, the factor should not be present; if Vq is an electrostatic potential in volts, Eq. (2) should define the energy operator differently. The sign convention should be stated explicitly.
  2. [§V] The sentence beginning ‘However, it did not provide a direct nanoscale map…’ is incomplete and should be rewritten.
  3. [Fig. 9] Axis labels such as ‘jd01j’ and ‘Cm’ appear to be raw MATLAB variable names; use standard notation such as |d01| and units of C·m.
  4. [References [13],[14]] References [13] and [14] appear to describe the same paper with different publication years. Please verify the citations.
  5. [General] A code/data availability statement would aid reproducibility and would let readers confirm whether the image-charge potential is implemented.

Circularity Check

0 steps flagged

No circular reduction: trench ΔE is a forward simulation; however, Table I energies are unreachable from the stated Hamiltonian, a non-circular but serious reproducibility gap.

full rationale

No significant circularity. The paper's main deliverable—the etched-trench ΔE=6.105 GHz (Table II) versus the smooth-gate baseline of 6.212 GHz (Table I)—is obtained by forward solution of Eqs. (1)–(3) for stated geometries; the experimental splittings of 6.426/6.3915 GHz are used only as benchmark comparisons and the gate geometry/barrier parameters are taken from the cited experiments, so the agreement is not a fitted-input prediction. The dielectric thickness, relative permittivity, and trench dimensions are design choices varied in sweeps, not parameters optimized to reproduce the benchmark, so there is no definitional identity between input and output. The only self-citation, Ref. [33], motivates the representative roughness profile in Sec. V, but the paper explicitly says it 'did not provide a direct nanoscale map' and a constructed profile is used; this citation is therefore not load-bearing. I do flag a separate, non-circular incompleteness: with grounded sides and Dirichlet plates at 1.0 V and 0.99 V, φ ∈ [0,1] V in vacuum, so Vq = Ec − φ from Eq. (2) is at most −1.0 eV in vacuum, yet Table I lists E1 = −1.187675 eV. No image-charge term or electron-density feedback into Poisson is described, so the stated equations cannot generate the reported spectrum; an undocumented potential must be present. This undermines the validation and the trench-design conclusions as model reproduction, but it is not an equivalence-by-construction or fit-renamed-as-prediction circularity.

Axiom & Free-Parameter Ledger

6 free parameters · 6 axioms · 0 invented entities

The paper's free parameters are mostly geometry/material values chosen by hand; none are explicitly fitted to the experimental target, but dielectric thickness and trench geometry are tuned to keep ΔE near 6 GHz. The main unaccounted element is the electron image potential, which is load-bearing and undocumented.

free parameters (6)
  • Gate bias configuration = V_bottom=1.0 V, V_top=0.99 V
    Sets the vertical electric field and absolute energy scale; chosen to mimic the far-field environment, not tied to a specific experimental bias.
  • Dielectric permittivity and barrier = ε_r=3.5, barrier=5 eV
    Nominal value; Fig. 8d sweeps ε_r=4–20, so the main design result depends on a hand-picked dielectric constant.
  • Dielectric thickness = H=10 nm
    Nominal; Fig. 8c shows ΔE varies strongly with H, and 10 nm keeps the qubit frequency near the 6 GHz baseline — effectively a design tune.
  • Trench geometry = depth 6 nm; semi-axes 0.75×gate
    Chosen by hand to keep the trap aligned with the gate and produce confinement comparable to the baseline.
  • Roughness profile = σ_rms=3 nm, clipped ±3 nm
    A representative Gaussian-random profile; Ref. [33] provides no nanoscale topography, so the roughness analysis uses an invented surface.
  • Neon thickness = L_Ne=10 nm
    Nominal conformal layer; a key assumption for the etched-trench design since neon is assumed to coat sidewalls.
axioms (6)
  • standard math Single-particle Schrödinger equation with a static potential describes the electron
    Eq. (1); standard non-relativistic single-electron description.
  • standard math Poisson's equation with fixed Dirichlet boundaries and piecewise-constant dielectrics gives the electrostatic potential
    Eq. (3); standard electrostatics.
  • ad hoc to paper An electron self-image potential is (apparently) included, though never described
    Needed to reconcile Table I energies (~ −1.188 eV) with the gate-only potential minimum (~ −0.995 eV); the methods do not mention its inclusion.
  • domain assumption Neon deposition conformally coats etched dielectric features
    §VII: 'the neon layer then conforms to the etched profile'; if the 6 nm trench is not conformally coated, the deterministic well will not form as simulated.
  • domain assumption The random roughness model represents real film morphology
    §V: profile is constructed because Ref. [33] provides no direct nanoscale map; conclusions about roughness rely on this invented surface.
  • domain assumption Top boundary at z=100 nm with V=0.99 V represents the far field
    §II: the field drops over a large length; truncating at 100 nm with a chosen voltage is a modeling assumption.

pith-pipeline@v1.3.0-alltime-deepseek · 9964 in / 19756 out tokens · 208963 ms · 2026-08-02T05:10:03.369119+00:00 · methodology

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Cite this review

Pith. "Pith review of Deterministic single-electron trapping on solid neon using engineered dielectric surface geometry." pith.science (2026). https://pith.science/paper/3UM5VFWJ

@misc{pith2026260713448,
  author       = {Pith},
  title        = {Pith review of: Deterministic single-electron trapping on solid neon using engineered dielectric surface geometry},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3UM5VFWJ}},
  note         = {Machine review of arXiv:2607.13448}
}
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read the original abstract

Levitating electron qubit on the surface of solid neon has recently emerged as a promising and intrinsically noise-resilient platform for quantum information processing. Their ultra-clean, inert environment suppresses conventional decoherence pathways associated with lattice disorder, charge traps, and nuclear-spin baths that limit coherence in semiconductor qubits. Yet, uncontrolled surface features such as bumps, valleys, and electrode-defined gaps can bind electrons unintentionally, contributing charge noise and inducing spin-orbit coupling mediated decoherence. To address this challenge, we propose an engineered interface in which a dielectric layer is deposited beneath the solid neon to provide an atomically smooth template, eliminating surface-roughness induced trapping. By selectively etching this dielectric layer at desired qubit locations, deterministic potential minima can be engineered to reliably capture electrons while suppressing unwanted surface bound states. We perform large-scale Schrodinger and Poisson simulation to compare the existing and proposed strategies of electron trapping on neon, obtaining good agreement with recent experimental measurements.

Figures

Figures reproduced from arXiv: 2607.13448 by Andrew Palmer, Eric Helgemo, Kundan Surse, Lukas Delventhal, Maja Cassidy, Md Serajum Monir, Rajib Rahman, Thanh Nguyen.

Figure 1
Figure 1. Figure 1: FIG. 1: Device geometry used in the simulations: (a) Simulation domain shown in dotted [PITH_FULL_IMAGE:figures/full_fig_p007_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2: Electrostatic potential landscape and ground-state wavefunction of the [PITH_FULL_IMAGE:figures/full_fig_p008_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3: Probability-density distributions of the first six eigenstates, showing the [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4: Representative bump and valley surface geometries and their corresponding [PITH_FULL_IMAGE:figures/full_fig_p011_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5: Dependence of the two lowest orbital energies on bump geometry parameters: (a) [PITH_FULL_IMAGE:figures/full_fig_p012_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6: Dependence of the two lowest orbital energies on valley geometry parameters: (a) [PITH_FULL_IMAGE:figures/full_fig_p013_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7: Random neon surface roughness simulation and the corresponding three-dimensional [PITH_FULL_IMAGE:figures/full_fig_p014_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8: (a) Device stack with dielectric layer. (b) Variation of the two lowest orbital energies [PITH_FULL_IMAGE:figures/full_fig_p016_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9: Transition dipole length [PITH_FULL_IMAGE:figures/full_fig_p017_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10: Device geometry and electrostatic confinement produced by the dielectric-etched [PITH_FULL_IMAGE:figures/full_fig_p019_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11: First six bound-state probability densities [PITH_FULL_IMAGE:figures/full_fig_p021_11.png] view at source ↗

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Reference graph

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