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HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling

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arxiv 2212.03354 v1 pith:44EPNDHV submitted 2022-12-06 cs.LG cs.ARcs.NEcs.PF

HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling

classification cs.LG cs.ARcs.NEcs.PF
keywords dynamicefficiencyhadasarchitectureedgefeaturesneuralbackbone
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In many cases, the implementation of DyNNs can be sub-optimal due to its underlying backbone architecture being developed at the design stage independent of both: (i) the dynamic computing features, e.g. early exiting, and (ii) the resource efficiency features of the underlying hardware, e.g., dynamic voltage and frequency scaling (DVFS). Addressing this, we present HADAS, a novel Hardware-Aware Dynamic Neural Architecture Search framework that realizes DyNN architectures whose backbone, early exiting features, and DVFS settings have been jointly optimized to maximize performance and resource efficiency. Our experiments using the CIFAR-100 dataset and a diverse set of edge computing platforms have seen HADAS dynamic models achieve up to 57% energy efficiency gains compared to the conventional dynamic ones while maintaining the desired level of accuracy scores. Our code is available at https://github.com/HalimaBouzidi/HADAS

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