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ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models

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arxiv 2406.18770 v2 pith:AG7Z7QMT submitted 2024-06-26 cs.LG

Yuxuan Yin , Yu Wang , Boxun Xu , Peng Li This is my paper · ORCID
classification cs.LG
keywords designoptimizationanalogado-llmbayesianhighmodelspoints
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Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine learning based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM's ability to infuse domain knowledge to rapidly generate viable design points to remedy BO's inefficiency in finding high value design areas specifically under the limited design space coverage of the BO's probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO's exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness.

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Cited by 8 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. OpenAlex reports about 37 citations worldwide. Full citation record

  1. SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

    cs.AR 2026-07 conditional novelty 7.0 of 10

    An NDA-safe scrubbed boundary lets cloud LLMs optimize analog circuits in real Cadence flows; multi-model PVT benchmarks show successful closure on LC-VCO (7/11) and two-stage op-amp (4/11) tasks.

  2. DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits

    cs.ET 2025-07 conditional novelty 7.0 of 10

    DiffCkt uses three diffusion networks to predict amplifier component counts, topology, and transistor sizes from performance specifications, and reports 2.21x to 8365x higher generation efficiency than prior analog EDA tools.

  3. LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits

    cs.LG 2024-11 conditional novelty 7.0 of 10

    LEDRO uses an LLM to propose refined parameter ranges, then runs TuRBO inside those ranges, beating full-space Bayesian optimization on a 22-topology, 4-node op-amp benchmark.

  4. White-Box Reasoning: Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design

    cs.AR 2025-08 conditional novelty 6.0 of 10

    An LLM grounded in gm/Id transistor lookup tables sizes a two-stage op-amp to spec in five iterations, claimed about an order of magnitude faster than a senior engineer.

  5. Schemato -- An LLM for Netlist-to-Schematic Conversion

    cs.LG 2024-11 conditional novelty 6.0 of 10

    A fine-tuned LLM converts circuit netlists to LTSpice .asc schematics with higher compilation and structural similarity than GPT-4o and Llama baselines.

  6. A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction

    cs.AI 2025-06 conditional novelty 5.0 of 10

    An LLM multi-agent framework extracts sizing relationships from analog circuit papers to prune the optimizer's search space, reporting 2.32 to 26.6 times faster sizing and higher pass rates on three circuits.

  7. AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection

    cs.CV 2025-05 conditional novelty 5.0 of 10

    AMSnet 2.0 is a 2,686-circuit analog schematic dataset, and the paper's U-Net plus split-merge pipeline extracts netlists and reconstructs digital schematics with F1 scores between 80.39 and 90.19.

  8. A Survey of Research in Large Language Models for Electronic Design Automation

    cs.LG 2025-01 conditional novelty 2.0 of 10

    A survey of LLM applications in electronic design automation, organized by design stage and adaptation technique.

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