Paper Citation Record · LEDGER

LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 8 inbound Pith citation observations for arXiv:2504.21770.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2504.21770 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 8 of 8 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 8 of 8 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-06T10:13:22.905355Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-01T14:05:46.780163Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 909a1a83-3653-4e7e-93ae-c2ecc59b60c4 · inbound

LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification cites this paper.

LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-05-16T17:53:11.577490Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 768b6edf-0bf5-490f-a57a-aaca90c412ef · inbound

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog cites this paper.

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 7

Resolution: verified exact; arxiv_id, observed 2026-05-10T11:45:21.405107Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c1ae19c1-f58c-4dd9-8db6-8f08b8f535f5 · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 42

Resolution: verified exact; arxiv_id, observed 2026-05-12T06:51:26.812604Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 94338e35-2c4b-49a5-8626-05287d863630 · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 44

Resolution: verified exact; arxiv_id, observed 2026-05-14T21:12:58.787364Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d18b828c-e630-4a97-9329-d72dbee9d1be · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 44

Resolution: verified exact; arxiv_id, observed 2026-05-21T08:59:55.375280Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4ff916a1-ba4c-4e45-b84b-fa627dd44d51 · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 44

Resolution: verified exact; arxiv_id, observed 2026-07-01T14:05:46.781880Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 652db53f-a3b0-4fd9-8165-7345dce17f5d · inbound

CHARGE: Leveraging CWE Hierarchies for Hardware Security SystemVerilog Assertion Generation cites this paper.

CHARGE: Leveraging CWE Hierarchies for Hardware Security SystemVerilog Assertion Generation LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-01T01:40:53.775456Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 80c254fc-6eda-4d6b-8c88-9eb7a5df8ae5 · inbound

Hardware Design and Security in the Era of Chiplets and LLMs cites this paper.

Hardware Design and Security in the Era of Chiplets and LLMs LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 74

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.905355Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.