Hardware Design and Security in the Era of Chiplets and LLMs | Paper Citation Record

Observation 4d634498-161a-4edd-8cbe-d528687d0700 · outbound

This paper cites Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor families: Industrial product,.

Hardware Design and Security in the Era of Chiplets and LLMs Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor families: Industrial product,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:32.452943Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e4abcbf4-281a-4790-b3db-eae037c0af44 · outbound

This paper cites [Online].

Hardware Design and Security in the Era of Chiplets and LLMs [Online]

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:32.219491Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 36c33d17-c6d7-4ece-85ad-90a6b05f976c · outbound

This paper cites Sapphire rapids: The next-generation Intel Xeon scalable processor,.

Hardware Design and Security in the Era of Chiplets and LLMs Sapphire rapids: The next-generation Intel Xeon scalable processor,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:31.959421Z

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Observation 2f79e9d0-1678-4590-b7fa-a21ef3a632e3 · outbound

This paper cites 2.5D root of trust: Secure system-level integration of untrusted chiplets,.

Hardware Design and Security in the Era of Chiplets and LLMs 2.5D root of trust: Secure system-level integration of untrusted chiplets,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:31.704837Z

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Observation a810296a-0d24-4c7e-968f-00159c5ae657 · outbound

This paper cites Coherence attacks and countermeasures in interposer-based chiplet systems,.

Hardware Design and Security in the Era of Chiplets and LLMs Coherence attacks and countermeasures in interposer-based chiplet systems,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:31.371081Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 7e9f9df6-ff79-4323-870c-525b1bb37b71 · outbound

This paper cites On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and innovations,.

Hardware Design and Security in the Era of Chiplets and LLMs On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and innovations,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:31.125012Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 786d4075-d51f-4234-8f78-9a7ef5461c38 · outbound

This paper cites Cambricon-LLM: A chiplet-based hybrid architecture for on-device inference of 70B LLM,.

Hardware Design and Security in the Era of Chiplets and LLMs Cambricon-LLM: A chiplet-based hybrid architecture for on-device inference of 70B LLM,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:30.986545Z

Source-reported events for the cited work

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Observation b9b2ab81-4977-4928-8df0-47be3e9fb641 · outbound

This paper cites Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models.

Hardware Design and Security in the Era of Chiplets and LLMs Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models

Reference 8

Resolution: verified exact; local_arxiv, observed 2026-08-06T10:13:24.223943Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 08a6fc24-31d5-48fd-8809-ceca4df77300 · outbound

This paper cites CHIME: Chiplet-based heterogeneous near-memory acceleration for edge multimodal LLM inference,.

Hardware Design and Security in the Era of Chiplets and LLMs CHIME: Chiplet-based heterogeneous near-memory acceleration for edge multimodal LLM inference,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:16.585770Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f80af512-f00b-4374-a759-00f85ec6404d · outbound

This paper cites LLMs and the future of chip design: Unveiling security risks and building trust,.

Hardware Design and Security in the Era of Chiplets and LLMs LLMs and the future of chip design: Unveiling security risks and building trust,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:30.811237Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b6790aa9-5559-4100-b6ab-ab9273f2148f · outbound

This paper cites LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges.

Hardware Design and Security in the Era of Chiplets and LLMs LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

Reference 11

Resolution: verified exact; local_arxiv, observed 2026-08-06T10:13:24.005507Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 054426a6-4336-4f4e-aec7-295914ef2602 · outbound

This paper cites Large language models (LLMs) for electronic design automation (EDA): Special session paper,.

Hardware Design and Security in the Era of Chiplets and LLMs Large language models (LLMs) for electronic design automation (EDA): Special session paper,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:30.683612Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 9fde4eef-98f2-4774-8d0e-5e3d6e623745 · outbound

This paper cites VeriGen: A large language model for Verilog code generation,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriGen: A large language model for Verilog code generation,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:30.481644Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 20b9cd47-21b8-463a-a352-2edfe95a0560 · outbound

This paper cites Automatically improving LLM-based Verilog generation using EDA tool feedback,.

Hardware Design and Security in the Era of Chiplets and LLMs Automatically improving LLM-based Verilog generation using EDA tool feedback,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:30.308733Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ea41fb18-92f0-40d5-8927-5fe9d757f53d · outbound

This paper cites VeriLeaky: Navigating IP protection vs utility in fine-tuning for LLM-driven Verilog coding,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriLeaky: Navigating IP protection vs utility in fine-tuning for LLM-driven Verilog coding,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:30.143815Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c4a9b193-1270-4ab9-be15-591265617355 · outbound

This paper cites RTL-Breaker: Assessing the security of LLMs against backdoor attacks on HDL code generation,.

Hardware Design and Security in the Era of Chiplets and LLMs RTL-Breaker: Assessing the security of LLMs against backdoor attacks on HDL code generation,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:29.987146Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation bc8cca33-9443-4c69-ad5e-fb8c58697ad5 · outbound

This paper cites VeriContaminated: Assessing LLM-driven Verilog coding for data contamination,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriContaminated: Assessing LLM-driven Verilog coding for data contamination,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:29.824125Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d6452aaa-3181-4bc0-b65d-dec8010692fe · outbound

This paper cites (Security) assertions by large language models,.

Hardware Design and Security in the Era of Chiplets and LLMs (Security) assertions by large language models,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:29.698704Z

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No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d743f4ab-e7f0-4933-9969-29796e18bd98 · outbound

This paper cites an unresolved cited work.

Hardware Design and Security in the Era of Chiplets and LLMs Unresolved cited work

Reference 19

Resolution: unresolved; raw_fallback, observed 2026-08-06T10:13:29.541347Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f71d4e40-f0c0-43d4-86c3-dc8590f9dc78 · outbound

This paper cites Pioneering chiplet technology and design for the AMD EPYC and Ryzen processor families: Industrial product,.

Hardware Design and Security in the Era of Chiplets and LLMs Pioneering chiplet technology and design for the AMD EPYC and Ryzen processor families: Industrial product,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:29.374484Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 05ce852c-8297-4bc0-ad7e-f0a7287bf98f · outbound

This paper cites 3D integration: Another dimension toward hardware security,.

Hardware Design and Security in the Era of Chiplets and LLMs 3D integration: Another dimension toward hardware security,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:29.256098Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0e5a113f-da4b-465a-aa52-49677289c69c · outbound

This paper cites NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?.

Hardware Design and Security in the Era of Chiplets and LLMs NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:29.056676Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 624d05b7-fc8e-4a10-81b9-d96276680fc1 · outbound

This paper cites Modular routing design for chiplet-based systems,.

Hardware Design and Security in the Era of Chiplets and LLMs Modular routing design for chiplet-based systems,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.959580Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 41c6e913-4222-4abc-a9c7-06c2a20c5e47 · outbound

This paper cites Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS.

Hardware Design and Security in the Era of Chiplets and LLMs Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:17.736131Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 131e0f3f-42b4-4827-9e2e-60af759f201d · outbound

This paper cites VeriThoughts: Enabling automated Verilog code generation using reasoning and formal verification,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriThoughts: Enabling automated Verilog code generation using reasoning and formal verification,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:17.821573Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 71b7d99d-004a-4262-9df9-42e197c64547 · outbound

This paper cites From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design.

Hardware Design and Security in the Era of Chiplets and LLMs From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:17.918881Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4c5da9ec-064d-4d1e-bd74-135f2d44a36d · outbound

This paper cites C2HLSC: Leveraging large language models to bridge the software-to-hardware design gap,.

Hardware Design and Security in the Era of Chiplets and LLMs C2HLSC: Leveraging large language models to bridge the software-to-hardware design gap,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.825331Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5450b29b-9a2e-40a1-9035-4666e03b7a1f · outbound

This paper cites LLM-driven code generation for neural networks on FPGAs: Bridging Python and HLS,.

Hardware Design and Security in the Era of Chiplets and LLMs LLM-driven code generation for neural networks on FPGAs: Bridging Python and HLS,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.626046Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c255d8b9-0d72-447b-8e95-137867ab2117 · outbound

This paper cites RTL++: Graph-enhanced LLM for RTL Code Generation.

Hardware Design and Security in the Era of Chiplets and LLMs RTL++: Graph-enhanced LLM for RTL Code Generation

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.224348Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8e692ef7-9cb4-445f-863e-eae7c319f237 · outbound

This paper cites Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form.

Hardware Design and Security in the Era of Chiplets and LLMs Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.327854Z

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Unavailable: canonical work link unavailable.

Observation 28dc7789-2f18-4267-8e9d-86bbf56aa139 · outbound

This paper cites Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification.

Hardware Design and Security in the Era of Chiplets and LLMs Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.402301Z

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Unavailable: canonical work link unavailable.

Observation f56ec65f-5b5a-4593-8622-190a76c3905c · outbound

This paper cites Hybrid-NL2SV A: Integrating RAG and finetuning for LLM-based NL2SV A,.

Hardware Design and Security in the Era of Chiplets and LLMs Hybrid-NL2SV A: Integrating RAG and finetuning for LLM-based NL2SV A,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.516976Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4c21de54-efd4-44e0-815b-302a87e7ace9 · outbound

This paper cites LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines.

Hardware Design and Security in the Era of Chiplets and LLMs LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.606997Z

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Unavailable: canonical work link unavailable.

Observation ff414ed6-b988-4f9a-9212-2de49ca84737 · outbound

This paper cites VeriDispatcher: Multi-model dispatching through pre-inference difficulty prediction for RTL generation optimization,.

Hardware Design and Security in the Era of Chiplets and LLMs VeriDispatcher: Multi-model dispatching through pre-inference difficulty prediction for RTL generation optimization,

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.692047Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e0fbc683-6024-4ec1-be9f-851537562a2d · outbound

This paper cites Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes.

Hardware Design and Security in the Era of Chiplets and LLMs Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.864533Z

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Unavailable: canonical work link unavailable.

Observation 9cd7485e-a228-4d98-a93c-a32d44d48d36 · outbound

This paper cites Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation.

Hardware Design and Security in the Era of Chiplets and LLMs Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation

Reference 36

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:18.970784Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b86133c5-290e-4f1d-835f-20eb2d894686 · outbound

This paper cites A survey of network-on-chip security attacks and countermea- sures,.

Hardware Design and Security in the Era of Chiplets and LLMs A survey of network-on-chip security attacks and countermea- sures,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.394319Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e8da0dda-ae5b-4e22-8496-72e332ceddda · outbound

This paper cites Cache hierarchy and memory subsystem of the AMD Opteron processor,.

Hardware Design and Security in the Era of Chiplets and LLMs Cache hierarchy and memory subsystem of the AMD Opteron processor,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.219998Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 572c2f29-cea5-4623-b71c-db6094945f64 · outbound

This paper cites Hardware Trojan threats to cache coherence in modern 2.5D chiplet systems,.

Hardware Design and Security in the Era of Chiplets and LLMs Hardware Trojan threats to cache coherence in modern 2.5D chiplet systems,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.105654Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 397f0e9c-f7fc-4b4a-ab93-aa38acfe3a10 · outbound

This paper cites Cache me, catch you: Cache related security threats in LLM serving frameworks,.

Hardware Design and Security in the Era of Chiplets and LLMs Cache me, catch you: Cache related security threats in LLM serving frameworks,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:28.002665Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b03ad7f7-1e83-4f77-9bd6-bccbb3692d3b · outbound

This paper cites I know what you said: Unveiling hardware cache side-channels in local large language model inference,.

Hardware Design and Security in the Era of Chiplets and LLMs I know what you said: Unveiling hardware cache side-channels in local large language model inference,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.879714Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4fb4439f-95df-450e-8e6c-9aea6e7d7be2 · outbound

This paper cites Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing,.

Hardware Design and Security in the Era of Chiplets and LLMs Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.731491Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d14ff061-f4c2-49fe-b0af-cadf9d99640a · outbound

This paper cites Meltdown.

Hardware Design and Security in the Era of Chiplets and LLMs Meltdown

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:19.866165Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e491a1f5-15af-47e4-a52f-dd529ca03f56 · outbound

This paper cites BADFET: Defeating modern secure boot using second-order pulsed electromagnetic fault injection,.

Hardware Design and Security in the Era of Chiplets and LLMs BADFET: Defeating modern secure boot using second-order pulsed electromagnetic fault injection,

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.612968Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 73c56f4d-3d5c-44b6-839b-1a7ddf81128a · outbound

This paper cites Drammer: Deterministic Rowhammer attacks on mobile platforms,.

Hardware Design and Security in the Era of Chiplets and LLMs Drammer: Deterministic Rowhammer attacks on mobile platforms,

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.474753Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation bee647bf-871d-49c8-a5c4-e5bdbfe1a2a6 · outbound

This paper cites Probing attacks on integrated circuits: Challenges and research opportunities,.

Hardware Design and Security in the Era of Chiplets and LLMs Probing attacks on integrated circuits: Challenges and research opportunities,

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.343240Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4c5ff5be-7353-4893-b020-44ebf0e884b5 · outbound

This paper cites Can transformer memory be corrupted? investigating cache- side vulnerabilities in large language models,.

Hardware Design and Security in the Era of Chiplets and LLMs Can transformer memory be corrupted? investigating cache- side vulnerabilities in large language models,

Reference 47

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:20.297286Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b01987eb-19a9-4b14-bfce-aee50b4ec5f1 · outbound

This paper cites GhostWriter: Exploiting GPU-cache contention to steal and steer multi-tenant large-language-model inference,.

Hardware Design and Security in the Era of Chiplets and LLMs GhostWriter: Exploiting GPU-cache contention to steal and steer multi-tenant large-language-model inference,

Reference 48

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.182596Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1d74bd1d-1678-402f-b574-067915e0b2ed · outbound

This paper cites Liu et al.,Securing system-on-chips: Hardware protection in the age of chiplets, PUFsecurity, 2023.

Hardware Design and Security in the Era of Chiplets and LLMs Liu et al.,Securing system-on-chips: Hardware protection in the age of chiplets, PUFsecurity, 2023

Reference 49

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:27.078598Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 94a44021-a288-438d-af35-0d435d010b08 · outbound

This paper cites Concerted wire lifting: Enabling secure and cost-effective split manufacturing,.

Hardware Design and Security in the Era of Chiplets and LLMs Concerted wire lifting: Enabling secure and cost-effective split manufacturing,

Reference 50

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:26.940814Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 37b3a9f7-d21a-430a-8331-aa4abe8a2cbb · outbound

This paper cites A modern approach to IP protection and Trojan prevention: Split manufacturing for 3D ICs and obfuscation of vertical interconnects,.

Hardware Design and Security in the Era of Chiplets and LLMs A modern approach to IP protection and Trojan prevention: Split manufacturing for 3D ICs and obfuscation of vertical interconnects,

Reference 51

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:26.778316Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 6b008847-d6ab-4554-96f8-44997b298cbe · outbound

This paper cites Security-aware 2.5D integrated circuit design flow against hardware IP piracy,.

Hardware Design and Security in the Era of Chiplets and LLMs Security-aware 2.5D integrated circuit design flow against hardware IP piracy,

Reference 52

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:26.612315Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c59300a8-cae2-4d14-b40a-9f105693c8cf · outbound

This paper cites Design flow for active interposer-based 2.5D ICs and study of RISC-V architecture with secure NoC,.

Hardware Design and Security in the Era of Chiplets and LLMs Design flow for active interposer-based 2.5D ICs and study of RISC-V architecture with secure NoC,

Reference 53

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:26.440337Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation fddf765f-799a-44db-9491-2ced51a6afc7 · outbound

This paper cites Physical attack protection techniques for IC chip level hardware security,.

Hardware Design and Security in the Era of Chiplets and LLMs Physical attack protection techniques for IC chip level hardware security,

Reference 54

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:26.236428Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f37b96b6-4a83-43f4-8240-98678508c576 · outbound

This paper cites SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation.

Hardware Design and Security in the Era of Chiplets and LLMs SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation

Reference 55

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:21.159302Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation be6d7725-de18-4db3-8967-38e201974582 · outbound

This paper cites Semantic consensus decoding: Backdoor defense for Verilog code generation,.

Hardware Design and Security in the Era of Chiplets and LLMs Semantic consensus decoding: Backdoor defense for Verilog code generation,

Reference 56

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:21.265040Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f40016cb-1284-422b-992c-764b85394b22 · outbound

This paper cites Benchmarking large language models under data contamination: A survey from static to dynamic evaluation,.

Hardware Design and Security in the Era of Chiplets and LLMs Benchmarking large language models under data contamination: A survey from static to dynamic evaluation,

Reference 57

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:26.101804Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 3dfbaee4-9144-42f8-8e30-935378321a95 · outbound

This paper cites SALAD: Systematic assessment of machine unlearning on LLM- aided hardware design,.

Hardware Design and Security in the Era of Chiplets and LLMs SALAD: Systematic assessment of machine unlearning on LLM- aided hardware design,

Reference 58

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.917756Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation cd228115-3081-49b9-8cb1-a2ac1c14aa5a · outbound

This paper cites Prompt injection attacks in large language models and AI agent systems: A comprehensive review of vulnerabilities, attack vectors, and defense mechanisms,.

Hardware Design and Security in the Era of Chiplets and LLMs Prompt injection attacks in large language models and AI agent systems: A comprehensive review of vulnerabilities, attack vectors, and defense mechanisms,

Reference 59

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.786906Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 511e8cd4-d376-47d9-9d82-361be59f1e02 · outbound

This paper cites HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking.

Hardware Design and Security in the Era of Chiplets and LLMs HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking

Reference 60

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:21.678239Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 890564ea-19d8-4293-99ad-d42dd1496b44 · outbound

This paper cites CircuitGuard: Mitigating LLM memorization in RTL code generation against IP leakage,.

Hardware Design and Security in the Era of Chiplets and LLMs CircuitGuard: Mitigating LLM memorization in RTL code generation against IP leakage,

Reference 61

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.624260Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e4c16fed-333a-4763-8155-f92ebebd19ba · outbound

This paper cites GLLaMoR: Graph-based logic locking by large language models for enhanced robustness,.

Hardware Design and Security in the Era of Chiplets and LLMs GLLaMoR: Graph-based logic locking by large language models for enhanced robustness,

Reference 62

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.488121Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ed559d4a-0057-490f-b2bc-0b08680c5f15 · outbound

This paper cites LockForge: Automating paper-to-code for logic locking with multi-agent reasoning LLMs,.

Hardware Design and Security in the Era of Chiplets and LLMs LockForge: Automating paper-to-code for logic locking with multi-agent reasoning LLMs,

Reference 63

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.340538Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 2cfc3532-9737-40c4-badd-1d11d29bfeb8 · outbound

This paper cites Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection.

Hardware Design and Security in the Era of Chiplets and LLMs Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection

Reference 64

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.030650Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b6ca95a5-3924-4bdf-a166-74c30bbd68b9 · outbound

This paper cites ARIANNA: An automatic design flow for fabric customization and eFPGA redaction,.

Hardware Design and Security in the Era of Chiplets and LLMs ARIANNA: An automatic design flow for fabric customization and eFPGA redaction,

Reference 65

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.204272Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 303b1c26-c606-42a2-a35b-bcf0a2435219 · outbound

This paper cites Netlist whisperer: Extensive analysis of circuit leakage using LLMs,.

Hardware Design and Security in the Era of Chiplets and LLMs Netlist whisperer: Extensive analysis of circuit leakage using LLMs,

Reference 66

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:25.070225Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d727b3cd-dc0b-4541-8ae8-5db991db0d3e · outbound

This paper cites LLM4PQC - accurate and efficient synthesis of PQC cores by feedback-driven LLMs,.

Hardware Design and Security in the Era of Chiplets and LLMs LLM4PQC - accurate and efficient synthesis of PQC cores by feedback-driven LLMs,

Reference 67

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:24.953479Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 823dea83-b0fe-4fd5-82d6-f5ab4f65d0e1 · outbound

This paper cites LLM4SecurePQC: LLM-driven and side-channel resilient hardware synthesis of PQC cores,.

Hardware Design and Security in the Era of Chiplets and LLMs LLM4SecurePQC: LLM-driven and side-channel resilient hardware synthesis of PQC cores,

Reference 68

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:24.819028Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f49f9f5c-f7d9-468d-8ffb-45d0f4a6eadf · outbound

This paper cites Graph neural networks for integrated circuit design, reliability, and security: Survey and tool,.

Hardware Design and Security in the Era of Chiplets and LLMs Graph neural networks for integrated circuit design, reliability, and security: Survey and tool,

Reference 69

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:24.668783Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation a3a390e9-c3b7-413a-8895-5bb0950ed4a8 · outbound

This paper cites TrojanLoC: Fine-grained hardware Trojan detection from Verilog code,.

Hardware Design and Security in the Era of Chiplets and LLMs TrojanLoC: Fine-grained hardware Trojan detection from Verilog code,

Reference 70

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.492453Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a3f4bbf6-95a0-45cf-8c28-cd8f71529c6c · outbound

This paper cites NetDeTox: Adversarial and efficient evasion of hardware-security GNNs via RL-LLM orchestration,.

Hardware Design and Security in the Era of Chiplets and LLMs NetDeTox: Adversarial and efficient evasion of hardware-security GNNs via RL-LLM orchestration,

Reference 71

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:24.495279Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 596b3393-bc63-4202-910b-a7718bb178f9 · outbound

This paper cites TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion.

Hardware Design and Security in the Era of Chiplets and LLMs TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion

Reference 72

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.669056Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b4d1be42-47ae-485a-b5ea-936c59467dad · outbound

This paper cites VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog.

Hardware Design and Security in the Era of Chiplets and LLMs VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog

Reference 73

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.805325Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 80c254fc-6eda-4d6b-8c88-9eb7a5df8ae5 · outbound

This paper cites LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs.

Hardware Design and Security in the Era of Chiplets and LLMs LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Reference 74

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.905355Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a45f71e7-7366-43f9-957b-0d8b27b3b4f5 · outbound

This paper cites MARVEL: Multi-agent RTL vulnerability extraction using large language models,.

Hardware Design and Security in the Era of Chiplets and LLMs MARVEL: Multi-agent RTL vulnerability extraction using large language models,

Reference 75

Resolution: unresolved; no resolver link, observed 2026-08-06T10:13:22.981251Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b73d2b68-1814-48f1-aafb-23ce83a8c049 · outbound

This paper cites FLAG: Finding line anomalies (in RTL code) with generative AI,.

Hardware Design and Security in the Era of Chiplets and LLMs FLAG: Finding line anomalies (in RTL code) with generative AI,

Reference 76

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T10:13:24.347268Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Coverage vector

Reference resolution

Outbound references

Pith citing papers