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Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor
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Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor
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Fault-tolerant quantum computing (FTQC) is essential for achieving large-scale practical quantum computation. Implementing arbitrary FTQC requires the execution of a universal gate set on logical qubits, which is highly challenging. Particularly, in the superconducting system, two-qubit gates on surface code logical qubits have not been realized. Here, we experimentally implement a logical CNOT gate along with arbitrary single-qubit rotation gates on distance-2 surface codes using the superconducting quantum processor \textit{Wukong}, thereby demonstrating a universal logical gate set. In the experiment, we demonstrate the transversal CNOT gate on a two-dimensional topological processor based on a tailored encoding circuit, at the cost of removing the ancilla qubits required for stabilizer measurements. Furthermore, we fault-tolerantly prepare logical Bell states and observe a violation of CHSH inequality, confirming the entanglement between logical qubits. Using the logical CNOT gate and an ancilla logical state, arbitrary single-qubit rotation gates are realized through gate teleportation. All logical gates are characterized on a complete state set and their fidelities are evaluated by logical Pauli transfer matrices. The demonstration of a universal logical gate set and the entangled logical states highlights significant aspects of FTQC on superconducting quantum processors.
Forward citations
Cited by 3 Pith papers
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Hybrid physical/logical zero-noise extrapolation with limited logical executions
Mixed physical-logical datasets for zero-noise extrapolation reduce estimator variance and physical runtime by orders of magnitude compared to pure logical or pure physical strategies when error correction suppresses ...
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Hybrid physical/logical zero-noise extrapolation with limited logical executions
Mixing a single low-noise logical circuit with several physical folded circuits in ZNE cuts the runtime needed for fixed estimator variance by orders of magnitude when the logical error-suppression factor γ≲0.1.
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Hybrid physical/logical zero-noise extrapolation with limited logical executions
Hybrid physical/logical zero-noise extrapolation can cut runtime when logical error is much smaller than physical error under a calibrated linear noise model.
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