Pith. sign in

REVIEW 3 cited by

Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2405.09035 v3 pith:FLY3YXJE submitted 2024-05-15 quant-ph

Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor

classification quant-ph
keywords logicalgatequantumgatesqubitssuperconductinguniversalarbitrary
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
0 comments
Share X Bluesky LinkedIn Reddit HN
read the original abstract

Fault-tolerant quantum computing (FTQC) is essential for achieving large-scale practical quantum computation. Implementing arbitrary FTQC requires the execution of a universal gate set on logical qubits, which is highly challenging. Particularly, in the superconducting system, two-qubit gates on surface code logical qubits have not been realized. Here, we experimentally implement a logical CNOT gate along with arbitrary single-qubit rotation gates on distance-2 surface codes using the superconducting quantum processor \textit{Wukong}, thereby demonstrating a universal logical gate set. In the experiment, we demonstrate the transversal CNOT gate on a two-dimensional topological processor based on a tailored encoding circuit, at the cost of removing the ancilla qubits required for stabilizer measurements. Furthermore, we fault-tolerantly prepare logical Bell states and observe a violation of CHSH inequality, confirming the entanglement between logical qubits. Using the logical CNOT gate and an ancilla logical state, arbitrary single-qubit rotation gates are realized through gate teleportation. All logical gates are characterized on a complete state set and their fidelities are evaluated by logical Pauli transfer matrices. The demonstration of a universal logical gate set and the entangled logical states highlights significant aspects of FTQC on superconducting quantum processors.

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Hybrid physical/logical zero-noise extrapolation with limited logical executions

    quant-ph 2026-04 conditional novelty 6.0

    Mixed physical-logical datasets for zero-noise extrapolation reduce estimator variance and physical runtime by orders of magnitude compared to pure logical or pure physical strategies when error correction suppresses ...

  2. Hybrid physical/logical zero-noise extrapolation with limited logical executions

    quant-ph 2026-04 conditional novelty 6.0

    Mixing a single low-noise logical circuit with several physical folded circuits in ZNE cuts the runtime needed for fixed estimator variance by orders of magnitude when the logical error-suppression factor γ≲0.1.

  3. Hybrid physical/logical zero-noise extrapolation with limited logical executions

    quant-ph 2026-04 unverdicted novelty 5.5

    Hybrid physical/logical zero-noise extrapolation can cut runtime when logical error is much smaller than physical error under a calibrated linear noise model.