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REVIEW 3 major objections 27 references

ECG-LDC: A Hardware-Efficient Low-Dimensional Computing Framework for ECG Arrhythmia Classification

T0 review · 3 major / 0 minor · reviewed 2026-07-14 · grok-4.5

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Pith's one-line read ECG-LDC classifies five arrhythmia types at 97.18% accuracy with a 3.86 kB memory footprint using only XOR/XNOR operations and zero DSP blocks.

desk verdict Clean dual-encoder LDC + zero-DSP FPGA co-design for five-class ECG; the 97% number is real under a leaky beat split, so treat wearable transfer claims as provisional. read the letter →

arxiv 2607.09680 v1 pith:FYLZBYYA submitted 2026-06-13 eess.SP cs.AIcs.LG

Anh Tran , Khanh Tran , Cuong Do This is my paper · ORCID
classification eess.SPcs.AIcs.LG
keywords TinyMLedgecomputingFPGAhardwareaccelerationarrhythmiaclassificationwearabledevicesLow-DimensionalECG
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Wearable cardiac monitors need accurate arrhythmia detectors that fit inside tiny power and memory budgets. Deep networks reach high accuracy but demand millions of parameters and multiply-accumulate units that low-cost edge chips cannot afford. This paper adapts Low-Dimensional Computing (LDC) into a dual-encoder design that separately encodes the shape of each heartbeat and the timing between beats, then classifies with simple binary XOR/XNOR operations. The resulting model occupies only 3.86 kB, runs on an inexpensive FPGA with no DSP blocks, and still reaches 97.18% five-class accuracy on the standard MIT-BIH arrhythmia database. The practical payoff is a classifier small and fast enough for continuous real-time monitoring on resource-constrained wearables while remaining competitive with far larger TinyML baselines.

What carries the argument

Dual-encoder LDC: dedicated value and feature codebooks for morphology and RR-interval features that are bound by element-wise multiplication (XOR on hardware), bundled by accumulation and sign, concatenated, and matched to class hypervectors by Hamming distance.

What would settle it

Retrain and re-evaluate the identical ECG-LDC configuration under a strict inter-patient (leave-subjects-out) protocol on MIT-BIH and measure whether five-class accuracy remains near 97% with the same 3.86 kB footprint.

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Extended reading notes

Core claim

A dual-encoder Low-Dimensional Computing architecture that independently binds morphological waveform features and RR-interval temporal features into bipolar hypervectors, then classifies by Hamming distance, achieves 97.18% five-class AAMI accuracy at 3.86 kB total memory and zero DSP utilization on FPGA, outperforming prior five-class FPGA designs in both accuracy and logic cost.

Load-bearing premise

The accuracy numbers rest on a random beat-level train/test split of MIT-BIH rather than a patient-independent split, so patterns from the same person can leak into both sets.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 0 minor

Summary. The paper proposes ECG-LDC, a hardware–software co-design that adapts Low-Dimensional Computing to five-class AAMI arrhythmia classification on MIT-BIH. A dual-encoder design uses separate value/feature codebooks for morphological windows (Nm=61) and RR-interval features (Nr=5), binds and bundles them into a concatenated bipolar embedding, and classifies by Hamming distance to a class codebook. Training uses STE bipolarization with BN; inference is realized with binary XOR/XNOR-popcount on a Pynq-Z2 accelerator (binding/bundling, threshold binarization, classification FSM). Reported results are 97.18% accuracy at 3.86 kB memory, an ablation of feature/codebook choices, a memory–accuracy sweep, and post-implementation FPGA metrics (8255 LUTs, 0 DSP, ~4.2 ms end-to-end latency, 1.71 W full system). The authors claim a favorable accuracy–memory trade-off versus TinyML baselines and the best accuracy among listed five-class FPGA designs with lower LUT use and zero DSP.

Significance. If the accuracy and efficiency numbers hold under a deployment-relevant protocol, the work is a useful contribution to TinyML ECG: it shows that LDC-style binary hypervector models can reach competitive five-class accuracy with kilobyte-scale memory and a DSP-free FPGA datapath, which is practically relevant for low-cost wearables. Strengths include a clear dual-encoder ablation (Table IV), an explicit accuracy–memory design sweep (Fig. 5), a concrete SystemVerilog/Pynq-Z2 realization with resource/power/latency numbers (Tables V–VI), and honest comparison footnotes (e.g., Greco latency). The hardware co-design and complexity analysis (Eqs. 15–20) are more than a pure software TinyML paper and would interest the edge biomedical signal-processing community.

major comments (3)
  1. Section IV-A states that MIT-BIH is randomly split 70/30 at the beat level. With only 47 subjects, consecutive beats from the same patient share morphology and RR statistics, so this protocol admits same-patient leakage. The abstract, introduction, and conclusion frame suitability for real-time wearable deployment on unseen users; that claim requires inter-subject evaluation (AAMI DS1/DS2, patient-wise hold-out, or leave-one-patient-out). Please report accuracy/macro-F1 (and ideally ROC/PR) under at least one patient-independent protocol, or substantially qualify the wearable-generalization claim and restate 97.18% as an intra-dataset upper bound. Without this, the central accuracy number does not support the deployment conclusion even if hardware metrics remain valid.
  2. Table III and the abstract compare ECG-LDC to TinyML and FPGA baselines, but Section IV-A does not establish that those baselines used the same split (or patient-independent splits). If competitors used inter-patient protocols while ECG-LDC used random beat splits—or vice versa—the accuracy ranking is not commensurate. Please document each baseline’s train/test protocol (or re-evaluate under a common protocol) so that the “highest accuracy among five-class FPGA designs” and “~1.8% below SOTA TinyML” statements rest on aligned evaluation.
  3. Table V reports full-system dynamic power of 1571 mW (1.71 W in Table VI) while the ECG-LDC core is only 34 mW dynamic. Wearable suitability is repeatedly claimed, yet 1.71 W is dominated by the PS/AXI stack on Pynq-Z2 and is not a wearable power budget. Please separate core vs. full-system power clearly in the abstract/conclusion, state what fraction is attributable to the LDC datapath, and either (i) provide a duty-cycled or MCU/ASIC power estimate, or (ii) limit the wearable claim to memory/LUT/DSP efficiency of the core rather than end-to-end board power.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: empirical accuracy, memory, and FPGA metrics are measured against external data and tools, not forced by construction or self-citation.

full rationale

ECG-LDC is a hardware-software co-design that adapts the existing LDC paradigm (external citations [5],[10]) with a dual-encoder for morphological and RR features. Encoding (Eqs. 1–3, 11–12), quantization (Eq. 10), BN-threshold reduction (Eqs. 13–14), and complexity (Eqs. 15–20) are definitional of the method but do not make the reported 97.18% accuracy, 3.86 kB footprint, or FPGA numbers (Tables V–VI) true by construction. Accuracy is obtained by training on a 70% random split of MIT-BIH and evaluating the held-out 30% (Section IV-A, Table II); hyperparameters are selected via an explicit accuracy–memory sweep (Fig. 5) and then frozen. Hardware results come from Vivado post-implementation reports on Pynq-Z2 and are compared to independent published baselines. Ablations (Table IV) and comparisons (Tables III, VI) are likewise empirical. There is no self-definitional loop, no fitted parameter renamed as a prediction, no load-bearing self-citation of an unverified uniqueness claim, and no renaming of a known identity. The random beat-level split is a methodological limitation for wearable generalization claims, but that is an external-validity issue, not circularity of the derivation chain.

Assumptions & free parameters 6 free parameters · 6 assumptions · 2 invented entities

The central accuracy and hardware claims rest on the LDC encoding/classification model from prior literature, standard ECG preprocessing and AAMI labeling choices, a set of hand-chosen hypervector and quantization sizes selected via a constrained sweep, and the dual-encoder architecture introduced here. No new physical entity is postulated; the invented piece is the dual-codebook ECG-LDC system itself. Free parameters are architectural sizes and training knobs that fix the reported operating point.

free parameters (6)
  • df,m = df,r (feature hypervector size) = 256
    Swept over {64,128,256,512,1024}; selected 256 to hit the reported 97.18% / 3.86 kB point (Fig. 5, Table I).
  • dv,m = dv,r (value hypervector size) = 16
    Swept over {16,32,64}; selected 16 as the memory-efficient operating point (Fig. 5, Table I).
  • Nm morphology window length = 61
    Fixed at 61 samples centered on R-peak after 250 Hz resampling; chosen design choice that defines the morphological input (Section III-A, Table I).
  • input quantization bit-width b = 8
    Linear quantization to 8-bit integers with xmin/xmax from training data (Eq. 10); fixes value-codebook rows 2^b.
  • packed word width / unroll factor P = 64
    Hardware parallelism parameter set to 64; affects cycle latency and LUT cost (Table I, Eq. 20).
  • training hyperparameters (LR, weight decay, epochs, batch, dropout/BN) = LR=1e-3, 100 epochs, batch=128
    Adam 1e-3, weight decay 1e-4, 100 epochs, batch 128, SiLU+dropout value maps and BN before bipolarization; determine the learned codebooks that produce reported accuracy.
assumptions (6)
  • domain assumption LDC binding-bundling with bipolar codebooks and Hamming nearest-class decision is a valid classifier for discrete multi-feature inputs (Eqs. 1–3).
    Taken from Duan et al. LDC framework (Section II-B); not re-derived here.
  • domain assumption AAMI mapping of MIT-BIH annotations into five classes N/S/V/F/Q is the evaluation target.
    Stated in Section IV-A as standard practice; defines what 'accuracy' means.
  • domain assumption Pan–Tompkins R-peak detection plus fixed morphology window and engineered RR features sufficiently represent intra- and inter-beat dynamics for classification.
    Section III-A preprocessing pipeline; errors in peak detection or feature design would flow into all results.
  • domain assumption Straight-through estimator and post-training fixed BN thresholds preserve enough fidelity that trained floating codebooks match binary hardware inference.
    Eqs. 4–7 and 12–14; train/deploy gap is assumed small without separate train-vs-hardware accuracy audit.
  • ad hoc to paper Random 70/30 beat split yields a meaningful estimate of generalization for wearable use.
    Section IV-A; not patient-independent, yet used as the sole reported test protocol for the headline accuracy.
  • standard math Standard arithmetic and Boolean identities for XOR/XNOR-popcount realizing bipolar multiply and Hamming similarity.
    Section II-B and III-C hardware mapping.
invented entities (2)
  • ECG-LDC dual-encoder architecture (separate morph and RR value/feature codebooks, concatenated embedding, class codebook)
    purpose: Encode morphological and RR features in dedicated spaces to reduce interference and improve five-class ECG accuracy under LDC constraints.
    Introduced in Section III-B and Fig. 2; ablation Table IV is the internal evidence. No independent clinical validation outside this paper.
  • ECG-LDC FPGA accelerator (binding/bundling, threshold binarization, XNOR-popcount classification FSM on Pynq-Z2)
    purpose: Demonstrate real-time, zero-DSP, low-memory inference matching the trained model.
    Section III-C and Fig. 3; performance is measured on one board/toolchain configuration only.

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Cite this review

Pith. "Pith review of ECG-LDC: A Hardware-Efficient Low-Dimensional Computing Framework for ECG Arrhythmia Classification." pith.science (2026). https://pith.science/paper/FYLZBYYA

@misc{pith2026260709680,
  author       = {Pith},
  title        = {Pith review of: ECG-LDC: A Hardware-Efficient Low-Dimensional Computing Framework for ECG Arrhythmia Classification},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FYLZBYYA}},
  note         = {Machine review of arXiv:2607.09680}
}
abstract

Continuous cardiac monitoring in wearable devices demands classifiers that are simultaneously accurate, energy-efficient, and deployable on resource-constrained hardware. While deep neural network approaches have demonstrated high classification accuracy for electrocardiogram (ECG) arrhythmia detection, their substantial parameter counts and reliance on multiply-accumulate-intensive operations make them impractical for low-cost edge platforms. In this work, we propose ECG-LDC, a hardware-software co-design framework that adapts Low-Dimensional Computing (LDC) for real-time ECG arrhythmia classification. ECG-LDC employs a dual-encoder architecture with dedicated value and feature codebooks to independently encode morphological waveform features and RR-interval temporal features, enabling effective capture of both intra-beat and inter-beat cardiac dynamics. The framework encompasses data preprocessing, model training, and a hardware accelerator architecture prototyped on the Pynq-Z2 platform. Implemented using binary representations and XOR/XNOR-based operations, ECG-LDC achieves $97.18\%$ accuracy with a memory footprint of only $3.86\ \text{kB}$. ECG-LDC sacrifices approximately $1.8\%$ accuracy versus SOTA TinyML classifiers but achieves $11$~$ 570\times$ reduction in memory usage; among FPGA-based five-class arrhythmia classifiers, it delivers the highest accuracy with up to $2.4\times$ fewer LUTs and zero DSP block utilization, affirming its suitability for real-time arrhythmia detection on resource-constrained wearable platforms.

Figures

Figures reproduced from arXiv: 2607.09680 by the authors.

Figure 1
Figure 1. Structure of an ECG beat. ded medical platforms. The primary contributions of this work are summarized as follows: 1) We propose a dual-encoder LDC architecture that em￾ploys distinct value and feature hypervectors to indepen￾dently encode morphological and RR-interval features of ECG signals. 2) We present a hardware architecture for ECG-LDC, pro￾totyped on the Pynq-Z2 FPGA platform, demonstrating its feasibility f… view at source ↗
Figure 2
Figure 2. ECG-LDC architecture overview. where the Hamming distance is defined as Hamm(e1, e2) = 1 df X df j=1 I[(e1)j ̸= (e2)j ] . (3) A key strength of LDC is its ability to learn the codebooks V, F, and C through gradient-based optimization. To enable end-to-end training, the discrete codebooks are parameterized as: V[xi ] = signSTE fθ˜(xi)  , (4) F = signSTE F˜  , (5) C = signSTE C˜  , (6) where fθ˜(·) denotes a trai… view at source ↗
Figure 3
Figure 3. Hardware architecture of the ECG-LDC accelerator. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Per-class ROC and PR curves. TABLE III: Comparison with lightweight SOTA arrhythmia classifiers on the MIT-BIH Arrhythmia Database. Work Year Weights Acc Model Size Memory (%) (kB) (kB) Xu et al. [11] 2020 — 95.90 — — Scrugli et al. [12] 2022 8-bit 96.98 — — Wang et al…
Figure 5
Figure 5. Figure 5: Accuracy–memory tradeoff of ECG-LDC TABLE V: Resource utilization and performance summary. Metric AXI Subsystem ECG-LDC Full System LUT 2589 5652 8255 FF 3473 4790 8296 BRAM 2 4 6 DSP 0 0 0 Static Power (mW) — 105 138 Dynamic Power (mW) 10 34 1571 Latency (µs) — 23.9 4…

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Works this paper leans on

27 extracted references · 1 canonical work pages

  1. [1]

    Global, regional, and national burden of cardiovascular diseases and risk factors in 204 countries and territories, 1990-2023,

    Global Burden of Cardiovascular Diseases and Risks 2023 Collaborators, “Global, regional, and national burden of cardiovascular diseases and risk factors in 204 countries and territories, 1990-2023,” JACC, vol. 86, no. 22, pp. 2167–2243, 2025. [Online]. Available: https://www.jacc.org/doi/abs/10.1016/j.jacc.2025.08.015

    work page doi:10.1016/j.jacc.2025.08.015 2023

  2. [2]

    Spec: A system for patient specific ecg beat classification using deep residual network,

    J. P. Allam, S. Samantray, and S. Ari, “Spec: A system for patient specific ecg beat classification using deep residual network,” Biocybernetics and Biomedical Engineering, vol. 40, no. 4, pp. 1446–1457, 2020. [Online]. Available: https://www.sciencedirect.com/ science/article/pii/S0208521620300942

    2020

  3. [3]

    Cat-net: Convolution, attention, and transformer based network for single- lead ecg arrhythmia classification,

    M. R. Islam, M. Qaraqe, K. Qaraqe, and E. Serpedin, “Cat-net: Convolution, attention, and transformer based network for single- lead ecg arrhythmia classification,”Biomedical Signal Processing and Control, vol. 93, p. 106211, 2024. [Online]. Available: https: //www.sciencedirect.com/science/article/pii/S1746809424002696

    2024

  4. [4]

    The impact of the mit-bih arrhythmia database,

    G. Moody and R. Mark, “The impact of the mit-bih arrhythmia database,”IEEE Engineering in Medicine and Biology Magazine, vol. 20, no. 3, pp. 45–50, 2001

    2001

  5. [5]

    A brain-inspired low-dimensional computing classifier for inference on tiny devices,

    S. Duan, X. Xu, and S. Ren, “A brain-inspired low-dimensional computing classifier for inference on tiny devices,” 2022. [Online]. Available: https://arxiv.org/abs/2203.04894

    arXiv 2022

  6. [6]

    Aha/accf/hrs recommendations for the standardization and interpretation of the electrocardiogram,

    B. Surawicz, R. Childers, B. J. Deal, and L. S. Gettes, “Aha/accf/hrs recommendations for the standardization and interpretation of the electrocardiogram,”Circulation, vol. 119, no. 10, pp. e235–e240,

  7. [7]

    Available: https://www.ahajournals.org/doi/abs/10.1161/ CIRCULATIONAHA.108.191095

    [Online]. Available: https://www.ahajournals.org/doi/abs/10.1161/ CIRCULATIONAHA.108.191095

  8. [8]

    Sinus bradycardia,

    Y . Hafeez and S. A. Grossman, “Sinus bradycardia,” In: StatPearls [Inter- net]. StatPearls Publishing, Treasure Island, FL, 2023, updated 2023 Aug

    2023

Show all 27 references
  1. [9]

    Available from: https://www.ncbi.nlm.nih.gov/books/NBK493201/

  2. [10]

    A real-time qrs detection algorithm,

    J. Pan and W. J. Tompkins, “A real-time qrs detection algorithm,”IEEE Transactions on Biomedical Engineering, vol. BME-32, no. 3, pp. 230– 236, 1985

    1985

  3. [11]

    Dense neural network based arrhythmia classification on low-cost and low-compute micro-controller,

    M. A. O. Zishan, H. Shihab, S. S. Islam, M. A. Riya, G. M. Rahman, and J. Noor, “Dense neural network based arrhythmia classification on low-cost and low-compute micro-controller,”Expert Systems with Applications, vol. 239, p. 122560, 2024. [Online]. Available: https://www.sci...

    2024

  4. [12]

    Towards vector optimization on low-dimensional vector symbolic architecture,

    S. Duan, Y . Liu, G. Liu, R. R. Kompella, S. Ren, and X. Xu, “Towards vector optimization on low-dimensional vector symbolic architecture,”

  5. [13]

    Available: https://arxiv.org/abs/2502.14075

    [Online]. Available: https://arxiv.org/abs/2502.14075

    arXiv

  6. [14]

    Interpretation of electrocardiogram (ecg) rhythm by combined cnn and bilstm,

    X. Xu, S. Jeong, and J. Li, “Interpretation of electrocardiogram (ecg) rhythm by combined cnn and bilstm,”IEEE Access, vol. 8, pp. 125 380– 125 388, 2020

    2020

  7. [15]

    An adaptive cognitive sensor node for ecg monitoring in the internet of medical things,

    M. A. Scrugli, D. Loi, L. Raffo, and P. Meloni, “An adaptive cognitive sensor node for ecg monitoring in the internet of medical things,”IEEE Access, vol. 10, pp. 1688–1705, 2022

    2022

  8. [16]

    Arrhythmia classifier using binarized convolutional neural network for resource- constrained devices,

    A. Wang, W. Xu, H. Sun, N. Pu, Z. Liu, and H. Liu, “Arrhythmia classifier using binarized convolutional neural network for resource- constrained devices,” in2022 4th International Conference on Com- munications, Information System and Computer Engineering (CISCE), 2022, pp. 213–220

    2022

  9. [17]

    Classifying cardiac arrhythmia from ecg signal using 1d cnn deep learning model,

    A. A. Ahmed, W. Ali, T. A. A. Abdullah, and S. J. Malebary, “Classifying cardiac arrhythmia from ecg signal using 1d cnn deep learning model,”Mathematics, vol. 11, no. 3, 2023. [Online]. Available: https://www.mdpi.com/2227-7390/11/3/562

    2023

  10. [18]

    Arrhythmia classifier based on ultra-lightweight binary neural network,

    N. Pu, Z. Wu, A. Wang, H. Sun, Z. Liu, and H. Liu, “Arrhythmia classifier based on ultra-lightweight binary neural network,” in2023 15th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), 2023, pp. 1–7

    2023

  11. [19]

    Fusiongcnn: An iot-based novel spatiotemporal graph convolutional network for ecg arrhythmia detection,

    S. Iqbal, X. Zhong, M. Alhussein, Z. Wu, K. Aurangzeb, W. Liu, and Y . Zhang, “Fusiongcnn: An iot-based novel spatiotemporal graph convolutional network for ecg arrhythmia detection,”IEEE Internet of Things Journal, vol. 12, no. 22, pp. 46 038–46 050, 2025

    2025

  12. [20]

    A tiny transformer for low-power arrhythmia classification on micro- controllers,

    P. Busia, M. A. Scrugli, V . J.-B. Jung, L. Benini, and P. Meloni, “A tiny transformer for low-power arrhythmia classification on micro- controllers,”IEEE Transactions on Biomedical Circuits and Systems, vol. 19, no. 1, pp. 142–152, 2025. PREPRINT, 2026 10

    2025

  13. [21]

    Multi-feature fusion and com- pressed bi-lstm for memory-efficient heartbeat classification on wearable devices,

    R. Nikandish, J. He, and B. Haghi, “Multi-feature fusion and com- pressed bi-lstm for memory-efficient heartbeat classification on wearable devices,”IEEE Journal of Biomedical and Health Informatics, pp. 1–10, 2026

    2026

  14. [22]

    Fpga-based system for artificial neural network arrhythmia classification,

    H. Zairi, M. K. Talha, K. Meddah, and S. O. Slimane, “Fpga-based system for artificial neural network arrhythmia classification,”Neural Computing and Applications, vol. 32, no. 8, pp. 4105–4120, 2020

    2020

  15. [23]

    A computational architecture for inference of a quantized-cnn for detecting atrial fibrillation,

    A. F. Jaramillo-Rueda, L. Y . Vargas-Pacheco, and C. A. Fajardo, “A computational architecture for inference of a quantized-cnn for detecting atrial fibrillation,”Ingenier ´ıa y Ciencia, vol. 16, no. 32, pp. 135–149, Nov. 2020

    2020

  16. [24]

    An atrial fibrillation detection system based on machine learning algorithm with mix-domain features and hardware acceleration,

    C. Chen, C. Ma, Y . Xing, Z. Li, H. Gao, X. Zhang, C. Yang, C. Liu, and J. Li, “An atrial fibrillation detection system based on machine learning algorithm with mix-domain features and hardware acceleration,” in 2021 43rd Annual International Conference of the IEEE Engineering...

    2021

  17. [25]

    Hardware implementation of 1d- cnn architecture for ecg arrhythmia classification,

    V . Rawal, P. Prajapati, and A. Darji, “Hardware implementation of 1d- cnn architecture for ecg arrhythmia classification,”Biomedical Signal Processing and Control, vol. 85, p. 104865, 2023. [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1746809423002987

    2023

  18. [26]

    Fpga-based 1d-cnn accelerator for real-time arrhythmia classification,

    Z. Liu, X. Ling, Y . Zhu, and N. Wang, “Fpga-based 1d-cnn accelerator for real-time arrhythmia classification,”Journal of Real-Time Image Processing, vol. 22, no. 2, p. 66, 2025

    2025

  19. [27]

    Fast and low cost fpga-based architecture for arrhythmia detection with cnn,

    L. Greco, F. Moscato, P. Ritrovato, and M. Vento, “Fast and low cost fpga-based architecture for arrhythmia detection with cnn,” Internet of Things, vol. 33, p. 101705, 2025. [Online]. Available: https://www.sciencedirect.com/science/article/pii/S2542660525002197

    2025

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