Large-scale characterization of Single-Hole Transistors in 22-nm FDSOI CMOS Technology

Alberto Gomez-Saiz; David F. Wise; Grayson M. Noah; John J. L. Morton; Mark A. I. Johnson; M. Fernando Gonzalez-Zalba; Thomas H. Swift; Virginia N. Ciriano-Tejel

REVIEW 3 major objections 5 minor 1 cited by

Large-scale characterization of Single-Hole Transistors in 22-nm FDSOI CMOS Technology

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read A commercial 22-nm CMOS process can host 384 hole-based quantum dots, each in its own transistor, with on-chip control electronics operating at deep cryogenic temperatures.

desk verdict A real 384-device p-type FDSOI quantum-dot dataset, but the headline yield percentages need sample sizes and a p-type check of the classifier before they carry weight. read the letter →

arxiv 2507.21306 v1 pith:HE5RUSPS submitted 2025-07-28 cond-mat.mes-hall

Thomas H. Swift , Alberto Gomez-Saiz , Virginia N. Ciriano-Tejel , David F. Wise , Grayson M. Noah , John J. L. Morton , M. Fernando Gonzalez-Zalba , Mark A. I. Johnson This is my paper

classification cond-mat.mes-hall PACS 85.35.Gv

keywords quantumdotsholespinqubitssingle-holetransistorsFDSOICMOScryogenicelectronicschargenoisemachinelearningclassificationCoulombdiamonds

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper attempts to show that a commercial 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS process can be turned into a platform for hole-based spin qubits by embedding hundreds of quantum dots in ordinary transistors. The authors fabricate a 'farm' of 384 p-type single-hole transistors with on-chip multiplexed digital and analog electronics, run it at deep cryogenic temperatures, and use a machine-learning classifier to sort Coulomb-diamond maps into 'QD' and 'No QD'. They find that the shortest available gate length, 28 nm, forms well-defined quantum dots about 30% of the time, while 40 nm gates succeed less than 10% of the time, and they report a median charge noise of roughly 6.5 micro-electron-volts per root hertz with a 1/f-like spectrum. If correct, this establishes both a scalability path—hundreds of quantum dots addressable with few lines—and a specific process target (gates at or below 28 nm) for future work.

What carries the argument

The argument rests on three linked elements. The 'farm' is a multiplexed array of 384 p-type transistors in the 22-nm FDSOI process, each with a front gate length from 28 to 80 nm, and on-chip digital and analog electronics that allow one device to be addressed at a time with few lines—this is what makes large-scale characterization possible. The 'Diamondsky' analysis package, a convolutional-neural-network classifier trained in earlier work on expert-labeled maps, sorts Coulomb-diamond maps into 'QD' and 'No QD', turning raw transport data into yield statistics. The charge-noise arm uses an LC resonator to track a Coulomb peak position over 100 seconds, then fits the power spectral density to $S(f) = S_0 / f^\gamma$ using Welch's method, producing the noise numbers that quantify the device environment.

What would settle it

Re-analyze the same farm's Coulomb-diamond maps with an expert human label set (or with a classifier retrained on p-type data) and compare the fraction labeled 'QD'. If the disagreement changes the reported ordering—30% at 28 nm versus under 10% at 40 nm—then the yield claim is an artifact of classifier transfer rather than a property of the devices.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central discovery is that p-type quantum dots can be formed in 22-nm FDSOI transistors at scale: 384 devices, each a single-hole transistor, are measured in one cool-down through on-chip multiplexing, and their behavior is classified automatically. The key quantitative results are a strong gate-length dependence of dot yield—about 30% for PCL = 28 nm versus below 10% for PCL = 40 nm—and charge-noise parameters with median S0 of 6.5 micro-electron-volts per root hertz and gamma near 1.25, close to 1/f. The paper also reports classical cryogenic transistor behavior consistent with short-channel effects: threshold voltage magnitude decreases and drain-induced barrier lowering increases as gate length shrinks, while the spread in threshold voltage grows, and subthreshold swing averages about 16 mV/dec at an estimated chip temperature of roughly 600 mK. Together these results are taken as evidence that monolithic quantum-classical integration in a manufacturing process is realistic, with device dimensions serving as the dominant tuning knob.

Load-bearing premise

The load-bearing premise is that the convolutional-neural-network classifier trained on n-type Coulomb maps in earlier work also correctly identifies p-type Coulomb maps, because the paper uses it without retraining or p-type-specific validation; if that transfer fails, the reported 30% and <10% yield figures would not be reliable.

Editorial extensions

If this is right

If the 28-nm result is representative, future 22-nm FDSOI fabrication runs should concentrate on gate lengths at or below 28 nm to maximize the number of usable quantum dots per chip.
A farm of 384 p-type dots with on-chip multiplexed access shows that hundreds of quantum devices can be addressed with a small number of cryogenic lines, directly addressing the I/O scaling bottleneck for spin qubits.
The measured median charge noise near 6.5 micro-electron-volts per root hertz at 1 Hz implies that charge noise, rather than device yield, may be the first limit on qubit coherence in these p-type devices, so noise reduction must accompany further process development.
The cryogenic classical parameters (threshold voltage, drain-induced barrier lowering, subthreshold swing) provide a rapid screening signature, and their observed short-channel trends mean device variability will grow as gates shrink toward the process minimum.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the yield ordering holds, the natural next step is to push below 28 nm or adjust the process at 28 nm to recover yield while controlling threshold-voltage variability, since the paper already shows variability grows at short gate lengths.
The median charge noise of 6.5 micro-electron-volts per root hertz is higher than values quoted for other platforms; this points to charge-noise reduction—through dielectric improvement or isotopic purification—as a prerequisite before these dots can act as qubits, a consequence the paper states qualitatively but does not translate into qubit-error rates.
A testable extension is to co-fabricate a second farm with gate lengths closely spaced around 28 nm (for example 24, 26, 28, 30 nm) to map the yield-versus-length curve and see whether the 30% figure is a plateau or a sharp maximum.
The same fast-readout plus classifier pipeline could be applied to n-type and p-type devices on the same chip to compare yield and charge-noise statistics between carrier types, separating process effects from hole-specific physics.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Read it. The genuinely new thing is the dataset: 384 p-type transistors in a commercial 22-nm FDSOI process, characterized at ~600 mK with on-chip multiplexing, plus deep-cryogenic classical transistor metrics (Vth, DIBL, SS) across the farm and charge-noise statistics. That is a useful contribution for people trying to scale hole spin qubits in CMOS. The spatial uniformity plot for Vth and the observation that DIBL rises while |Vth| falls for shorter PCL are sane and match short-channel physics. The qualitative dimension-yield trend — PCL=28 nm clearly better than PCL=40 nm — is probably real, and the recommendation to focus future runs on PCL <= 28 nm is reasonable given the caveat about variability.

Soft spots, in rough order of importance. First, the classifier transfer. Section III says the Diamondsky CNN trained on expert-labeled data in ref [10] was used for p-type devices, but there is no p-type validation subset, confusion matrix, or confidence audit. Hole dots have different lever arms, charging energies, and excited-state visibility, so the decision boundary could shift. Because the 30% vs <10% yield claim rests on this classifier, the missing validation genuinely weakens the quantitative conclusion. I would not call it fatal — the figures show examples that look like clear QDs vs noise, and the difference is large — but it needs to be addressed. Second, sample sizes. I could not find how many devices of each geometry were measured. The 30% and <10% are quoted without n or confidence intervals. Table I gives median S0 = 6.5 µeV/√Hz with IQR 17.5 and gamma 1.25, but no n; only two example traces are shown. This is fixable with a supplement table. Third, the abstract says '384 p-type quantum dots'; the body supports 384 fabricated p-type devices, with ~30% yielding good dots at the best geometry. That wording overstates the result.

The reader's take and the stress-test note land on the right issue. I don't think the concern is manufactured: it is a load-bearing missing validation, but it is also a common one in this area, and the underlying data look valuable enough that the paper deserves a serious referee rather than a desk reject. If the authors add per-geometry n, error bars, and at least a small p-type validation of the classifier, the central claims will probably hold. Who is this for: experimental groups working on CMOS spin qubits, cryo-CMOS, device variability, and anyone planning a large QD-farm run. I would bring it to our reading group and would probably cite it for the p-type FDSOI dataset. Recommendation: send to peer review, but flag the classifier validation and missing statistics as requirements for acceptance.

Referee Report

3 major / 5 minor

Summary. The paper reports cryogenic characterization of 384 p-type single-hole transistors fabricated in a commercial 22-nm FDSOI CMOS process and integrated in a multiplexed farm with on-chip electronics. The authors measure classical DC parameters (threshold voltage, DIBL, subthreshold swing) as a function of gate length, apply an automated CNN classifier (Diamondsky) from prior work to label Coulomb diamond maps as 'QD' or 'No QD', and report quantum dot yield versus device dimensions, with about 30% good dots at PCL=28 nm versus below 10% at PCL=40 nm. They also report charge noise from peak-tracking measurements, with median S0 around 6.5 micro-eV per root hertz and gamma around 1.25. The paper concludes that future fabrication runs should focus on PCL at or below 28 nm and that the results demonstrate a path to monolithic integration of quantum and classical electronics at scale.

Significance. If the findings are robust, the paper is a valuable scaling study: it shows that a commercial FDSOI process can host hundreds of hole-based quantum dot devices with integrated multiplexing at deep cryogenic temperatures, and it identifies a geometry-dependent yield trend that can inform future process runs. The use of automated machine-learning classification for high-throughput cryogenic characterization is a useful methodological contribution. However, the central yield result currently rests on an unvalidated transfer of a classifier from n-type to p-type devices, and the statistical basis for the headline percentages is incomplete. The abstract also overstates the number of demonstrated quantum dots. These issues need to be addressed before the quantitative claims can be fully accepted.

major comments (3)

[Section III, Fig. 3] The yield percentages in the bottom panels of Fig. 3 are generated by the 'Diamondsky' CNN from ref. [10], which was trained on n-type Coulomb diamond maps using domain-expert labels. The manuscript gives no evidence that the decision boundary transfers to p-type devices: there is no retraining on p-type data, no p-type validation subset with expert labels, no confusion matrix, and no confidence-score audit. Because hole and electron dots differ in charging energy, lever arm, and excited-state visibility, misclassification could systematically bias the central yield comparison (about 30% at PCL=28 nm versus below 10% at PCL=40 nm) and therefore the recommendation to focus future runs on PCL at or below 28 nm. Please provide p-type validation statistics, for example agreement, sensitivity, and specificity on an expert-labeled subset of p-type Coulomb maps, or explicitly re-present the yields as classifier outputs pending such validation.
[Abstract and Section III] The abstract states that the work demonstrates 'the monolithic integration of 384 p-type quantum dots', but the body reports a farm of 384 p-type transistors of which only a fraction are classified as quantum dots (about 30% for the best geometry). This overstates the number of demonstrated quantum dots and should be corrected, for example to '384 single-hole transistors' with the yield statistics reported in Section III. The phrase 'quantum dot yield' already makes clear that not all devices form dots, so the abstract should be consistent with that.
[Section III, Fig. 3 (bottom panels)] The yield percentages for each PCL and RX W combination are reported without sample sizes, error bars, or confidence intervals. The reader cannot determine how many devices underpin the 'about 30%' versus 'below 10%' comparison, whether the difference is statistically significant, or whether the yield varies across device instances within a cell. Reporting the number of devices per cell and confidence intervals for binomial proportions (e.g., Wilson intervals) is necessary to support the conclusion that PCL at or below 28 nm is the promising dimension for future runs. Without these, the headline yield comparison is not quantitatively established.

minor comments (5)

[Section IV, Table I] The number of devices used to compute the median S0 and IQR values is not stated; Fig. 4 shows only two devices, so it is unclear whether the table is based on two or many devices and whether the two example devices are representative. Please state the number of devices and their geometry.
[Fig. 4 caption] The caption reads 'two different device over 100 seconds'; this should be 'two different devices over 100 seconds'.
[Section II] The text says all measurements are taken at base temperature (about 20 mK) with on-chip power dissipation raising the sample temperature to around 600 mK; it should be clarified whether the DC transistor data in Fig. 1 were recorded at 20 mK or at 600 mK, since this affects the comparison of subthreshold swing with theory.
[Section III] The text states that the first-hole voltage V1h and the gate lever arm alpha are extracted, but the paper does not present these quantities or their statistics; either include the data or remove the claim from the description.
[Section II, Fig. 1] The box-and-whisker plots would benefit from a statement of the number of devices per gate length and the definition of outliers used in the whisker construction.

Circularity Check

0 steps flagged · score 1.0 of 10

No circular derivation found: yield, noise, and electrostatic parameters are measured outcomes, not assumptions; the Diamondsky classifier transfer is a validity concern, not a circular reduction.

full rationale

The paper's derivation chain is empirical rather than definitional. Classical parameters are extracted by defined procedures: Vth via a constant-current method in the linear regime, DIBL from Vth changes with source voltage, and SS from subthreshold slope. QD yield is obtained by applying the previously trained Diamondsky CNN to Coulomb diamond maps, and charge-noise parameters S0 and gamma are fitted to measured power spectral densities using Eq. (1). None of these quantities is defined in terms of the paper's conclusions, and no fitted parameter is renamed as a prediction. The only self-citation concern is that Diamondsky, developed in ref. [10] by overlapping authors, is applied to p-type devices without retraining or a p-type validation set; the reported '~30% good dots at PCL=28 nm' therefore depends on the transferability of an n-type-trained decision boundary. However, this is an external-validity and robustness limitation, not a circularity: the yield-vs-dimension trend is not encoded in the classifier's training labels, and the classifier's outputs on unseen p-type maps are empirical observations. Similarly, charge-noise medians are reported characteristics of fits, not assumed inputs. Under the stated circularity rules, this warrants only a minimal score.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The central claims rest on standard quantum dot physics, the operation of the LC resonator, and a prior neural network classifier. The main unverified assumption is the transfer of the Diamondsky classifier to p-type devices without validation. The fitted noise parameters S0 and gamma are outputs of the measurement, not free assumptions, but they are reported statistical quantities whose reliability depends on the number of measured devices.

free parameters (2)

S0 (power spectral density at 1 Hz) = median 6.5 µeV/√Hz, IQR 17.5
Fitted to each device's peak-position PSD using S(f) = S0/f^γ; reported as charge noise magnitude.
γ (noise exponent) = median 1.25, IQR 0.72
Fitted power-law exponent in the charge noise model; reported as frequency dependence.

assumptions (3)

domain assumption The formed single-hole transistor hosts a quantum dot whose Coulomb diamond edges are visible in the in-phase LC resonator response.
Section III assumes the observed features in gate-voltage/source-drain maps are QD Coulomb diamonds; this is the basis for the QD/No QD classification.
ad hoc to paper The Diamondsky CNN classifier, trained on expert-labeled data in prior work, produces correct labels when applied to p-type devices in this paper.
Section III uses the package without stating whether it was retrained or validated on p-type maps; the yield percentages inherit this assumption.
domain assumption The charge noise power spectral density follows S(f) = S0/f^γ over the measured frequency range.
Section IV fits this model to compute S0 and gamma; no goodness-of-fit or alternative models are reported.

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Cite this review

Pith. "Pith review of Large-scale characterization of Single-Hole Transistors in 22-nm FDSOI CMOS Technology." pith.science (2026). https://pith.science/paper/HE5RUSPS

@misc{pith2026250721306,
  author       = {Pith},
  title        = {Pith review of: Large-scale characterization of Single-Hole Transistors in 22-nm FDSOI CMOS Technology},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HE5RUSPS}},
  note         = {Machine review of arXiv:2507.21306}
}

read the original abstract

State-of-the-art quantum processors have recently grown to reach 100s of physical qubits. As the number of qubits continues to grow, new challenges associated with scaling arise, such as device variability reduction and integration with cryogenic electronics for I/O management. Spin qubits in silicon quantum dots provide a platform where these problems may be mitigated, having demonstrated high control and readout fidelities and compatibility with large-scale manufacturing techniques of the semiconductor industry. Here, we demonstrate the monolithic integration of 384 p-type quantum dots, each embedded in a silicon transistor, with on-chip digital and analog electronics, all operating at deep cryogenic temperatures. The chip is fabricated using 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. We extract key quantum dot parameters by fast readout and automated machine learning routines to determine the link between device dimensions and quantum dot yield, variability, and charge noise figures. Overall, our results demonstrate a path to monolithic integration of quantum and classical electronics at scale.

Figures

Figures reproduced from arXiv: 2507.21306 by the authors.

**Figure 4.** (a)-(b) In-phase signal (I) against time and gate voltage for two different device over 100 seconds (c)-(d) Power spectral density calculated from peak position data. To compare charge noise data between different devices and device types, the power spectral density is fitted to: S(f) ∝ S0 f γ , (1) where S0 is the power spectral density at f = 1 Hz and γ gives an indication of the frequency dependence of the charge… view at source ↗

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