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Three-dimensional surface codes: Transversal gates and fault-tolerant architectures

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arxiv 1801.04255 v2 pith:I65NYZ2O submitted 2018-01-12 quant-ph

Three-dimensional surface codes: Transversal gates and fault-tolerant architectures

classification quant-ph
keywords surfacecodescodequantumarchitecturescomputinggatestransversal
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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One of the leading quantum computing architectures is based on the two-dimensional (2D) surface code. This code has many advantageous properties such as a high error threshold and a planar layout of physical qubits where each physical qubit need only interact with its nearest neighbours. However, the transversal logical gates available in 2D surface codes are limited. This means that an additional (resource intensive) procedure known as magic state distillation is required to do universal quantum computing with 2D surface codes. Here, we examine three-dimensional (3D) surface codes in the context of quantum computation. We introduce a picture for visualizing 3D surface codes which is useful for analysing stacks of three 3D surface codes. We use this picture to prove that the $CZ$ and $CCZ$ gates are transversal in 3D surface codes. We also generalize the techniques of 2D surface code lattice surgery to 3D surface codes. We combine these results and propose two quantum computing architectures based on 3D surface codes. Magic state distillation is not required in either of our architectures. Finally, we show that a stack of three 3D surface codes can be transformed into a single 3D color code (another type of quantum error-correcting code) using code concatenation.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Genuine Multipartite Entanglement between Logical Qubits via Cross-Code Lattice Surgery

    quant-ph 2026-07 accept novelty 7.5

    Cross-code lattice surgery between surface and 3D colour codes yields certified logical GHZ and |CCZ> GME plus arbitrary logical rotations on a trapped-ion processor.