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LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
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Driven by Moore's Law, the complexity and scale of modern chip design are increasing rapidly. Electronic Design Automation (EDA) has been widely applied to address the challenges encountered in the full chip design process. However, the evolution of very large-scale integrated circuits has made chip design time-consuming and resource-intensive, requiring substantial prior expert knowledge. Additionally, intermediate human control activities are crucial for seeking optimal solutions. In system design stage, circuits are usually represented with Hardware Description Language (HDL) as a textual format. Recently, Large Language Models (LLMs) have demonstrated their capability in context understanding, logic reasoning and answer generation. Since circuit can be represented with HDL in a textual format, it is reasonable to question whether LLMs can be leveraged in the EDA field to achieve fully automated chip design and generate circuits with improved power, performance, and area (PPA). In this paper, we present a systematic study on the application of LLMs in the EDA field, categorizing it into the following cases: 1) assistant chatbot, 2) HDL and script generation, and 3) HDL verification and analysis. Additionally, we highlight the future research direction, focusing on applying LLMs in logic synthesis, physical design, multi-modal feature extraction and alignment of circuits. We collect relevant papers up-to-date in this field via the following link: https://github.com/Thinklab-SJTU/Awesome-LLM4EDA.
Forward citations
Cited by 6 Pith papers
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When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering
LLM answers to HDL questions are often redundant and verbose; a task-aware multi-agent framework cuts redundancy by 37% and padding by 31% while raising judge-based quality scores.
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MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
MCP4EDA is an MCP server that lets LLMs orchestrate the open-source RTL-to-GDSII flow and iteratively refine synthesis scripts from post-layout metrics.
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VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs
A multi-role LLM prompting framework with PPA-aware in-context learning reports 25/29 functional correctness on RTLLM and up to 88% power, 76% area, and 73% timing gains over its own baseline.
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EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
EvoVerilog uses multiobjective evolutionary search with LLMs to generate Verilog code, reporting higher pass@10 than prior methods on VerilogEval-Machine and VerilogEval-Human.
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