Real-Time Analysis of Unstructured Data with Machine Learning on Heterogeneous Architectures

Fotis I. Giasemis

REVIEW 3 major objections 4 minor 295 references

Real-Time Analysis of Unstructured Data with Machine Learning on Heterogeneous Architectures

T0 review · 3 major / 4 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read A graph-neural-network track finder reconstructs charged particles in the LHCb vertex detector with physics performance comparable to the production algorithm while running inside the first-level GPU trigger.

desk verdict A useful engineering thesis with a real GNN-in-trigger result, but the abstract oversells the FPGA work and the headline physics-parity claim belongs to the prototype, not the deployed C++/CUDA version. read the letter →

arxiv 2508.07423 v3 pith:JGHTBH44 submitted 2025-08-10 physics.data-an cs.AIcs.DCcs.LGhep-ex

Fotis I. Giasemis This is my paper

classification physics.data-ancs.AIcs.DCcs.LGhep-ex

keywords graphneuralnetworktrackreconstructionLHCbVELOreal-timetriggerGPUcomputingFPGAquantizationheterogeneousarchitectures

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper's central claim is that a graph-neural-network track finder, ETX4VELO, can reconstruct charged-particle tracks in the upgraded LHCb vertex detector with physics performance comparable to the production 'Search by triplet' algorithm, while running entirely on GPUs inside the first-level trigger Allen. If true, it shows that machine-learned track reconstruction can be competitive in the most demanding real-time filtering environment in particle physics, rather than being strictly a costlier alternative. The paper also claims that an FPGA implementation of the pipeline's embedding MLP can deliver competitive inference throughput at lower energy per event than a GPU, pointing toward heterogeneous trigger systems. These results are established on simulated LHCb collisions and evaluated with the MonteTracko library; the FPGA throughput figures come from synthesis estimates rather than board measurements.

What carries the argument

The central object carrying the claim is the ETX4VELO pipeline, a graph-neural-network track finder. Its functional blocks are: an embedding MLP that turns VELO hit coordinates into a low-dimensional embedding; a k-nearest-neighbour graph built in that embedding space; a message-passing GNN with node and edge networks that scores whether each edge connects hits from the same particle; and a triplet classifier followed by weakly connected components that assembles the scored edges into tracks. The triplet stage is the piece that lets the pipeline separate electron tracks that share initial hits. On the GPU side, the same models are exported through ONNX and run with ONNX Runtime or TensorRT u

What would settle it

Measure the deployed pipeline on real Run 3 LHCb collisions and compare its reconstructed track multiplicity, momentum spectra, and occupancy dependence with the production 'Search by triplet' algorithm; a divergence in efficiency or false-track rate with pile-up that does not appear in the Monte Carlo evaluation would falsify the transfer of the physics-performance claim to production.

Watch

Extended reading notes

Core claim

ETX4VELO replaces the hand-crafted combinatorial search of the production VELO tracker with a learned pipeline: an MLP embeds detector hits into a Euclidean space, a k-nearest-neighbour graph connects nearby hits, a graph neural network scores each edge as genuine or fake, a triplet classifier handles electrons that share hits, and a weakly-connected-components pass groups surviving edges into tracks. Evaluated with MonteTracko on simulated proton-proton collisions, it achieves tracking efficiency, clone rate, ghost/fake rate, and hit purity comparable to 'Search by triplet' for long particles, VELO-only particles, and electrons, and runs end to end inside Allen on GPUs at throughputs the th

Load-bearing premise

The central claim assumes that the simulated Monte Carlo collisions used for training and evaluation faithfully represent real LHCb Run 3 VELO conditions—occupancy, noise, and alignment—since no validation on real collision data is presented.

Editorial extensions

If this is right

If the central claim holds, LHCb could run VELO track finding with a learned algorithm at the same physics quality as the production search while keeping the entire first-level trigger on GPUs.
The comparable electron performance suggests the pipeline can handle the shared-hit ambiguity that is specifically hard for combinatorial seeding, potentially recovering tracks that classical algorithms lose.
The INT8 results imply that the memory and compute cost of GNN inference can be reduced to a level compatible with the trigger without sacrificing tracking quality.
The FPGA results point toward heterogeneous first-level triggers in which the fixed-shape MLP embedding runs on low-power programmable logic while the data-dependent graph and tracking steps remain on GPUs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Not tested in the paper: the same pipeline could be retrained for other LHCb subdetectors or for the HL-LHC VELO geometry; the graph-construction and GNN stages would need re-validation because occupancy and hit density change materially.
A straightforward testable extension: measure the FPGA implementation on the actual Alveo board, taking power and latency from counters rather than synthesis reports; the paper's power-per-event advantage is currently an estimate.
The sim-to-real question could be closed by running the deployed Allen code on a sample of real Run 3 collisions and comparing track-level outputs with the production algorithm; the thesis does not yet present that evidence.
If the scaling behavior is as reported, the approach could inform trigger design beyond LHCb, since any experiment with a pixel vertex detector and a throughput constraint faces the same combinatorial bottleneck.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Worth a serious referee, with a clear request to fix the framing. The genuinely new thing here is ETX4VELO: a GNN track-finding pipeline adapted from Exa.TrkX to the LHCb VELO, with a triplet classifier for electron tracks, integrated into Allen and run end-to-end on GPUs. The evaluation against the production Search-by-triplet algorithm over eta, phi, pT, vz, and occupancy, using MonteTracko, is the right methodology, and the parenthetical reporting in Tables 8.1–8.3 is honest: the reader can see the difference between the full prototype and the version actually in C++/CUDA. There is also an INT8 quantization study and a partial FPGA implementation of the embedding MLP with power/cost numbers. The work builds on a JINST paper and an IEEE NEWCAS paper, and the code is downloadable. That is real, reproducible engineering, and the thesis deserves referee time.

The soft spots are in the claims, not the measurements. First, the abstract says the pipeline was “accelerated on the FPGA architecture,” but Chapter 10 covers only the embedding MLP. That is an overstatement. Second—and more important—the parenthetical values in Tables 8.1–8.3 are not a minor detail: they are the deployed implementation. The abstract and Chapter 8 headline parity with Search by triplet for the full pipeline with triplets; the version running inside Allen omits that step, and the thesis does not state up front how much the deployed version loses on electrons. If the parentheses are close, fine, but the reader has to dig for it. The framing should be corrected. Third, all physics performance is on simulated MC. No real-data validation appears, so production-readiness is not demonstrated even though the code runs in Allen. Fourth, the GPU throughput numbers come from consumer RTX cards and the FPGA numbers from Vivado synthesis, not the production A5000 or on-board measurements. The thesis mostly discloses these limitations, but they belong in the abstract. None of this invalidates the core engineering result; it just means the claims need to be scoped precisely.

For whom: people working on ML in LHC triggers, FastML/accelerator people, and reviewers who care about deployment details. I would want the revised version to state which pipeline variant achieved the headline numbers and to correct the FPGA claim. Send it to peer review.

Referee Report

3 major / 4 minor

Summary. The thesis presents ETX4VELO, a graph-neural-network-based track reconstruction pipeline for the LHCb VELO, and claims that it reaches physics performance comparable to the production 'Search by triplet' algorithm while running end-to-end inside Allen, LHCb's first-level GPU trigger. The physics performance is evaluated with the MonteTracko framework on simulated proton-proton collisions as a function of eta, phi, pT, vz and occupancy, with the triplet-based Python pipeline as the primary comparison and parenthetical values for the C++/CUDA implementation without the triplet step. A second contribution is an FPGA implementation of the embedding MLP, with throughput, power and cost comparisons against GPUs using Vivado synthesis estimates.

Significance. If the central claims hold, this is a valuable demonstration that a GNN-based tracking pipeline can be deployed inside a real first-level trigger at the LHC collision rate, and it provides concrete evidence on the GPU/FPGA trade-off for such workloads. The manuscript has clear strengths: the evaluation uses an external production baseline, the performance metrics follow LHCb conventions via MonteTracko, the training/validation losses are shown, the ommission of the triplet step in the C++/CUDA version is reported rather than hidden, and the code is organised under a public GitLab group. These features make the work a useful reference for the FastML community. However, several load-bearing points need to be clarified or qualified before the abstract-level claims can be accepted as stated.

major comments (3)

[§8.4, Tables 8.1–8.3; abstract] The headline physics-performance comparison uses the full pipeline with the triplet classifier, while the implementation inside Allen is the C++/CUDA version without the triplet step. Table 8.1–8.3 captions explicitly state that the parenthetical values 'correspond to the performance of the ETX4VELO pipeline without the triplet approach, as currently implemented in C++/CUDA and presented in Chapter 9'. Since Chapter 9 is the version that actually runs in Allen, the abstract's claim that the pipeline is implemented end-to-end inside the trigger and achieves the reported physics performance needs to be tied to this exact configuration. Please state explicitly whether the triplet classifier is part of the Allen implementation; if it is not, the central comparison must be reported for the deployed configuration, or the claim should be qualified accordingly.
[§8.3.1, Figs. 8.18–8.25] All physics-performance results are obtained from simulated Monte Carlo samples (e.g., 7.6 interactions per crossing at sqrt(s)=14 TeV). No validation on Run 3 collision data is presented. The central claim that ETX4VELO is production-ready inside the LHCb trigger depends on the assumption that the simulation faithfully reproduces VELO occupancy, noise and alignment. If real-data validation is not yet possible, the manuscript should say so explicitly and discuss the expected sim-to-real transfer, rather than presenting the simulated performance without qualification.
[§9.3–§9.4, Tables 9.5–9.7; §10.1–§10.3, Tables 10.2–10.7] The throughput comparisons are measured on consumer GPUs (RTX 2080 Ti, RTX 3090), not the production RTX A5000 used in Allen, so the claim that the pipeline fits the trigger budget relies on an extrapolation. In addition, the FPGA throughput and power figures come from Vivado synthesis estimates rather than on-board measurements, and the FPGA implementation covers only the embedding MLP, not the full pipeline. The secondary FPGA/GPU comparison should be scoped to the measured/synthesized component and clearly labelled as an estimate.

minor comments (4)

[Abstract and §10.3] The abstract says the pipeline 'was also accelerated on the FPGA architecture'; Chapter 10 in fact implements only the embedding MLP on FPGA. Consider phrasing this as a partial acceleration with the scope stated up front.
[Tables 9.5–9.6] The comparisons to '530000' and '860000' for the full Allen pipeline should state the units (events/s) and the exact hardware/conditions under which these reference numbers were obtained.
[§3.4, §4.1] Typographical errors: 'competion' should be 'competition', 'byconsequence' should be 'by consequence'. There are also inconsistent spellings of 'MonteTracko' in figure captions.
[§9.2] For reproducibility, give exact software versions and commit hashes or release tags for the GDL4HEP code used for the reported numbers, in addition to the dependency versions already listed.

Circularity Check

0 steps flagged · score 1.0 of 10

No material circularity: central claims rest on external benchmarks (Search by triplet, Allen, Monte Carlo truth), not on fitted parameters renamed as predictions.

full rationale

This is an empirical engineering thesis rather than a derivation from first principles, so the circularity patterns are largely inapplicable. The central physics-performance claim is a direct comparison between ETX4VELO and the production Search-by-triplet algorithm inside Allen, evaluated on simulated LHCb events with MonteTracko (Ch. 8, Tables 8.1–8.3, Figs. 8.18–8.25). The GNN is trained on simulation truth with separate validation losses (Figs. 8.15–8.17), and the baseline is external production code, so the comparison does not reduce to the training data or to the thesis's own definitions. Throughput claims are measured against the full Allen VELO pipeline on specified GPUs (Tables 9.5–9.6), and the FPGA numbers are synthesis-based estimates on Alveo cards (Tables 10.2–10.7). The self-citations to the author's JINST [8] and NEWCAS [13] papers reproduce the same empirical measurements, but they are not load-bearing in a circular way because the evidence is externally falsifiable against the production algorithm and simulation truth. One non-circular consistency caveat is present: the parenthetical values in Table 8.1 show that the C++/CUDA Allen implementation omits the triplet classifier, so the strongest parity claim applies to the full Python pipeline rather than the deployed Allen version; this is a correctness/scope risk, not a circularity.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

All load-bearing degrees of freedom are engineering choices of an ML pipeline: graph construction parameters, score thresholds, model sizes, and quantization or precision settings. The pipeline introduces no new physical entities and no new physics axioms beyond background physics. The entire results chain depends on simulation fidelity, the standard LHCb Monte Carlo, and synthesis-based estimates on the FPGA side, which is why those appear as domain assumptions.

free parameters (5)

k-NN neighborhood size k
Used for the rough graph construction (Section 8.3.2); chosen by hand, controls graph density, physics performance, and inference cost.
Edge and triplet score thresholds
Operating points behind the efficiency and fake-rate numbers in Tables 8.1 to 8.3 and Figures 8.18 to 8.25; threshold sensitivity is not shown, so the comparison rests on these choices.
Embedding MLP and GNN architecture sizes
Reduced 'down to the minimum size possible, while keeping the physics performance within acceptable levels' (Figure 9.2 caption); a hand-guided tradeoff between physics performance and throughput.
INT8 quantization scales (PTQ) = calibrated on a representative sample
Section 9.2.5: quantization scales are fitted on a calibration dataset during post-training quantization; the performance delta is reported in Table 9.4.
FPGA fixed-point precisions ap_fixed<a,b> = 8-bit and 16-bit variants
Section 10.1.4 and Tables 10.5 to 10.7: bit widths chosen after the tolerance study in Figure 10.4; they set resource usage and the reported throughput and power figures.

assumptions (5)

domain assumption Monte Carlo simulation truth correctly labels which detector hits belong to the same particle, and the simulated VELO response matches the real detector.
Invoked in Section 8.3.1 (Datasets) and used through MonteTracko for all physics performance claims; the quoted conditions (7.6 interactions per crossing, sqrt(s)=14 TeV, Figure 7.4) are simulation conditions. No real-data validation appears in the visible text.
domain assumption Supervised training on simulated pp samples transfers to the pile-up and occupancy conditions of the trigger deployment.
The training process (Section 8.3.6) and occupancy scaling studies (Figures 9.11 to 9.13) assume the trained model and measured throughput hold at production occupancies without retraining or degradation beyond what is reported.
domain assumption The production Allen framework and its Search by triplet implementation provide an accurate baseline for the classical tracking comparison.
Tables 8.1 to 8.3 and Figures 8.18 to 8.25 compare against Allen's implementation as ground truth for classical tracking; no independent re-implementation is provided.
standard math Standard ML and HPC background (backpropagation, SGD, message passing, Amdahl's law, CUDA semantics) is applicable as presented.
Chapters 4 and 5 are pedagogical background; the results rely on these standard tools without re-derivation.
domain assumption Vivado HLS synthesis estimates of clock period, latency, and resource utilization are reliable proxies for on-board FPGA performance.
Tables 10.2 to 10.7 report FPGA throughput and power from synthesis, and Table 10.7 is explicitly labeled as 'theoretical performance' for the Alveo implementations, whereas GPU figures are measured; a common measurement basis is not established.

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Cite this review

Pith. "Pith review of Real-Time Analysis of Unstructured Data with Machine Learning on Heterogeneous Architectures." pith.science (2026). https://pith.science/paper/JGHTBH44

@misc{pith2026250807423,
  author       = {Pith},
  title        = {Pith review of: Real-Time Analysis of Unstructured Data with Machine Learning on Heterogeneous Architectures},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JGHTBH44}},
  note         = {Machine review of arXiv:2508.07423}
}

read the original abstract

As the particle physics community needs higher and higher precisions in order to test our current model of the subatomic world, larger and larger datasets are necessary. With upgrades scheduled for the detectors of colliding-beam experiments around the world, and specifically at the Large Hadron Collider at CERN, more collisions and more complex interactions are expected. This directly implies an increase in data produced and consequently in the computational resources needed to process them. At CERN, the amount of data produced is gargantuan. This is why the data have to be heavily filtered and selected in real time before being permanently stored. This data can then be used to perform physics analyses, in order to expand our current understanding of the universe and improve the Standard Model of physics. This real-time filtering, known as triggering, involves complex processing happening often at frequencies as high as 40 MHz. This thesis contributes to understanding how machine learning models can be efficiently deployed in such environments, in order to maximize throughput and minimize energy consumption. Inevitably, modern hardware designed for such tasks and contemporary algorithms are needed in order to meet the challenges posed by the stringent, high-frequency data rates. In this work, I present our graph neural network-based pipeline, developed for charged particle track reconstruction at the LHCb experiment at CERN. The pipeline was implemented end-to-end inside LHCb's first-level trigger, entirely on GPUs. Its performance was compared against the classical tracking algorithms currently in production at LHCb. The pipeline was also accelerated on the FPGA architecture, and its performance in terms of power consumption and processing speed was compared against the GPU implementation.

Figures

Figures reproduced from arXiv: 2508.07423 by the authors.

**Figure 2.1.** Comparison of the streaming data rates (in bytes per second) versus [PITH_FULL_IMAGE:figures/full_fig_p048_2_1.png] view at source ↗

**Figure 2.2.** Plan for the LHC/High-Luminosity LHC (updated in January 2025). Figure from [ [PITH_FULL_IMAGE:figures/full_fig_p051_2_2.png] view at source ↗

**Figure 2.3.** LHCb luminosity results over the various data-taking periods at the LHC. [PITH_FULL_IMAGE:figures/full_fig_p052_2_3.png] view at source ↗

Figures from the paper (99 more)

**Figure 2.4.** Figure 2.4: The evolution of the data bandwidth as a function of time for past and [PITH_FULL_IMAGE:figures/full_fig_p053_2_4.png]

**Figure 2.6.** Figure 2.6: LHC / HL-LHC Plan (updated in February 2022). Taken from [ [PITH_FULL_IMAGE:figures/full_fig_p054_2_6.png]

**Figure 2.7.** Figure 2.7: Projected evolution of ATLAS compute usage from 2020 until 2036, under two R&D scenarios. The Figure 2.5: Projected evolution of the ATLAS compute usage from 2020 unt [PITH_FULL_IMAGE:figures/full_fig_p054_2_7.png]

**Figure 3.1.** Figure 3.1: A cylindrical coordinate system defined by an origin [PITH_FULL_IMAGE:figures/full_fig_p061_3_1.png]

**Figure 3.2.** Figure 3.2: The polar (𝜃) and azimuthal (𝜑) angles. Adapted from [101]. 𝐿 𝑀 𝑁 = →↑ 𝑂 = 180↓ 𝑁 = →2.44 𝑂 = 170↓ 𝑁 = →1.32 𝑂 = 150↓ 𝑁 = →0.88 𝑂 = 135↓ 𝑁 = →0.55 𝑂 = 120↓ 𝑁 = 0 𝑂 = 90↓ 𝑁 = 0.55 𝑂 = 60↓ 𝑁 = 0.88 𝑂 = 45↓ 𝑁 = 1.32 𝑂 = 30↓ 𝑁 = 2.43 𝑂 = 10↓ 𝑂 𝑂 = 0↓ 𝑁 = +↑ [PITH_FULL_I…

**Figure 3.3.** Figure 3.3: Values of pseudorapidity 𝜂 versus polar angle 𝜃. Figure from [103] [PITH_FULL_IMAGE:figures/full_fig_p062_3_3.png]

**Figure 3.4.** Figure 3.4: Illustration of beam bunching utilized at the Large Hadron Collider at [PITH_FULL_IMAGE:figures/full_fig_p063_3_4.png]

**Figure 3.5.** Figure 3.5: Illustration of Primary Vertices (PVs) and Secondary Vertices (SVs) [PITH_FULL_IMAGE:figures/full_fig_p064_3_5.png]

**Figure 3.6.** Figure 3.6: A projectile scattering off a target particle. The impact parameter [PITH_FULL_IMAGE:figures/full_fig_p066_3_6.png]

**Figure 3.7.** Figure 3.7: The Standard Model of elementary particles including twelve fundamental [PITH_FULL_IMAGE:figures/full_fig_p068_3_7.png]

**Figure 4.1.** Figure 4.1: Euler diagram of AI and its subfields as relevant to this thesis. The term machine learning is believed to have been coined by Arthur Samuel in 1959 for his work on programming a computer to play checkers [131]. In general, AI is considered as a more general term …

**Figure 4.2.** Figure 4.2: Example of different representations: Suppose we want to separate [PITH_FULL_IMAGE:figures/full_fig_p074_4_2.png]

**Figure 4.3.** Figure 4.3: Examples of underfitting and overfitting on a synthetically generated [PITH_FULL_IMAGE:figures/full_fig_p080_4_3.png]

**Figure 4.4.** Figure 4.4: Illustration of a deep feedforward neural network, highlighting its input, [PITH_FULL_IMAGE:figures/full_fig_p081_4_4.png]

**Figure 4.5.** Figure 4.5: The operations between the input and the first hidden layer. Weights are [PITH_FULL_IMAGE:figures/full_fig_p082_4_5.png]

**Figure 4.6.** Figure 4.6: Popular activation functions. 𝑦 = 𝑓NN(x) = 𝑓𝑘 ( 𝒇 𝑘−1 (· · · 𝒇 2 ( 𝒇 1 (x)))) , (4.26) where 𝒇𝑙 , for the layer index 𝑙 = 1, ..., 𝑘 − 1, are functions with vector output of the form: 𝒇𝑙 (z) = gl(W𝑙z + b𝑙) , (4.27) where W𝑙 are the weights between layers 𝑙 and 𝑙 − 1, …

**Figure 4.7.** Figure 4.7: Illustration of gradient descent in a two-dimensional parameter space. [PITH_FULL_IMAGE:figures/full_fig_p085_4_7.png]

**Figure 4.8.** Figure 4.8: Illustration of the process of convolving a filter across an image using a [PITH_FULL_IMAGE:figures/full_fig_p087_4_8.png]

**Figure 4.9.** Figure 4.9: The architecture of LeNet-5, a convolutional neural network for digits recognition, as depicted in the original paper [ [PITH_FULL_IMAGE:figures/full_fig_p089_4_9.png]

**Figure 4.10.** Figure 4.10: A directed graph with eight vertices and seven edges. 3 8 1 7 6 5 2 4 [PITH_FULL_IMAGE:figures/full_fig_p090_4_10.png]

**Figure 4.12.** Figure 4.12: Illustration of the process of message passing. Every node defines [PITH_FULL_IMAGE:figures/full_fig_p091_4_12.png]

**Figure 4.13.** Figure 4.13: Illustration of the process of symmetric quantization. The scale is [PITH_FULL_IMAGE:figures/full_fig_p093_4_13.png]

**Figure 5.1.** Figure 5.1: Demonstration of Amdahl’s law for the theoretical maximum speedup of [PITH_FULL_IMAGE:figures/full_fig_p097_5_1.png]

**Figure 5.2.** Figure 5.2: Historical evolution of microprocessor clock rates from 1980 to 2012, [PITH_FULL_IMAGE:figures/full_fig_p098_5_2.png]

**Figure 5.3.** Figure 5.3: Flynn’s Taxonomy. (a) Single Instruction Stream, Single Data Stream (SISD), (b) Single Instruction Stream, Multiple Data Stream (SIMD), (c) Multiple Instruction Stream, Single Data Stream (MISD), (d) Multiple Instruction Stream, Multiple Data Stream (MIMD). The instr…

**Figure 5.4.** Figure 5.4: CUDA thread and memory hierarchy. Figure from [ [PITH_FULL_IMAGE:figures/full_fig_p103_5_4.png]

**Figure 5.5.** Figure 5.5: Illustration of the memory hierarchy for a Single Instruction, Multiple [PITH_FULL_IMAGE:figures/full_fig_p104_5_5.png]

**Figure 5.6.** Figure 5.6: Comparison of the allocation of resources between a CPU and a GPU. [PITH_FULL_IMAGE:figures/full_fig_p105_5_6.png]

**Figure 5.7.** Figure 5.7: Illustration of heterogeneous programming using the CUDA programming [PITH_FULL_IMAGE:figures/full_fig_p107_5_7.png]

**Figure 5.8.** Figure 5.8: Illustration of the structure of an FPGA, highlighting its three fundamental [PITH_FULL_IMAGE:figures/full_fig_p109_5_8.png]

**Figure 5.9.** Figure 5.9: Block diagram illustration of a System on a Chip (SoC) FPGA, highlight [PITH_FULL_IMAGE:figures/full_fig_p109_5_9.png]

**Figure 5.10.** Figure 5.10: Illustration of a comparison of different processor architectures based [PITH_FULL_IMAGE:figures/full_fig_p111_5_10.png]

**Figure 6.1.** Figure 6.1: Aerial view of the European Organization for Nuclear Research (CERN), [PITH_FULL_IMAGE:figures/full_fig_p113_6_1.png]

**Figure 6.2.** Figure 6.2: Sketch of the LHC showing its accelerator ring with two beam pipes [PITH_FULL_IMAGE:figures/full_fig_p114_6_2.png]

**Figure 6.3.** Figure 6.3: The CERN accelerator complex during Run 2. Figure from [ [PITH_FULL_IMAGE:figures/full_fig_p115_6_3.png]

**Figure 6.4.** Figure 6.4: Layout of the upgraded LHCb detector. Figure from [ [PITH_FULL_IMAGE:figures/full_fig_p117_6_4.png]

**Figure 6.5.** Figure 6.5: Upgrade VELO module layout, with the LHCb acceptance highlighted. [PITH_FULL_IMAGE:figures/full_fig_p118_6_5.png]

**Figure 6.6.** Figure 6.6: Left: Schematic top view of the 𝑧-𝑥 plane at 𝑦 = 0, illustrating the 𝑧-extent of the luminous region and the nominal LHCb pseudorapidity acceptance, 2 < 𝜂 < 5. Right: Schematic of the nominal sensor layout around the 𝑧-axis in the closed VELO configuration. Half of t…

**Figure 22.** Figure 22: (left) Resolution in the x direction for small angles ✓y. (right) Absolute measurement Figure 6.7: Dependence of hit resolution on the track polar angle. Left: Single hit [PITH_FULL_IMAGE:figures/full_fig_p120_22.png]

**Figure 17.** Figure 17: Percentage of a radiation length (between the origin and Figure 6.8: Left: Percentage of radiation length (betwe [PITH_FULL_IMAGE:figures/full_fig_p121_17.png]

**Figure 6.9.** Figure 6.9: Upgraded LHCb online system. All system components are connected to [PITH_FULL_IMAGE:figures/full_fig_p122_6_9.png]

**Figure 6.10.** Figure 6.10: Upgraded LHCb online system with three GPUs running HLT1 on the [PITH_FULL_IMAGE:figures/full_fig_p123_6_10.png]

**Figure 6.11.** Figure 6.11: Illustration of the simulation process inside LHCb. Generated with [ [PITH_FULL_IMAGE:figures/full_fig_p124_6_11.png]

**Figure 6.12.** Figure 6.12: Production rates estimates for various Standard Model processes at the [PITH_FULL_IMAGE:figures/full_fig_p125_6_12.png]

**Figure 6.13.** Figure 6.13: Illustration of a 𝐵 + → 𝐽/𝜓𝐾+ candidate event in LHCb data, highlighting the tracks, primary and secondary vertices, and the impact parameter of the antimuon track. Figure from [228]. is only achievable through a software-based trigger system operating on a detecto…

**Figure 6.** Figure 6: LHCb Run 2 (left) and upgrade (right) online dataflow diagrams in a compact format. Figure 6.14: LHCb trigger diagram for Run 3. Figure from [PITH_FULL_IMAGE:figures/full_fig_p127_6.png]

**Figure 6.15.** Figure 6.15: LHCb upgrade dataflow focusing on the real-time aspects. Figure [PITH_FULL_IMAGE:figures/full_fig_p129_6_15.png]

**Figure 6.16.** Figure 6.16: Illustration of the LHCb trigger computing model. The same re [PITH_FULL_IMAGE:figures/full_fig_p130_6_16.png]

**Figure 6.17.** Figure 6.17: Schematic of the HLT1 reconstruction at LHCb. Figure from [ [PITH_FULL_IMAGE:figures/full_fig_p131_6_17.png]

**Figure 6.** Figure 6: Velo tracking e!ciency as a function of momentum and transverse momentum (pT ). [8] 2.2 Primary Vertex finding One of the physics requirement in HLT1 is to reconstruct all primary vertices (PVs) from proton-proton collisions. VELO tracks can be extrapolated as straight…

**Figure 6.18.** Figure 6.18: Breakdown of the default HLT1 reconstruction sequence published [PITH_FULL_IMAGE:figures/full_fig_p132_6_18.png]

**Figure 7.1.** Figure 7.1: Cloud chamber photograph of the first positron ever observed. The thick [PITH_FULL_IMAGE:figures/full_fig_p136_7_1.png]

**Figure 7.2.** Figure 7.2: Depiction of the track types in the LHCb detector during Run 3. Figure [PITH_FULL_IMAGE:figures/full_fig_p137_7_2.png]

**Figure 7.3.** Figure 7.3: Examples of pixels being activated due to the passage of charged particles [PITH_FULL_IMAGE:figures/full_fig_p140_7_3.png]

**Figure 25.** Figure 25: Number of VELO hits per track (at Figure 25: Number of VELO hits per track (at [PITH_FULL_IMAGE:figures/full_fig_p141_25.png]

**Figure 7.5.** Figure 7.5: Search by triplet [26], used for tracking in the VELO. It comprises iterative seeding and following stages, where modules are considered from right to left. (a) Seeding stage: For the hit 𝑐0, four candidate hits 𝑐0𝑎, 𝑐0𝑏, 𝑐0𝑐, and 𝑐0𝑑 are considered in the neighborin…

**Figure 7.6.** Figure 7.6: VELO tracking efficiency as a function of [PITH_FULL_IMAGE:figures/full_fig_p144_7_6.png]

**Figure 8.1.** Figure 8.1: Illustration of the process of moving from hits in the detector to the “rough” graph of the event. Colored hits correspond to [PITH_FULL_IMAGE:figures/full_fig_p151_8_1.png]

**Figure 8.2.** Figure 8.2: The process of graph construction for simulated LHCb data in the VELO [PITH_FULL_IMAGE:figures/full_fig_p152_8_2.png]

**Figure 8.3.** Figure 8.3: Illustration of the process of moving from the event graph to the reconstructed tracks of the event. Colored hits correspond to [PITH_FULL_IMAGE:figures/full_fig_p153_8_3.png]

**Figure 8.5.** Figure 8.5: Evaluation of the early version of the ETX4VELO pipeline with the MonteTracko library, with a minimum track length of [PITH_FULL_IMAGE:figures/full_fig_p156_8_5.png]

**Figure 8.6.** Figure 8.6: The percentage of particles versus the number of shared hits they have, [PITH_FULL_IMAGE:figures/full_fig_p157_8_6.png]

**Figure 8.7.** Figure 8.7: Example of 2 electrons (in red and purple) sharing their first hit (in black) [PITH_FULL_IMAGE:figures/full_fig_p158_8_7.png]

**Figure 8.8.** Figure 8.8: Example of 2 electrons (in red and purple) sharing their first five hits (in [PITH_FULL_IMAGE:figures/full_fig_p158_8_8.png]

**Figure 8.9.** Figure 8.9: Illustration of the process of moving from hit–hit connections to edge– [PITH_FULL_IMAGE:figures/full_fig_p159_8_9.png]

**Figure 8.10.** Figure 8.10: Schematic of the encoding step. The hit coordinates are processed [PITH_FULL_IMAGE:figures/full_fig_p163_8_10.png]

**Figure 8.11.** Figure 8.11: Schematic of the message passing step. The hit encodings are updated by [PITH_FULL_IMAGE:figures/full_fig_p163_8_11.png]

**Figure 8.12.** Figure 8.12: Schematic of the classification step. The final edge encodings are used [PITH_FULL_IMAGE:figures/full_fig_p164_8_12.png]

**Figure 8.13.** Figure 8.13: Visual representation of the three triplet configurations in the edge graph: [PITH_FULL_IMAGE:figures/full_fig_p166_8_13.png]

**Figure 8.14.** Figure 8.14: The architecture of the embedding network used for the physics [PITH_FULL_IMAGE:figures/full_fig_p167_8_14.png]

**Figure 8.15.** Figure 8.15: Training and validation losses for the Embedding MLP used for the [PITH_FULL_IMAGE:figures/full_fig_p167_8_15.png]

**Figure 8.16.** Figure 8.16: Training and validation losses for the GNN ending with the edge [PITH_FULL_IMAGE:figures/full_fig_p168_8_16.png]

**Figure 8.17.** Figure 8.17: Training and validation losses for the GNN ending with the triplet [PITH_FULL_IMAGE:figures/full_fig_p168_8_17.png]

**Figure 8.18.** Figure 8.18: Comparison of ETX4VELO and Search by triplet in Allen, as a function [PITH_FULL_IMAGE:figures/full_fig_p170_8_18.png]

**Figure 8.19.** Figure 8.19: Comparison of ETX4VELO and Search by triplet in Allen, as a function [PITH_FULL_IMAGE:figures/full_fig_p170_8_19.png]

**Figure 8.20.** Figure 8.20: Comparison of ETX4VELO and Search by triplet in Allen, as a function [PITH_FULL_IMAGE:figures/full_fig_p171_8_20.png]

**Figure 8.21.** Figure 8.21: Comparison of ETX4VELO and Search by triplet in Allen, as a function [PITH_FULL_IMAGE:figures/full_fig_p171_8_21.png]

**Figure 8.22.** Figure 8.22: Comparison of ETX4VELO and Search by triplet in Allen, as a function [PITH_FULL_IMAGE:figures/full_fig_p171_8_22.png]

**Figure 8.23.** Figure 8.23: Comparison of ETX4VELO and Search by triplet in Allen, as a function [PITH_FULL_IMAGE:figures/full_fig_p172_8_23.png]

**Figure 8.24.** Figure 8.24: Track-finding performance comparison of Search by triplet in Allen [PITH_FULL_IMAGE:figures/full_fig_p172_8_24.png]

**Figure 8.25.** Figure 8.25: Fake rate comparison of Search by triplet in Allen versus ETX4VELO [PITH_FULL_IMAGE:figures/full_fig_p173_8_25.png]

**Figure 9.1.** Figure 9.1: The process of passing the ETX4VELO models from the Python to the [PITH_FULL_IMAGE:figures/full_fig_p177_9_1.png]

**Figure 9.2.** Figure 9.2: Starting from the original Exa.TrkX model architectures, the ETX4VELO [PITH_FULL_IMAGE:figures/full_fig_p180_9_2.png]

**Figure 9.3.** Figure 9.3: Illustration of combining and storing various points in 3-dimensional [PITH_FULL_IMAGE:figures/full_fig_p181_9_3.png]

**Figure 9.4.** Figure 9.4: The conventional two-level parallelization scheme used in Allen. Events [PITH_FULL_IMAGE:figures/full_fig_p181_9_4.png]

**Figure 9.5.** Figure 9.5: The process of deploying ML models trained in PyTorch on an Nvidia [PITH_FULL_IMAGE:figures/full_fig_p183_9_5.png]

**Figure 9.6.** Figure 9.6: Illustration of the function of ONNX Runtime for different training [PITH_FULL_IMAGE:figures/full_fig_p183_9_6.png]

**Figure 9.7.** Figure 9.7: The process of executing an ONNX exported model using ONNX [PITH_FULL_IMAGE:figures/full_fig_p184_9_7.png]

**Figure 9.8.** Figure 9.8: The different LHCb events are batched together and passed on to the [PITH_FULL_IMAGE:figures/full_fig_p184_9_8.png]

**Figure 9.9.** Figure 9.9: Illustration of the process of performing Post-Training Quantization [PITH_FULL_IMAGE:figures/full_fig_p187_9_9.png]

**Figure 9.10.** Figure 9.10: Throughput comparison of track reconstruction in the VELO on an [PITH_FULL_IMAGE:figures/full_fig_p190_9_10.png]

**Figure 9.11.** Figure 9.11: Comparison of the scaling of the throughput as a function of occupancy [PITH_FULL_IMAGE:figures/full_fig_p192_9_11.png]

**Figure 9.12.** Figure 9.12: Comparison of the ETX4VELO throughput as a function of occupancy [PITH_FULL_IMAGE:figures/full_fig_p193_9_12.png]

**Figure 9.13.** Figure 9.13: Comparison of the ETX4VELO throughput as a function of occupancy [PITH_FULL_IMAGE:figures/full_fig_p193_9_13.png]

**Figure 10.1.** Figure 10.1: Illustration of the process of converting an ML model trained in PyTorch [PITH_FULL_IMAGE:figures/full_fig_p200_10_1.png]

**Figure 10.2.** Figure 10.2: Block diagram of the Zynq-7000 family, highlighting the processing [PITH_FULL_IMAGE:figures/full_fig_p201_10_2.png]

**Figure 10.3.** Figure 10.3: Setup of the PYNQ-Z2 board. 1: The board is set to be booted from [PITH_FULL_IMAGE:figures/full_fig_p202_10_3.png]

**Figure 10.4.** Figure 10.4: Percentage of values predicted, using the untuned, compiled HLS [PITH_FULL_IMAGE:figures/full_fig_p205_10_4.png]

**Figure 10.5.** Figure 10.5: Comparison between the FPGA and GPU ML model inference latency [PITH_FULL_IMAGE:figures/full_fig_p207_10_5.png]

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