Circuit-level-configurable Zero-field Superconducting Diodes: A Universal Platform Beyond Intrinsic Symmetry Breaking

Anqi Wang; Bingbing Tong; Dong Pan; Fanming Qu; Guangtong Liu; Guoan Li; Jiangping Hu; Jianhua Zhao; Jie Shen; Li Lu

REVIEW 2 major objections 5 minor 1 cited by

Circuit-level-configurable Zero-field Superconducting Diodes: A Universal Platform Beyond Intrinsic Symmetry Breaking

T0 review · 2 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read Ordinary wire resistance creates zero-field superconducting diodes.

desk verdict A plausible and cleanly motivated circuit-level mechanism for zero-field SDE, undercut by uncalibrated constant offsets in the decisive controls; still deserves a serious referee. read the letter →

arxiv 2505.18330 v1 pith:KYO422AO submitted 2025-05-23 cond-mat.supr-con cond-mat.mes-hallquant-ph

Xiaofan Shi , Ziwei Dou , Dong Pan , Guoan Li , Yupeng Li , Anqi Wang , Zhiyuan Zhang , Xingchen Guo

show 10 more authors

Xiao Deng Bingbing Tong Zhaozheng Lyu Peiling Li Fanming Qu Guangtong Liu Jianhua Zhao Jiangping Hu Li Lu Jie Shen

This is my paper · ORCID

classification cond-mat.supr-concond-mat.mes-hallquant-ph

keywords superconductingdiodeeffectzero-fieldCooper-pairtransistorchemicalpotentialshiftlineresistanceCoulombblockadecircuit-levelcontrolInAsnanowire

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that the zero-field superconducting diode effect (SDE) seen in a Cooper-pair transistor comes from an ordinary experimental detail: the resistance of the measurement line, which shifts the device's chemical potential by $-|e| I_{\mathrm{DC}} R_L$ when a bias current flows. Because the critical current of a Cooper-pair transistor oscillates with gate voltage via Coulomb blockade, positive and negative applied currents move the critical-current traces along the gate axis in opposite directions, making $I_C^+ \neq |I_C^-|$ even though the superconductor itself has no intrinsic symmetry breaking. The authors demonstrate the mechanism with three controls: swapping which contact is grounded flips the diode polarity as the sign of the shift changes, symmetrically biasing both contacts cancels the shift and eliminates the SDE, and increasing $R_L$ or $I_C$ increases the gate shift and diode efficiency up to about 60% at zero magnetic field. If correct, this turns a previously exotic effect into a generic, circuit-level design tool and calls into question interpretations of some zero-field SDEs in terms of intrinsic time-reversal symmetry breaking.

What carries the argument

The key mechanism is the chemical potential shift $-|e| I_{\mathrm{DC}} R_L$ from the line resistance acting on a Cooper-pair transistor, whose critical current is steeply gate-dependent through Coulomb blockade. The CPT's $I_C(V_{\mathrm{PG}})$ oscillations make the device a sensitive probe of Fermi-level shifts, so that the same bias current in opposite directions moves the positive and negative critical-current curves oppositely along the gate-voltage axis, creating a gate-controllable $\Delta I_C$ without any intrinsic symmetry breaking.

What would settle it

Run the symmetric biasing configuration in which the SDE is reported to vanish, extract $I_C^+$ and $|I_C^-|$ without any offset subtraction, and check whether the same constant offsets (e.g., ±0.35 nA) reappear; if they do, the offsets are instrumental and the subtraction is legitimate, but if they vanish, the subtraction removed part of the effect being measured.

Watch

Extended reading notes

Core claim

The central discovery is that a field-free superconducting diode can be produced purely by the chemical potential shift $-|e| I_{\mathrm{DC}} R_L$ developed across the external line resistance in the measurement circuit. In a Cooper-pair transistor with $E_C \sim E_J$, the critical current is a sensitive function of the island's Fermi level through Coulomb blockade, so a positive bias $I_C^+$ displaces the Fermi level downward and a negative bias $|I_C^-|$ displaces it upward, shifting the two $I_C(V_{\mathrm{PG}})$ traces in opposite directions along the gate axis. The resulting difference $\Delta I_C = I_C^+ - |I_C^-|$ is present at zero field, is an even function of magnetic field with a maximum at $B=0$, can be switched in polarity by choosing which contact is grounded, and can be nulled by symmetric biasing. The authors conclude that the observed zero-field SDE in this platform is entirely accounted for by this circuit-level mechanism, explicitly excluding intrinsic inversion and time-reversal symmetry breaking.

Load-bearing premise

The control experiments assume that small constant offsets subtracted from the critical-current branches (for example, ±0.35 nA in Fig. 3d,e,g and Fig. 4) are purely instrumental and unrelated to the diode effect, but no independent calibration is provided to prove that.

Editorial extensions

If this is right

Any superconductor whose critical current is gate- or density-sensitive will show a zero-field SDE when its measurement line has a finite resistance, so the effect should be generic across materials.
The diode polarity is set by which side of the device is grounded, and its efficiency can be tuned by $R_L$, by the critical current, and by the gate voltage.
Previously reported zero-field SDEs attributed to exotic intrinsic symmetry breaking should be re-examined for a possible circuit-level chemical-potential-shift contribution.
The mechanism works at room-temperature configurable line resistances and should extend to high-$T_c$ and low-dimensional superconductors where $I_C$ is chemically sensitive.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The same line-resistance mechanism should produce rectification in any two-terminal superconductor with a sharp gate dependence, including nanowire and 2D-material junctions beyond the CPT, so the platform's reach is wider than the paper's prototype.
The reported constant offsets could be measured independently by replacing the device with a test resistor with exactly matched $I_C$ sensitivity, or by comparing the offset magnitude in devices with different $R_L$; such calibration would settle the mechanism's exclusivity.
An active tunable resistor (e.g., a field-effect transistor at room temperature) could replace the passive $R_L$ to modulate the diode efficiency in real time, a practical step the paper only hints at.
The model predicts that for small $|I_C R_L|$ the gate shift $dV_{\mathrm{PG}}$ should grow linearly with $|I_C R_L|$ and saturate at half a Coulomb period; a systematic study of the full curve would provide a quantitative test independent of the maximum-efficiency points shown.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

You should know two things about this paper. First, it demonstrates a zero-field superconducting diode effect in a Cooper-pair transistor and attributes it to the chemical potential shift -|e|ICRL from the series line resistance, not to intrinsic symmetry breaking. That mechanism is physically reasonable, and the ground-swap polarity reversal is a genuinely nice control. Second, the most decisive controls rest on subtracting antisymmetric constant offsets from the critical-current traces, and those offsets are never independently calibrated. That is the soft spot, and it is not a small one.

What is actually new here is not the voltage-drop-across-a-resistor physics; that is textbook. What is new is using that effect as an explanation for zero-field SDE, with gate-switchable polarity and efficiency, and explicitly arguing that prior zero-field SDE reports attributed to intrinsic TRSB may need re-examination. The data in Fig. 2 show a clear gate-dependent dIC at B=0, and the even-in-B behavior distinguishes it from finite-field SDE. The sweep-order control, the ground-swap reversal, and the symmetric-bias null are exactly the right experiments. The dVPG scaling with |ICRL| in Figs. 4g,h provides separate support that does not depend on the offset subtraction, and the iterative model in Supp. Fig. 9d qualitatively captures the tilted IC(VPG) at large RL. Credit where it is due: the experimental logic is mostly sound, and the paper is well written.

Now the soft spot. Supplementary Section 5 states that all IC+ and |IC-| traces in Fig. 3d,e,g and Fig. 4 were corrected by antisymmetric offsets of -0.35 nA and +0.35 nA, shifting dIC by +0.7 nA. If dIC is of order 1 nA, that is a large correction. The paper asserts the offset is “not due to the SDE” but gives no calibration, no raw unsubtracted traces, and the offset varies between datasets (0.35, 0.05, 0.23 nA). The ground-swap reversal is robust to a common-mode offset, so that control survives, but the null in Fig. 3i and the absolute efficiency magnitudes, including the ~60% claim, are hostage to the offset choice. The additional claim that this “challenges” prior intrinsic zero-field SDE interpretations is also stronger than the evidence supports; without reanalyzing those specific devices, it is a caution, not a refutation.

I would send this to peer review. The mechanism is important, the central idea is clear, and the paper has real controls. A good referee should demand raw traces, an independent calibration of the offsets (for example, a configuration where SDE is impossible), and error bars. If the offsets check out, the paper is solid. If not, the core attribution loses its support.

Referee Report

2 major / 5 minor

Summary. The paper reports a zero-field superconducting diode effect (SDE) in an InAs-Al Cooper-pair transistor (CPT), attributing the effect not to intrinsic inversion or time-reversal symmetry breaking in the superconductor, but to the chemical-potential shift -|e|I_CR_L produced by the line resistance between the device and ground. The authors observe gate-dependent non-reciprocal critical currents, an even magnetic-field dependence of the diode signal, polarity reversal upon swapping which contact is grounded through R_L, a null under symmetric biasing, and tuning of the diode efficiency by R_L and I_C, with a maximal reported efficiency of about 60%. They argue that this is a generic, circuit-level mechanism that challenges material-specific intrinsic-symmetry-breaking interpretations of zero-field SDEs.

Significance. If established, the result is conceptually and practically significant: it identifies a common external-circuit element, the measurement line resistance, as a sufficient source of zero-field nonreciprocity in gate-sensitive superconducting devices, and it demonstrates electrical control of polarity and efficiency. The paper has genuine strengths: the raw Fig. 2 observation is presented without offset subtraction and is qualitatively convincing; the ground-swap and symmetric-bias controls are clever and, in principle, decisive; the simple CPT model and the EC/EJ fits are reproducible; and the Supplementary Information is unusually transparent about the data treatment, including the offset subtractions. However, the central controls and the reported efficiency magnitudes depend on uncalibrated antisymmetric constant offsets, so the paper's strongest claims are not yet fully supported.

major comments (2)

[Supplementary Section 5 (final paragraph)]
[Control and extension of the generic zero-field SDE (fourth paragraph)]

minor comments (5)

[Abstract and Discussion]
[Supplementary Section 6]
[Supplementary Section 1]
[References]
[Figures 3 and 4]

Circularity Check

1 steps flagged · score 3.0 of 10

Uncalibrated antisymmetric offset subtraction shifts plotted ΔIC by up to 0.7 nA, weakening the null and polarity controls; dVPG scaling remains independent.

other [Supplementary Information Sec. 5, final paragraph; applied to Figs. 3d-i, 4, Supp. Figs. 3e,7,8]
"Also, we note that all the original IC+(VPG) (and IC-(VPG)) in Fig. 3d,e,g and all plots in Fig. 4 and Supplementary Figs. 7,8 have been subtracted by a small constant offset of -0.35 nA (and +0.35 nA) independent of RL and IC configurations. The original IC+(VPG) (and IC-(VPG)) in Fig. 3i has been subtracted by an offset of -0.05 nA (and +0.05 nA). The original IC+(VPG) (and IC-(VPG)) in Supplementary Fig. 3e has been subtracted by an offset of -0.23 nA (and +0.23 nA). Such small and constant offset is not due to the SDE."

The offset correction shifts the plotted asymmetry by a constant: with −0.35 nA on IC+ and +0.35 nA on |IC−|, ΔIC_plot = ΔIC_raw + 0.70 nA (and ±0.10, ±0.46 nA for Fig. 3i and Supp. Fig. 3e). The SDE/null traces are thus not raw observables: an antisymmetric constant of exactly the form of a constant SDE is added to ΔIC and then asserted, without independent calibration or raw traces, to be 'not due to the SDE.' The offset value changes between configurations (0.35, 0.05, 0.23 nA), so the correction is effectively adjusted per dataset; the ground-swap polarity reversal and symmetric-bias null do not independently exclude a contact/measurement offset of the same magnitude. dVPG extraction is insensitive to vertical offsets and supplies separate support.

full rationale

The derivation chain is mostly self-contained: the proposed mechanism is a circuit-level electrostatic shift, and the main supportive observations (dVPG increasing with |ICRL|, polarity reversal upon swapping the grounded contact, even-in-B behavior, sweep-order independence) are external controls rather than fits to the target observable. I find no load-bearing self-citation: Ref. 4 (Hu-Wu-Dai) is a legitimate external theory paper despite an overlapping author, and other self-references are not used to justify the central mechanism. The one concerning step is the uncalibrated antisymmetric offset subtraction in Supplementary Section 5. The plotted ΔIC values used for the Fig. 3i null and for efficiency/polarity magnitudes are shifted by a constant (0.70 nA in the main control data) whose sign and magnitude coincide with a spurious constant SDE; the paper's only justification is the assertion that the offset is 'not due to the SDE,' with no independent calibration or raw traces. Because the offset values differ across configurations, this correction has the structure of an adjusted parameter. However, the dVPG-versus-|ICRL| correlation and the sign change of dVPG under contact swap are unaffected by constant vertical offsets, so the central claim retains independent quantitative support. On balance the circularity is partial and concentrated in the null/polarity controls, not in the dVPG scaling.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claim rests on the CPT model (EC, EJ fitted) and on the assumed equivalence between line-resistance voltage drop and gate-voltage shift. The ad hoc antisymmetric offsets are the most concerning free parameters because they are introduced at the data-analysis stage and directly alter the measured SDE.

free parameters (5)

Charging energy EC = D1: 41 μeV (IC fit) / 34 μeV (Coulomb diamond); D2: 11 μeV; D3: 20-21 μeV
Extracted from fits to IC(VPG) and Coulomb diamond measurements; enters the CPT Hamiltonian used to model IC(VPG), so the predicted response to chemical potential shift depends on it.
Josephson energy EJ = D1: 80 μeV
Extracted from IC(VPG) fit (Supp Fig. 9b); sets the magnitude of IC and the sensitivity of IC to gate shift.
Antisymmetric current offsets (IC+/IC-) = -0.35/+0.35 nA (Fig. 3d,e,g; Fig. 4); -0.05/+0.05 nA (Fig. 3i); -0.23/+0.23 nA (Supp Fig. 3e)
Constant offsets subtracted from the two critical-current branches. Because the signs are opposite, they directly change ΔIC by 0.1-0.7 nA and can create or mask SDE; no independent calibration is provided.
Gate lever arm (implicit) = Not measured; assumed for dVPG vs |ICRL| comparison
The conversion from chemical potential shift to the observed gate shift dVPG requires the lever arm α = Cg/CΣ. The paper compares dVPG directly to |ICRL| without reporting α, so the quantitative agreement is not established.
Iterative model constant k = 0.2 (illustrative)
In Supp Fig. 9d, k=0.2 is chosen by hand to illustrate the tilt in IC(VPG); it is not fitted to data.

assumptions (5)

standard math Cooper-pair box Hamiltonian H = 4EC(n-ng/2)^2 - EJ cos(theta-phi/2) - EJ cos(theta+phi/2) describes the CPT (Supp Eq. S1)
Invoked in Supp Sec. 6 to compute IC(VPG); standard model for Cooper-pair transistors.
domain assumption At base temperature only the ground state contributes to supercurrent (f(E0)≈1, f(En>0)≈0)
Used in Supp Sec. 6 to compute IC from ground-state energy dispersion.
domain assumption The island chemical potential shifts by -|e|IDCRL when D is grounded via RL, and this acts equivalently to a gate-voltage shift
Central mechanism introduced in Fig. 1a,b and used throughout; the equivalence between the voltage shift and the gate shift is asserted rather than derived from the device electrostatics.
domain assumption Line resistance connected to S (not to ground) does not affect the device chemical potential
Stated in Fig. 3c,f; needed so that only the grounded-side RL matters.
domain assumption Even-parity Cooper-pair regime holds for the CPTs (no quasiparticle poisoning)
Supp Sec. 7 confirms even parity from Coulomb diamond periodicity; if odd-parity states contributed significantly, the IC(VPG) response and the diode effect could change.

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Cite this review

Pith. "Pith review of Circuit-level-configurable Zero-field Superconducting Diodes: A Universal Platform Beyond Intrinsic Symmetry Breaking." pith.science (2026). https://pith.science/paper/KYO422AO

@misc{pith2026250518330,
  author       = {Pith},
  title        = {Pith review of: Circuit-level-configurable Zero-field Superconducting Diodes: A Universal Platform Beyond Intrinsic Symmetry Breaking},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KYO422AO}},
  note         = {Machine review of arXiv:2505.18330}
}

read the original abstract

Modern industry seeks next-generation microelectronics with ultra-low dissipation and noise beyond semiconducting systems, where the superconducting electronics offer promise. Its physical foundation is the superconducting diode effect (SDE) with nonreciprocal supercurrent. SDE has hitherto mainly relied on material-specific intrinsic symmetry breaking in superconductors, suffering from low yield, controllability, and compatibility with further functional extension - an undesirable aspect for applications. Here, we demonstrated a field-free SDE due to the chemical potential shift from external circuit line resistance, which is generic and challenges the previous interpretations of the intrinsic symmetry breaking in superconductivity for zero-field SDE. Moreover, this SDE is circuit-level configurable since it can be electrically switched on/off with its polarity and efficiency precisely modulated via gate voltage and circuit reconfiguration, facilitating functional extension. Such a generic, controllable and extensible SDE addresses critical challenges in dissipationless circuit towards application, and thus establishes a robust platform for scalable superconducting electronics.

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

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Reference graph

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

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work page 2024

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