Hardware-Adaptive and Superlinear-Capacity Memristor-based Associative Memory

Can Li; Chengping He; Giacomo Pedretti; Jim Ignowski; Keyi Shan; Mingrui Jiang; Shengbo Wang; Szu-Hao Yang; Zefan Li

REVIEW 4 major objections 6 minor 35 references

Hardware-Adaptive and Superlinear-Capacity Memristor-based Associative Memory

T0 review · 4 major / 6 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read A hardware-adaptive training rule triples defect-ridden memristor memory capacity and gives Hopfield networks superlinear storage scaling.

desk verdict Real hardware, adaptive training, and credible small-scale retrieval, but the superlinear-capacity exponents are empirical fits that need baselines and basin-size analysis before they carry the load. read the letter →

arxiv 2505.12960 v1 pith:LY6U2KJ7 submitted 2025-05-19 cs.LG cs.AIcs.ET

Chengping He , Mingrui Jiang , Keyi Shan , Szu-Hao Yang , Zefan Li , Shengbo Wang , Giacomo Pedretti , Jim Ignowski

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Can Li

This is my paper · ORCID

classification cs.LGcs.AIcs.ET

keywords associativememoryHopfieldnetworkmemristorcrossbarhardware-adaptivetrainingstuck-at-faulttolerancemultilayerrecurrentcontinuouspatternscapacityscaling

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that associative memory in memristor hardware stops being fragile and capacity-limited once the Hopfield network weights are trained by gradient descent on a fixed-point objective that is calibrated to the actual device array. The same training rule, extended to a network with a hidden layer, makes storage capacity grow superlinearly with neuron count for correlated patterns and lets the memory store continuous-valued patterns, which classical sign-activation Hopfield networks cannot. If correct, memristor-based associative memories become practical for pattern completion under hardware faults, with much higher capacity per device and flexible capacity tuning by choosing hidden-layer size. The claims are backed by experiments on integrated 64x64 memristor crossbars.

What carries the argument

The load-bearing object is the fixed-point training objective. At a stored fixed point, $X = \mathrm{sgn}(WX+b)$; replacing sgn by tanh makes the objective differentiable, so gradient descent can drive every stored pattern toward being a fixed point while respecting a mask of stuck-at-fault devices in the crossbar model. In the multilayer version the same loss is applied to the full two-layer map $f(\xi^m)$, and the hidden layer acts as a data compressor, which is what the paper credits for superlinear capacity and continuous-pattern support.

What would settle it

Retrieve a pattern from the trained multilayer network while increasing the corruption rate from 5% to 40% pixel flips; if retrieval accuracy collapses at corruption rates where the single-layer network still succeeds, the superlinear-capacity claim would not correspond to robust associative recall. A second check is to measure whether every stored pattern is still a fixed point after applying the measured conductance variation ($\sigma \approx 3.9\,\mu\text{S}$), since the training loss only guarantees fixed points at the converged target weights.

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Extended reading notes

Core claim

The paper's central claim is that a Hopfield network can be made hardware-adaptive by treating associative-memory storage as an optimization problem: minimize the squared distance between each stored pattern and its relaxed one-step update, $\tanh(W\xi^m+b)$, instead of using Hebbian or pseudo-inverse weight formulas. Because the objective is differentiable, the weights can be trained with gradient descent through a crossbar model that masks stuck-at-fault devices, so the remaining devices compensate for the broken ones. The paper further claims that the same loss, applied to a two-layer recurrent network with a hidden layer whose output feeds back, gives a system whose capacity scales as $\propto N^{1.49}$ for correlated binary patterns and $\propto N^{1.74}$ for continuous patterns, versus roughly linear scaling for single-layer Hopfield networks, and that synchronous updates on memristor hardware cut energy and latency dramatically.

Load-bearing premise

The argument assumes that patterns made into fixed points by the squared-distance loss also have large enough basins of attraction that corrupted inputs converge back to them, and this is not proven for the multilayer dynamics with asymmetric weights and synchronous updates.

Editorial extensions

If this is right

Storing patterns in a memristor Hopfield network no longer requires fault-free or precisely programmed devices; the training loop compensates for stuck-at-fault locations, and the paper reports triple the capacity of the pseudo-inverse baseline when 50% of devices are stuck.
Adding one hidden layer with the same synapse count turns the capacity scaling from linear to superlinear ($\propto N^{1.49}$ on correlated MNIST binary patterns), so larger memories need not demand quadratically more devices for the same pattern size.
Continuous-valued patterns become storable and retrievable through the multilayer tanh dynamics, with capacity scaling $\propto N^{1.74}$, a capability conventional sign-based Hopfield networks lack.
Capacity can be tuned by changing hidden-neuron count at fixed input dimension, and the hidden layer reduces required memristors by 43.7% to 95% for small pattern sets.
Synchronous updates exploit memristor parallelism, cutting latency by up to 99.7% and improving energy efficiency by up to 8.8x compared with asynchronous update schemes reported earlier.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The mechanism suggests that any compute-in-memory substrate whose non-idealities can be modelled, not just oxide memristors, could inherit the same defect tolerance, since the training objective is substrate-agnostic once a mask is available.
Because training enforces only clean-pattern fixed points, the reported capacity numbers likely depend on the corruption level used to define 'retrievable'; a testable extension would be to include noisy or partial patterns in the loss and measure whether basin size increases.
The superlinear exponent appears tied to pattern correlation: the paper itself reports a much weaker advantage ($\propto N^{1.11}$ vs $\propto N^{1.06}$) for random patterns, so the practical gain depends on how structured the stored data are; applying the same architecture to other correlated datasets would probe that dependence.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague,

The short version: this is a genuine hardware paper with a working integrated memristor Hopfield system, and the hardware-adaptive training with stuck-at-fault masking is a real step forward. But the headline "superlinear capacity" is an empirical power-law fit from simulations, not a derived result, and the paper never compares against the dense Hopfield models that already give superlinear or exponential capacity in software.

What is genuinely new: they train HNN weights by minimizing a fixed-point loss (Eq. 5) on clean patterns, using a calibrated crossbar model that masks known stuck-at faults, then deploy the weights on a real CMOS-integrated 64x64 memristor array. The small-scale retrieval experiments look credible: 10% flips recover stored MNIST patterns within a few synchronous iterations, conductance maps match targets, and they quantify programming noise. The multilayer extension is a nice engineering trick: a bottleneck hidden layer gives higher capacity on correlated patterns with fewer memristors, and they show continuous-pattern recall on hardware. The synchronous-update latency and energy numbers are striking (99%+ latency reduction), though these are estimates for a 64-neuron system, not measured at scale.

The soft spots are concentrated where the abstract oversells. The exponents (∝N^1.49, ∝N^1.74) are fitted to a few points on MNIST with no confidence intervals, and there is no comparison to dense Hopfield networks—whose papers they cite but never bench against. The training objective only enforces clean patterns as fixed points; it does not train on corrupted inputs or analyze basins of attraction. Since capacity is measured at one noise level (5% bit flips; Gaussian σ=0.6) with a cosine >0.99 threshold, we don't know whether basins shrink as N or pattern count grows. For the single-layer case, capacity is still linear (2x better than pseudo-inverse), which is honest; the superlinear multiplier comes entirely from multilayer compression and only shows on correlated MNIST. Also, the stuck-at-fault handling is underspecified: they mask fault locations to zero weights in the model, but a real stuck device would contribute a nonzero conductance. Maybe they only used devices stuck at zero; the text doesn't say.

None of this kills the paper. The hardware demonstration stands on its own. But the capacity claims need dense-Hopfield baselines, error bars, and some discussion of basins before they can be taken as architectural laws rather than fitting curves.

I think this deserves serious peer review. The experiments are there, code is public, and the adaptive-training idea is worth careful attention. A conditional accept with requests for baselines, error bars, and basin analysis would be the right outcome.

Referee Report

4 major / 6 minor

Summary. The paper proposes a hardware-adaptive learning algorithm for memristor-based Hopfield networks (HNNs) for associative memory. Instead of using a fixed rule such as Hebbian or pseudo-inverse learning, the method trains the weights by gradient descent to make each stored pattern a stable fixed point under the recurrent update, using a tanh surrogate for the sign nonlinearity and a hardware-calibrated crossbar model that masks stuck-at-fault devices. The authors extend the approach to a two-layer recurrent architecture and demonstrate retrieval of binarized MNIST patterns on an integrated 64x64 memristor crossbar, with additional simulations of larger networks. They report that the method roughly triples capacity relative to a pseudo-inverse baseline at 50% stuck-at faults, and that the multilayer extension gives capacity scaling approximately proportional to N^1.49 for binary MNIST and N^1.74 for continuous MNIST patterns, versus roughly linear scaling for single-layer HNNs. The paper also reports energy and latency advantages of synchronous updates over asynchronous updates.

Significance. If the claims hold, this would be a useful engineering advance for memristor-based associative memory: it combines defect-aware training, multilayer recurrent architectures, continuous-valued patterns, and hardware demonstrations on an integrated crossbar. The paper includes a hardware prototype, open code, and comparisons against several classical learning rules, which are strengths. However, the central capacity and fault-tolerance claims are empirical power-law fits and hardware-model simulations rather than derived guarantees, and no comparison is made with modern dense associative memory models that already achieve superlinear or exponential capacity, so the novelty and robustness of the 'superlinear capacity' claim remain uncertain..

major comments (4)

[Hardware-Adaptive Learning Algorithm; Pattern Retrieval Experiment (Eqs. 5-6, Fig. 3i-3j)] The training objective in Eqs. (5)-(6) enforces only that each stored pattern is approximately a fixed point; it contains no term for corrupted inputs, and the paper provides no analysis of basin size, convergence, or possible limit cycles for the synchronous, asymmetric-weight recurrent dynamics. Capacity is defined at a single operating point (5% random bit flips for binary patterns, Gaussian noise with sigma=0.6 for continuous patterns, cosine similarity >0.99), so the fitted power-law exponents may overstate useful associative memory capacity if basins shrink or oscillations appear as N or the number of stored patterns grows. This is load-bearing for the abstract's central claims, and I ask the authors to report capacity as a function of noise level, verify convergence at and beyond the claimed capacity limits, and either provide a theoretical convergence/basin argument or clearly frame the results as empirical with these caveats.
[Fig. 4(f), Fig. 5(f); Results on capacity scaling] The scaling exponents 1.49, 1.74, 1.06, and related values are fitted power-law exponents, but the manuscript reports no confidence intervals, no goodness-of-fit statistics, and no model comparison against, e.g., logarithmic or sublinear alternatives. The fits appear to be based on a small number of input sizes, and for MNIST the correlation structure of the patterns changes with resolution/preprocessing, so the comparison between single-layer and multilayer exponents may reflect the dataset rather than an architectural property. Please provide the raw capacity data for all points, error bars from repeated experiments, fitted exponents with uncertainties, and a sensitivity analysis with respect to the capacity threshold.
[Introduction and Discussion; related work (Refs. 9,10)] The paper claims superlinear capacity scaling as a central contribution, but it does not compare against dense associative memory models or modern Hopfield networks, which in the cited literature already achieve superlinear or exponential storage capacity. Because the claim is framed as a fundamental improvement over 'previous HNNs' rather than over classical Hebbian/pseudo-inverse rules, the absence of such a comparison leaves the novelty and significance of the capacity result unclear. I ask for a quantitative comparison under the same capacity metric and hardware constraints, or, failing that, a clearly scoped statement that the comparison is only against classical single-layer Hopfield networks.
[Methods: Hardware-Adaptive Training Algorithm; Fig. 3(h-j)] The fault-tolerance experiments model stuck-at-fault devices by setting the corresponding weights to zero during training, but a physical memristor stuck-at-fault is typically a stuck-on or stuck-off conductance, not a zero weight. Unless the differential-pair encoding or readout scheme makes a stuck device equivalent to a zero contribution, the claimed 3x effective capacity under 50% device faults may not transfer to actual hardware faults. The manuscript should either clarify the mapping, demonstrate fault injection with realistic stuck-on/stuck-off conductances, or explicitly restrict the claim to zero-conductance faults.

minor comments (6)

[Heading 'Continuous Patterns associative Memory'] The heading contains a typo: 'multiplayer network' should be 'multilayer network'.
[Methods: Memristor Integration] The word 'periphral' appears in the first sentence of the Methods section and should be corrected to 'peripheral'.
[Eqs. (3)-(5)] Equation (3) includes a bias term b, but Eq. (5) omits it; please clarify whether the bias is trained and included in the hardware mapping or intentionally set to zero.
[Fig. 3(i,j) and capacity measurements] The figure captions and text do not clearly state which capacity curves are from physical hardware measurements and which are from the calibrated crossbar model; this distinction should be explicit in the captions and main text.
[Eq. (4) and Methods] The tanh steepness parameter lambda is set to 1 without a sensitivity analysis; because the loss landscape and fixed-point accuracy may depend on lambda, a short study of its effect would strengthen the method's robustness claims.
[Fig. 3(e) and capacity definition] The text says corrupted inputs are generated by flipping 10% of pixels in the demonstration, while the capacity metric uses 5% flips; please clarify that these are different protocols and motivate the choice of 5% for capacity measurements.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: capacity and scaling claims are empirical, not derived by construction from the training loss.

full rationale

The paper's training objective, Eqs. (5)-(6), minimizes the distance between each stored pattern and the network output on that clean pattern, which does make stored patterns fixed points by construction. However, the reported capacity metric is deliberately stricter than the training objective: it requires retrieval with cosine similarity above 0.99 from inputs corrupted by 5% bit flips (binary) or Gaussian noise with σ=0.6 (continuous). Success on corrupted inputs requires basin-of-attraction behavior that is not guaranteed by the fixed-point loss, so the capacity numbers are not mathematically forced by the training objective. The scaling exponents (∝N^1.49, ∝N^1.74, etc.) are fitted slopes describing measured capacity-versus-size curves, not quantities predicted from the equations, so they are empirical characterizations rather than circular reductions. The comparisons against pseudo-inverse, Hebbian, Storkey, and equilibrium-propagation baselines use the same fault masks and success criteria, making the comparison meaningful. The hardware-calibrated crossbar model from Ref. [45] is a self-citation by some of the authors, but it is an experimentally validated external tool used to account for device non-idealities; it is not invoked as the proof of the capacity or superlinear-scaling claims. No equation in the paper is shown to equal another by construction, and no fitted parameter is renamed as a prediction. Thus the manuscript does not exhibit the specific reduction patterns that would constitute circularity.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The model rests on the standard Hopfield fixed-point condition plus the untested assumption that fixed-point training yields large basins. The capacity thresholds, corruption levels, hidden ratio, and training hyperparameters are chosen by the authors and affect the reported exponents. No new physical entities are introduced.

free parameters (5)

λ (tanh steepness) = 1
Set by hand in Eq. 4; controls relaxation of sign and can affect basins and capacity.
capacity threshold (cosine similarity) = 0.99
Capacity is defined as max patterns retrievable with cosine similarity >0.99; exponents depend on this threshold.
corruption level for capacity tests = 5% pixel flips; Gaussian σ=0.6
Basin-of-attraction definition depends on input corruption level; changing it would change measured capacity.
hidden neuron ratio in scaling runs = N_h = N/2
Chosen so multilayer uses same synapse count as single layer; scaling exponents depend on hidden width.
training hyperparameters = lr 3e-2/3e-4; 10k/60k steps; loss 1e-8
Training details from Methods; capacity results may depend on these choices.

assumptions (5)

standard math Stored patterns should be fixed points X = sgn(WX + b) of the update rule.
Standard Hopfield condition used to define loss in Eq. (3).
domain assumption tanh(λ(WX+b)) with λ=1 is a sufficient surrogate for sgn during training.
Eqs. (4)-(5) replace sign with tanh; no bound is given for how well a tanh fixed point survives the sign update.
ad hoc to paper Minimizing fixed-point loss on clean patterns creates useful basins of attraction for corrupted inputs.
Nothing in Eqs. (5)-(6) enforces basin width; retrieval quality is only demonstrated empirically.
domain assumption Synchronous updates of the trained multilayer network converge to stored attractors.
No Lyapunov function for trained asymmetric multilayer weights; convergence is observed for tested cases.
domain assumption Power-law scaling extrapolates beyond the tested neuron counts.
Exponents fit over limited N range with no saturation analysis.

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Pith. "Pith review of Hardware-Adaptive and Superlinear-Capacity Memristor-based Associative Memory." pith.science (2026). https://pith.science/paper/LY6U2KJ7

@misc{pith2026250512960,
  author       = {Pith},
  title        = {Pith review of: Hardware-Adaptive and Superlinear-Capacity Memristor-based Associative Memory},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LY6U2KJ7}},
  note         = {Machine review of arXiv:2505.12960}
}

abstract

Brain-inspired computing aims to mimic cognitive functions like associative memory, the ability to recall complete patterns from partial cues. Memristor technology offers promising hardware for such neuromorphic systems due to its potential for efficient in-memory analog computing. Hopfield Neural Networks (HNNs) are a classic model for associative memory, but implementations on conventional hardware suffer from efficiency bottlenecks, while prior memristor-based HNNs faced challenges with vulnerability to hardware defects due to offline training, limited storage capacity, and difficulty processing analog patterns. Here we introduce and experimentally demonstrate on integrated memristor hardware a new hardware-adaptive learning algorithm for associative memories that significantly improves defect tolerance and capacity, and naturally extends to scalable multilayer architectures capable of handling both binary and continuous patterns. Our approach achieves 3x effective capacity under 50% device faults compared to state-of-the-art methods. Furthermore, its extension to multilayer architectures enables superlinear capacity scaling (\(\propto N^{1.49}\ for binary patterns) and effective recalling of continuous patterns (\propto N^{1.74}\ scaling), as compared to linear capacity scaling for previous HNNs. It also provides flexibility to adjust capacity by tuning hidden neurons for the same-sized patterns. By leveraging the massive parallelism of the hardware enabled by synchronous updates, it reduces energy by 8.8x and latency by 99.7% for 64-dimensional patterns over asynchronous schemes, with greater improvements at scale. This promises the development of more reliable memristor-based associative memory systems and enables new applications research due to the significantly improved capacity, efficiency, and flexibility.

Figures

Figures reproduced from arXiv: 2505.12960 by the authors.

**Figure 1.** Key concepts of our high-capacity memristor-based associative memory enabled by hardware-adaptive learning: (a) Associative memory in the human brain and implemented by Hopfield neural networks (HNN). The human brain’s associative memory retrieves complete information from incomplete inputs. Similarly, an artificial HNN can recover stored patterns from corrupted or partial inputs. (b) A schematic showing the digital… view at source ↗

**Figure 2.** Integrated memristor hardware for associative memory experiments : (a) Photo of our memristor-based associative memory system, comprising our integrated memristor chip, a power supply, a microcontroller, and peripheral circuitry for troubleshooting. (b) The layout of our integrated memristor chip with three 64 × 64 crossbar arrays alongside fully integrated peripheral circuits—including transimpedance amplifiers (TI… view at source ↗

**Figure 3.** Experimental demonstration of adaptive learning algorithm for single-layer HNN and performance analysis (a) Schematic illustration of the adaptive training and pattern retrieval process of our memristor-based associative memory system. A physics-based crossbar model is used to train the synaptic weights, where the device non-idealities, such as stuck-at-fault devices for that particular hardware, are taken into cons… view at source ↗

Figures from the paper (3 more)

**Figure 4.** Figure 4: Associative memory implemented with multilayer structure: (a) Schematic of the Hopfield Neural Network (HNN) for associative memory with a traditional one-layer fully-connected structure and the multilayer structure enabled by our adaptive learning method. (b) Experime…

**Figure 5.** Figure 5: Continuous patterns associative memory enabled by adaptive learning and multiplayer network: (a) Schematic comparison between conventional HNN that supports only binary patterns and the multilayer associative memory with adaptive learning proposed in this work that sup…

**Figure 6.** Figure 6: Performance Benchmarks: (a) The typical mean and standard deviation of the programming error between the target conductance (ranging from 0 to 150 µS) and the actual readout conductance from our integrated memristor crossbar. (b) Simulation results showing the impact o…

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Works this paper leans on

35 extracted references · 33 canonical work pages

[2]

& Sun, J

He, K., Zhang, X., Ren, S. & Sun, J. Deep residual learning for image recognition. InProceedings of the IEEE conference on computer vision and pattern recognition, 770–778 (2016). 3.Vaswani, A.et al.Attention is all you need.Adv. neural information processing systems30(2017)

work page 2016
[4]

Pavlov, P. I. Conditioned reflexes: an investigation of the physiological activity of the cerebral cortex.Annals neurosciences 17, 136 (2010)

work page 2010
[5]

Hopfield, J. J. Neural networks and physical systems with emergent collective computational abilities.Proc. national academy sciences79, 2554–2558 (1982)

work page 1982
[6]

Hopfield, J. J. Neurons with graded response have collective computational properties like those of two-state neurons. Proc. national academy sciences81, 3088–3092 (1984)

work page 1984
[7]

Hopfield, J. J. & Tank, D. W. “neural” computation of decisions in optimization problems.Biol. cybernetics52, 141–152 (1985). 8.Hopfield, J. J. & Tank, D. W. Computing with neural circuits: A model.Science233, 625–633 (1986)

work page 1985
[9]

& Hopfield, J

Krotov, D. & Hopfield, J. J. Dense associative memory for pattern recognition.Adv. neural information processing systems 29(2016)

work page 2016
[10]

& Vermet, F

Demircigil, M., Heusel, J., Löwe, M., Upgang, S. & Vermet, F. On a model of associative memory with huge storage capacity.J. Stat. Phys.168, 288–299 (2017). 17/20 11.Krotov, D. A new frontier for hopfield networks.Nat. Rev. Phys.5, 366–367 (2023)

work page 2017
[12]

& Dixon, A

Goto, H., Tatsumura, K. & Dixon, A. R. Combinatorial optimization by simulating adiabatic bifurcations in nonlinear hamiltonian systems.Sci. advances5, eaav2372 (2019). 13.Strukov, D. B., Snider, G. S., Stewart, D. R. & Williams, R. S. The missing memristor found.nature453, 80–83 (2008). 14.Rao, M.et al.Thousands of conductance levels in memristors integr...

work page 2019

Show all 35 references

[20]

Wang, Z.et al.In situ training of feed-forward and recurrent convolutional memristor networks.Nat. Mach. Intell.1, 434–442 (2019)

2019
[21]

Ambrogio, S.et al.Equivalent-accuracy accelerated neural-network training using analogue memory.Nature558, 60–67 (2018)

2018
[22]

23.Wan, W.et al.A compute-in-memory chip based on resistive random-access memory.Nature608, 504–512 (2022)

Ambrogio, S.et al.An analog-ai chip for energy-efficient speech recognition and transcription.Nature620, 768–775 (2023). 23.Wan, W.et al.A compute-in-memory chip based on resistive random-access memory.Nature608, 504–512 (2022)

2023
[24]

A., Strachan, J

Zidan, M. A., Strachan, J. P. & Lu, W. D. The future of electronics based on memristive systems.Nat. electronics1, 22–29 (2018). 25.Yao, P.et al.Fully hardware-implemented memristor convolutional neural network.Nature577, 641–646 (2020)

2018
[26]

Commun.15, 1132 (2024)

Feng, Y .et al.Memristor-based storage system with convolutional autoencoder-based image compression network.Nat. Commun.15, 1132 (2024)

2024
[27]

Jiang, M., Shan, K., He, C. & Li, C. Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar.Nat. Commun.14, 5927 (2023)

2023
[28]

Electron.3, 409–418 (2020)

Cai, F.et al.Power-efficient combinatorial optimization using intrinsic noise in memristor hopfield neural networks.Nat. Electron.3, 409–418 (2020)

2020
[29]

advances6, eaba9901 (2020)

Yang, K.et al.Transiently chaotic simulated annealing based on intrinsic nonlinearity of memristors for efficient solution of optimization problems.Sci. advances6, eaba9901 (2020). 30.Zidan, M. A.et al.A general memristor-based partial differential equation solver.Nat. Electro...

2020
[32]

Electron.1, 548–554 (2018)

Jiang, H.et al.A provable key destruction scheme based on memristive crossbar arrays.Nat. Electron.1, 548–554 (2018)

2018
[33]

Wang, Z., Wu, Y ., Park, Y . & Lu, W. D. Safe, secure and trustworthy compute-in-memory accelerators.Nat. Electron. 1–12 (2024). 18/20

2024
[34]

B.et al.Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Eryilmaz, S. B.et al.Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array. Front. neuroscience8, 205 (2014)

2014
[35]

& Sun, Z

Li, Y ., Wang, S., Yang, K., Yang, Y . & Sun, Z. An emergent attractor network in a passive resistive switching circuit.Nat. Commun.15, 7683 (2024)

2024
[36]

& Yang, Y

Wang, Y ., Yu, L., Wu, S., Huang, R. & Yang, Y . Memristor-based biologically plausible memory based on discrete and continuous attractor networks for neuromorphic systems.Adv. Intell. Syst.2, 2000001 (2020)

2020
[37]

Electron

Yan, M.et al.Ferroelectric synaptic transistor network for associative memory.Adv. Electron. Mater.7, 2001276 (2021)

2021
[38]

communications6, 7522 (2015)

Hu, S.et al.Associative memory realized by a reconfigurable memristive hopfield neural network.Nat. communications6, 7522 (2015)

2015
[39]

Zhou, Y .et al.Associative memory for image recovery with a high-performance memristor array.Adv. Funct. Mater.29, 1900155 (2019)

2019
[40]

on Explor

Pedretti, G.et al.A spiking recurrent neural network with phase-change memory neurons and synapses for the accelerated solution of constraint satisfaction problems.IEEE J. on Explor. Solid-State Comput. Devices Circuits6, 89–97 (2020). 41.Do, H. The organization of behavior.Ne...

2020
[42]

Storkey, A. J. & Valabregue, R. The basins of attraction of a new hopfield learning rule.Neural Networks12, 869–876 (1999). 43.Kanter, I. & Sompolinsky, H. Associative recall of memory without errors.Phys. Rev. A35, 380 (1987)

1999
[44]

& Manton, J

Tolmachev, P. & Manton, J. H. New insights on learning rules for hopfield networks: Memory and objective function minimisation. In2020 International Joint Conference on Neural Networks (IJCNN), 1–8 (IEEE, 2020)

2020
[45]

Mao, R., Wen, B., Jiang, M., Chen, J. & Li, C. Experimentally-validated crossbar model for defect-aware training of neural networks.IEEE Transactions on Circuits Syst. II: Express Briefs69, 2468–2472 (2022)

2022
[46]

electronic materials5, 1800876 (2019)

Sheng, X.et al.Low-conductance and multilevel cmos-integrated nanoscale oxide memristors.Adv. electronic materials5, 1800876 (2019)

2019
[47]

& Corinto, F

Zoppo, G., Marrone, F. & Corinto, F. Equilibrium propagation for memristor-based recurrent neural networks.Front. neuroscience14, 501774 (2020)

2020
[48]

D., Williams, R

Yi, S.-i., Kendall, J. D., Williams, R. S. & Kumar, S. Activity-difference training of deep neural networks using memristor crossbars.Nat. Electron.6, 45–51 (2023)

2023
[49]

& Cohen, N

McCloskey, M. & Cohen, N. J. Catastrophic interference in connectionist networks: The sequential learning problem. In Psychology of learning and motivation, vol. 24, 109–165 (Elsevier, 1989)

1989
[50]

& McCALLUM, S

Robins, A. & McCALLUM, S. Catastrophic forgetting and the pseudorehearsal solution in hopfield-type networks. Connect. Sci.10, 121–135 (1998)

1998
[51]

Zhang, C., Bengio, S., Hardt, M., Mozer, M. C. & Singer, Y . Identity crisis: Memorization and generalization under extreme overparameterization.arXiv preprint arXiv:1902.04698(2019). 19/20

2019 arXiv
[52]

& Uhler, C

Radhakrishnan, A., Belkin, M. & Uhler, C. Overparameterized neural networks implement associative memory.Proc. Natl. Acad. Sci.117, 27162–27170 (2020). Acknowledgements This work was supported in part by Research Grant Council of Hong Kong SAR (C7003-24Y , 27210321, C1009-22GF...

2020

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.

[1] [2]

& Sun, J

He, K., Zhang, X., Ren, S. & Sun, J. Deep residual learning for image recognition. InProceedings of the IEEE conference on computer vision and pattern recognition, 770–778 (2016). 3.Vaswani, A.et al.Attention is all you need.Adv. neural information processing systems30(2017)

work page 2016

[2] [4]

Pavlov, P. I. Conditioned reflexes: an investigation of the physiological activity of the cerebral cortex.Annals neurosciences 17, 136 (2010)

work page 2010

[3] [5]

Hopfield, J. J. Neural networks and physical systems with emergent collective computational abilities.Proc. national academy sciences79, 2554–2558 (1982)

work page 1982

[4] [6]

Hopfield, J. J. Neurons with graded response have collective computational properties like those of two-state neurons. Proc. national academy sciences81, 3088–3092 (1984)

work page 1984

[5] [7]

Hopfield, J. J. & Tank, D. W. “neural” computation of decisions in optimization problems.Biol. cybernetics52, 141–152 (1985). 8.Hopfield, J. J. & Tank, D. W. Computing with neural circuits: A model.Science233, 625–633 (1986)

work page 1985

[6] [9]

& Hopfield, J

Krotov, D. & Hopfield, J. J. Dense associative memory for pattern recognition.Adv. neural information processing systems 29(2016)

work page 2016

[7] [10]

& Vermet, F

Demircigil, M., Heusel, J., Löwe, M., Upgang, S. & Vermet, F. On a model of associative memory with huge storage capacity.J. Stat. Phys.168, 288–299 (2017). 17/20 11.Krotov, D. A new frontier for hopfield networks.Nat. Rev. Phys.5, 366–367 (2023)

work page 2017

[8] [12]

& Dixon, A

Goto, H., Tatsumura, K. & Dixon, A. R. Combinatorial optimization by simulating adiabatic bifurcations in nonlinear hamiltonian systems.Sci. advances5, eaav2372 (2019). 13.Strukov, D. B., Snider, G. S., Stewart, D. R. & Williams, R. S. The missing memristor found.nature453, 80–83 (2008). 14.Rao, M.et al.Thousands of conductance levels in memristors integr...

work page 2019