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REVIEW 2 major objections 6 minor 51 references

Resynthesizing LDPC encoder matrices with two-sided Hamming descent cuts CNOT counts by over half and raises preparation fidelity after routing.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-07-11 18:57 UTC pith:MBZNY3VC

load-bearing objection Solid, matrix-verified LDPC encoder resynthesis with real gate cuts that mostly survive routing; the layout-free convention is the main caveat, not a collapse of the claim. the 2 major comments →

arxiv 2607.04462 v1 pith:MBZNY3VC submitted 2026-07-05 quant-ph cs.ETcs.ITmath.IT

Noise-Aware Synthesis of Quantum LDPC Encoder Circuits via Two-Sided Hamming Descent

Aditya Sodhani (1) , Keshab K. Parhi (1) ((1) University of Minnesota) This is my paper
classification quant-ph cs.ETcs.ITmath.IT
keywords quantum LDPC codesencoder synthesislinear reversible circuitsCNOT optimizationtwo-sided Hamming descentnoise-aware optimizationBivariate Bicycle codesfault-tolerant quantum computing
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Quantum LDPC codes need a clean encoded starting state, but standard algebraic encoder constructions leave substantial redundant CNOT structure in the linear-reversible block. This paper treats that block as an exact matrix-resynthesis problem and rebuilds it with two-sided Hamming descent: residual matrices are reduced to the identity from both ends, scored by Hamming distance rather than weight, with multistart and a soft depth penalty. Across seventeen CSS encoders the pipeline cuts aggregate CNOT count by 53.8 percent, by up to 68 percent on Bivariate Bicycle codes, and the advantage survives native-graph routing and circuit-level noise. A final live-range schedule further trims idle exposure without adding two-qubit gates. The practical claim is that encoder-matrix resynthesis plus hardware-calibrated selection is a compiler-level lever for higher-fidelity LDPC state preparation.

Core claim

On CSS LDPC encoder matrices, two-sided Hamming descent produces exact equivalent CNOT circuits that are substantially shorter and shallower than Cleve–Gottesman / Sharma–Kumar–Garani constructions and stronger published greedy synthesizers; after commutation-aware re-layering, native routing, noise-aware selection, and live-range scheduling, the gains remain visible in routed gate count, depth, and preparation failure under circuit-level noise.

What carries the argument

Two-sided Hamming descent: reduce a residual matrix A to the identity by row and column transvections scored by exact Hamming-distance change to I, with a soft layer penalty and permutation-conjugation multistart, then verify the assembled circuit implements the original encoder matrix M exactly.

Load-bearing premise

The routed depth and noise advantages assume the final qubit permutation after routing can be absorbed for free by later software relabeling, rather than paying the cost of restoring canonical data and check roles on the chip.

What would settle it

On the four Bivariate Bicycle codes, re-run the biplanar SABRE pipeline while forcing restoration of canonical data/check positions, recompute routed two-qubit depth and Stim preparation-failure rates, and check whether the reported 51–71 percent routed reductions and fidelity gains still hold after that restoration cost.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 6 minor

Summary. The paper formulates CSS LDPC encoder preparation as exact linear-reversible resynthesis of the CNOT block matrix M, and proposes two-sided Hamming descent (row and column transvections scored by Hamming distance to the identity, with a soft layer penalty and multistart under permutation conjugation) inside a six-stage noise-aware pipeline: synthesis, commutation-aware re-layering, count–depth Pareto retention, SABRE routing on code-native Tanner graphs, first-order post-routing selection E = N + κ I_lr, and live-range (ALAP + just-in-time reset) scheduling. On seventeen BB, HGP, and EA QC-LDPC encoders it reports aggregate CNOT reduction from 6310 to 2913 (53.8%, up to 68% on BB), matched-budget gains over published greedy baselines, commutation-aware depths within 1.05–1.17× of a per-circuit lower bound, large routed count/depth reductions on BB-native biplanar connectivity, and lower Stim preparation-failure rates under count-only, full, and routed noise models, with live-range scheduling cutting routed BB failure by up to 13.7% without adding two-qubit gates. Every reported logical circuit is matrix-verified to exact M.

Significance. If the results hold, this is a useful compiler-level contribution for fault-tolerant LDPC stacks: encoder preparation is a first operational step whose noise injects into the initial logical state, and the paper shows that fixed CG/SKG constructions leave substantial removable redundancy on dense structured matrices (especially BB). Strengths that raise the bar for the field include exact-M matrix verification (Alg. 1 Part E; Alg. 2), one-sided ablation, matched-budget head-to-heads against hsum/Hsum/hprod/Hprod and general-purpose tools (PMH, Qiskit-O3, t|ket⟩, PyZX), commutation-aware depth near an explicit lower bound, and Stim failure rates with stated run counts and z-scores on key live-range tests. The combination of two-sided residual search with post-routing noise-aware selection and live-range scheduling is a coherent end-to-end pipeline rather than a count-only synthesizer.

major comments (2)
  1. Section 4.1 and Tables 8, 11, 14: routed depth and routed-noise claims use a layout-free SABRE convention that accepts the final qubit permutation as free software relabeling for downstream syndrome extraction. The manuscript bounds restoration SWAP counts (177 vs 188, 260 vs 259, 330 vs 314, 450 vs 480) and notes that adding them as a worst case still leaves 43.2–50.5% routed-count reduction, but it does not re-report restored-layout depth or Stim failure rates. This is a genuine scope limitation on the hardware half of the central claim. Please either (i) report restored-layout depth and preparation-failure numbers for the BB family, or (ii) state more prominently in the abstract, introduction, and conclusion that routed depth/noise results are layout-free preparation results and that the architecture layer must absorb the permutation for free.
  2. Section 3.4, Eqs. (1)–(2) and Section 4.10: the first-order score E(C;κ)=N+κ I_lr is the selection objective for the noise-aware pipeline, with Pearson correlation 0.90–0.99 to Stim failure rates cited as validation. That correlation is encouraging but is reported only as a range; for a load-bearing selection rule, please report per-code correlations (or a scatter of predicted cost vs measured failure) on the same frontier used for selection, and state explicitly whether any multi-candidate instance selected a different circuit under the propagation-aware refinement than under Eq. (2). Without that, the claim that hardware-calibrated selection (as opposed to count-best + live-range alone) is generally necessary remains only partially quantified outside the single BB[[90,8,10]] 2.4% example in Section 4.12.
minor comments (6)
  1. Abstract and opening: “referred as two-sided Hamming descent” should be “referred to as”; several abstract/intro lines also show missing spaces (“Acrossseveralfamilies”, “can beroutedefficiently”).
  2. Figure 5 caption attributes the depth-greedy baseline to “[28]”; in the text that method is Goubault de Brugière et al. [32]. Align citation numbers.
  3. Table 1 reports ASAP depth in parentheses for “Ours” while later tables switch to commutation-aware depth; a one-line note under Table 1 pointing to Section 2.2 / Table 6 would reduce confusion.
  4. Section 4.3 / Appendix A: PyZX counts include CNOT and CZ while the synthesizer is pure-CNOT; the text already calls this favorable to PyZX, but a column header or footnote in Table 2/16 would make the metric mismatch impossible to miss.
  5. Keywords and Section 1: “commutation-aware scheduling” and “live-range scheduling” are central; ensure both appear in the keyword list for discoverability.
  6. Section 4.9: preparation failure is correctly distinguished from post-decoding logical failure; consider one sentence in the abstract that the fidelity metric is pre-decoding stabilizer-state deviation, so readers do not over-read it as a full FTQC threshold claim.

Circularity Check

0 steps flagged

No significant circularity: empirical algorithmic measurements against fixed algebraic targets M and external baselines, with exact matrix verification.

full rationale

The paper formulates encoder preparation as exact resynthesis of a fixed linear-reversible matrix M extracted from CG/SKG constructions, then reports measured CNOT counts, commutation-aware depths, routed costs, and Stim preparation-failure rates for circuits that are verified to implement exactly that same M (Algorithm 1 Part E; Algorithm 2 matrix and tableau checks). Success is defined by equality to the external algebraic target and by simulation against independent baselines (CG/SKG, PMH, Qiskit-O3, t|ket>, PyZX, published greedy methods of Schaeffer/Perkowski and Goubault de Brugière et al.), not by redefining the objective as the claimed improvement. Multistart under permutation conjugation and the mu-sweep merely select among verified circuits of different count-depth trade-offs; they do not fit a free parameter to the reported reductions. Self-citations to related encoder work by the same authors exist but are not load-bearing for the central empirical claims. No self-definitional loop, fitted-input-as-prediction, uniqueness import, or ansatz smuggling appears in the derivation chain. The layout-free routing convention is a scope limitation on hardware interpretation, not circularity.

Axiom & Free-Parameter Ledger

4 free parameters · 5 axioms · 2 invented entities

This is an algorithmic systems paper: it inherits standard linear algebra over F2 and CSS encoder structure, then adds heuristic search knobs and simplified noise models. The free parameters control search breadth and hardware trade-offs; they are not fitted to invent the gate-count reductions, which are measured after matrix verification. No new physical entities are postulated.

free parameters (4)
  • restart count R = 50
    Number of permutation-conjugation multistarts per mu; set to 50 for main runs and matched baselines.
  • layer penalty mu grid = {0, 0.5, 1, 2, 4, 8, 16}
    Hand-chosen discrete sweep that traces the count–depth Pareto frontier and can change selected circuits.
  • idle-to-gate ratio kappa = 0.1 (primary); swept in {0,0.01,0.03,0.1,0.3,1.0}
    Hardware-calibrated ratio p_idle/p_2q used for post-routing selection and noise experiments; primary tables use kappa=0.1.
  • SABRE seed budget = 10 seeds, opt level 2
    Best-of-ten random seeds at optimization level 2 for routing comparisons.
axioms (5)
  • standard math Any two CNOT circuits implementing the same M in GL(n,F2) realize the same encoder unitary on computational basis states.
    Section 2.1; basis of exact resynthesis and matrix verification.
  • domain assumption CSS LDPC encoders factor as Hadamards on a subset followed by a CNOT block from CG/SKG constructions.
    Introduction and Section 2; scopes the problem to the linear-reversible CNOT block.
  • domain assumption Two CNOTs commute unless the control of one is the target of the other; greedy ASAP under that precedence is an acceptable depth metric.
    Section 3.3; used for commutation-aware depth and lower-bound comparisons.
  • ad hoc to paper First-order preparation cost E = N + kappa I_lr is a useful ranking surrogate for Stim preparation failure under the stated depolarizing/idle models.
    Section 3.4; authors report high correlation but this is a modeling choice, not a theorem.
  • ad hoc to paper Final SABRE qubit permutation can be absorbed by free relabeling for state-preparation evaluation on code-native Tanner graphs.
    Section 4.1 layout convention for routed depth and noise tables.
invented entities (2)
  • two-sided Hamming descent synthesizer no independent evidence
    purpose: Heuristic exact CNOT resynthesis of encoder matrix M via residual reduction from both ends with Hamming-to-identity scoring and layer penalty.
    Core algorithmic contribution; independent evidence is empirical benchmark performance and matrix checks, not an external physical prediction.
  • noise-aware post-routing selection with live-range idle exposure no independent evidence
    purpose: Choose among Pareto candidates after routing using N + kappa I_lr, then ALAP just-in-time reset to cut idle exposure.
    Pipeline stages 5–6; validated only within the paper’s Stim experiments.

pith-pipeline@v1.1.0-grok45 · 35050 in / 3362 out tokens · 36609 ms · 2026-07-11T18:57:50.266273+00:00 · methodology

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Cite this review

Pith. "Pith review of Noise-Aware Synthesis of Quantum LDPC Encoder Circuits via Two-Sided Hamming Descent." pith.science (2026). https://pith.science/paper/MBZNY3VC

@misc{pith2026260704462,
  author       = {Pith},
  title        = {Pith review of: Noise-Aware Synthesis of Quantum LDPC Encoder Circuits via Two-Sided Hamming Descent},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MBZNY3VC}},
  note         = {Machine review of arXiv:2607.04462}
}
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read the original abstract

Quantum low-density parity-check (LDPC) codes are a promising route to fault-tolerant quantum computation, but their use requires efficient preparation of encoded states. Standard encoder constructions generate circuits through fixed algebraic procedures, yet the resulting circuit can contain substantial redundancy. We formulate LDPC encoder preparation as a circuit-resynthesis problem: given the linear-reversible matrix implemented by the encoder's CNOT block, we seek a lower-cost equivalent circuit that can be routed efficiently on the target hardware and which mitigates noise. We propose a novel optimization approach referred as two-sided Hamming descent and a noise-aware optimization pipeline for this task. Across several families of Calderbank-Shor-Steane (CSS) LDPC encoders, including Bivariate Bicycle, hypergraph-product, and entanglement-assisted codes, the proposed pipeline produces substantially smaller and shallower encoder circuits than the standard constructions and the synthesis baselines considered, cutting gate counts by 53.8% in aggregate across the benchmark and by up to 68% on the Bivariate Bicycle family. The gains remain visible after routing, where the two-qubit depth is reduced by up to 71% and translate into higher-fidelity state preparation under circuit-level noise. On the Bivariate Bicycle family, live-range scheduling further reduces routed preparation failure by up to 13.7% without adding two-qubit gates to the selected circuit. These results indicate that encoder-matrix resynthesis, combined with hardware-calibrated selection and scheduling, is an effective compiler-level tool for preparing quantum LDPC code states.

Figures

Figures reproduced from arXiv: 2607.04462 by Aditya Sodhani (1), Keshab K. Parhi (1) ((1) University of Minnesota).

Figure 1
Figure 1. Figure 1: Our six-stage noise-aware encoder pipeline. Hadamard gates applied to a prescribed subset 𝑆 of qubits and 𝐶 is a CNOT circuit. The CNOT block 𝐶 realizes a linear reversible transformation 𝑀 ∈ GL(𝑛, F2). Throughout, 𝑀𝑥 denotes matrix–vector multiplication over F2, and computational-basis strings are ordered as 𝑞0𝑞1 · · · 𝑞𝑛−1. The induced CNOT unitary is 𝑈𝑀 = Í 𝑥∈F 𝑛 2 |𝑀𝑥⟩⟨𝑥|, so 𝑀 determines the action of… view at source ↗
Figure 2
Figure 2. Figure 2: The same matrix 𝑀 = 𝐼 + 𝑒0𝑒 ⊤ 2 on three qubits is realized by CNOT circuits of different length, hence by the same unitary. (a) one gate; (b) three gates. Filled dots are controls, ⊕ targets. q0 q1 q2 q3 (a) Sequence A 5 CNOTs q0 q1 q2 q3 (b) Sequence B 3 CNOTs [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: The same four-qubit matrix 𝑀 is implemented by two CNOT circuits of different gate count, so the shorter one replaces the longer. (a) five gates; (b) three gates. Filled dots are controls, ⊕ targets. state the optimization problem as follows: given the matrix 𝑀 extracted from a CG/SKG encoder, find a short transvection word for 𝑀. 2.2 Circuit cost metrics Beyond word length, we use two hardware-sensitive c… view at source ↗
Figure 4
Figure 4. Figure 4: The two-sided move space reduces the residual 𝐴 to the identity from both ends. Front (column-operation) and back (row-operation) moves act on 𝐴 while maintaining 𝑀 = 𝐿 𝐴𝑅. See Section 3.1. 3.2 Hamming objective, depth penalty, and multistart Algorithm 1 is a single procedure with five visible parts, banner-labeled A through E in the pseudocode, which we walk through in order. Part A: multistart under perm… view at source ↗
Figure 5
Figure 5. Figure 5: Count–depth Pareto frontiers on the four BB codes. The two-sided front (blue, ours) dominates the one-sided ablation front (orange), the depth-greedy method of [32] (green), and the CG/SKG construction (gray) on both count and depth for every BB code. The depth-greedy front is the Pareto-optimal subset of that method’s four cost functions over many restarts [PITH_FULL_IMAGE:figures/full_fig_p018_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: shows the construction. Every CSS LDPC code has such a native coupling map, built the same way from its own 𝐻𝑋 and 𝐻𝑍. This is exactly the connectivity a device needs to measure the code’s stabilizers. Routing the encoder on this graph is therefore the realistic hardware target. The HGP and EA codes do not share the BB biplanar graph, but each has its own native Tanner graph, so we route every HGP and EA e… view at source ↗
Figure 7
Figure 7. Figure 7: Routed two-qubit reductions on the code-native Tanner graphs of the HGP and EA codes. Routed count falls on every code, and routed depth-best falls on ten of thirteen. 21 [PITH_FULL_IMAGE:figures/full_fig_p021_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Preparation-failure rate versus two-qubit depolarizing strength 𝑝 for four representative codes. The synthesized circuits outperform the CG/SKG baselines at every noise level, and the gap approaches the CNOT-count ratio as 𝑝 decreases. proxy. Under this model, depth becomes important because idle layers also contribute errors. Scheduling the count-best circuit at its commutation-aware depth instead of its … view at source ↗
Figure 9
Figure 9. Figure 9: The two pipeline configurations compared here. The count-optimal configuration selects the count-best circuit before routing. The noise-aware configuration routes the frontier, selects the lowest-cost routed candidate, and then applies live-range scheduling. idle exposure in a nonmonotone way. For example, on BB [[144, 12, 12]], the logical count-best circuit routes to 5263 CNOT gates, while a slightly lar… view at source ↗

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