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Bistable Memory Recurrent Units enable ultra-low power analog recurrent neural networks via direct parameter-to-circuit mapping and noise suppression at cell boundaries

2026-06-30 22:18 UTC pith:N76ISPAO

load-bearing objection The paper maps BMRUs to current-mode analog circuits with direct parameter correspondence and 20x boundary noise suppression in 180 nm sims, but the first-quadrant fixed-threshold reformulation's effect on expressivity is asserted without shown verification. the 2 major comments →

arxiv 2605.15216 v3 pith:N76ISPAO submitted 2026-05-12 cs.AR cs.LG

Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations

Arthur Fyon , Julien Brandoit , Loris Mendolia , Damien Ernst , Jean-Michel Redout\'e , Guillaume Drion This is my paper
classification cs.AR cs.LG
keywords analog circuitsrecurrent neural networkslow-power hardwareBistable Memory Recurrent Unitshardware-software co-designnoise suppressionCMOS implementationkeyword spotting
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that Bistable Memory Recurrent Units, RNNs with discrete outputs and hysteretic dynamics, can be mapped to current-mode analog circuits with one-to-one correspondence between learned parameters and circuit elements. This mapping is enabled by reformulating the units for first-quadrant operation with fixed thresholds. Discrete outputs suppress analog noise by at least twentyfold at each boundary, eliminating the accumulation that has blocked recurrent analog designs. Transistor simulations in 180 nm CMOS confirm the software model predicts circuit behavior accurately enough to serve as a simulator. Power analyses show recurrence adds only linear cost while feedforward layers dominate quadratically, supporting sub-microwatt keyword spotting at the RNN core.

Core claim

Bistable Memory Recurrent Units admit an ultra-low power current-mode analog implementation which establishes a one-to-one correspondence between each learned parameter and a circuit element; the discrete outputs suppress analog noise by at least 20-fold at each cell boundary, breaking the noise accumulation that prevents analog recurrence. The reformulation for first-quadrant operation with fixed thresholds preserves expressivity and trainability while enabling the direct correspondence.

What carries the argument

Bistable Memory Recurrent Units reformulated for first-quadrant operation with fixed thresholds, which carry the one-to-one parameter-to-circuit-element mapping and enable noise suppression via discrete outputs

Load-bearing premise

Reformulating BMRUs for first-quadrant operation with fixed thresholds preserves expressivity and trainability while enabling direct hardware mapping

What would settle it

A fabricated 180 nm CMOS circuit implementing recurrent BMRUs that shows noise suppression below 20-fold at cell boundaries or deviates from software predictions in recurrent mode would falsify the claim

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Power cost of adding recurrence scales linearly with state dimension
  • Feedforward layers dominate total power and scale quadratically
  • Recurrence is added at linear marginal cost relative to the feedforward backbone
  • End-to-end keyword spotting achieves sub-microwatt inference at the RNN core
  • Software model serves as high-fidelity low-cost simulator of physical hardware

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The linear marginal cost of recurrence could allow larger state dimensions in always-on sensors without proportional power growth
  • The high-fidelity software simulator could speed iteration on other analog recurrent designs without repeated full transistor simulations
  • Sub-microwatt recurrent cores may extend to continuous biomedical monitoring tasks where temporal dynamics matter
  • The approach of discrete outputs to break noise accumulation might generalize to other hysteretic or threshold-based analog neural units

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 2 minor

Summary. The paper claims that Bistable Memory Recurrent Units (BMRUs) can be reformulated for first-quadrant current-mode operation with fixed thresholds to enable a direct one-to-one mapping from learned parameters to analog circuit elements in 180 nm CMOS. This mapping, combined with discrete hysteretic outputs, is asserted to suppress analog noise by at least 20-fold at cell boundaries, overcoming noise accumulation in recurrent analog computation. Transistor-level simulations demonstrate near-perfect agreement with the software model, which is then used to show linear marginal power cost for adding recurrence (versus quadratic for feedforward layers) and sub-microwatt end-to-end keyword spotting.

Significance. If the reformulation preserves expressivity and trainability without loss, the result would be significant for always-on edge AI: it supplies a concrete hardware-software co-design path to analog recurrence at ultra-low power, with explicit parameter-to-device correspondence and quantitative noise/power scaling data. The near-perfect simulation fidelity and the reproducible large-scale noise/power analyses are explicit strengths that would allow the software model to serve as a low-cost proxy for hardware exploration.

major comments (2)
  1. [Abstract and BMRU reformulation section] Abstract and the BMRU reformulation section: the claim that 'reformulation ... with fixed thresholds [preserves] expressivity and trainability' is stated without quantitative support. No comparison is provided of reachable state-transition functions, training convergence, or benchmark accuracy between the original variable-threshold BMRU and the fixed-threshold first-quadrant version. Because the one-to-one parameter-circuit mapping, the 20-fold noise suppression argument, and the linear power-scaling claim all rest on this equivalence, the absence of such verification is load-bearing.
  2. [Simulation results section] Noise-suppression analysis (simulation results section): the reported 20-fold reduction is obtained from post-reformulation simulations; the text does not derive or bound the suppression factor from the fixed-threshold hysteretic dynamics alone, leaving open whether the factor is an intrinsic property of the reformulated BMRU or an artifact of the particular circuit sizing and input statistics used.
minor comments (2)
  1. [Circuit design section] Notation for currents and thresholds should be unified between the software model equations and the circuit schematic; inconsistent symbols make the claimed one-to-one correspondence harder to verify by inspection.
  2. [Application results] The keyword-spotting benchmark description omits the exact RNN topology (number of BMRU layers, hidden dimension) used for the sub-microwatt claim; adding this would allow direct reproduction of the power numbers.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and for recognizing the potential significance of the BMRU hardware-software co-design. We respond to each major comment below, agreeing that additional quantitative support will strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract and BMRU reformulation section] Abstract and the BMRU reformulation section: the claim that 'reformulation ... with fixed thresholds [preserves] expressivity and trainability' is stated without quantitative support. No comparison is provided of reachable state-transition functions, training convergence, or benchmark accuracy between the original variable-threshold BMRU and the fixed-threshold first-quadrant version. Because the one-to-one parameter-circuit mapping, the 20-fold noise suppression argument, and the linear power-scaling claim all rest on this equivalence, the absence of such verification is load-bearing.

    Authors: We agree that explicit quantitative comparisons are needed to substantiate the preservation of expressivity and trainability under the fixed-threshold reformulation. The reformulation rescales weights and biases to achieve equivalent first-quadrant dynamics while fixing thresholds for circuit mapping. In the revised version we will add a new subsection with side-by-side training convergence curves on standard RNN benchmarks, final test accuracies (including keyword spotting), and a characterization of reachable state-transition functions showing that the fixed-threshold model spans an equivalent functional class via parameter adjustment. revision: yes

  2. Referee: [Simulation results section] Noise-suppression analysis (simulation results section): the reported 20-fold reduction is obtained from post-reformulation simulations; the text does not derive or bound the suppression factor from the fixed-threshold hysteretic dynamics alone, leaving open whether the factor is an intrinsic property of the reformulated BMRU or an artifact of the particular circuit sizing and input statistics used.

    Authors: The 20-fold suppression is measured in transistor-level simulations of the reformulated circuit. The underlying mechanism is the hysteretic snap to discrete stable points, which quantizes noise at each recurrence step. We acknowledge the manuscript lacks an explicit analytical bound independent of sizing. In revision we will derive a lower bound on the suppression factor from the fixed-threshold dynamics alone: for additive Gaussian noise of std. dev. σ and hysteresis separation Δ, the effective noise variance after the threshold is reduced by a factor of at least Δ/(2σ) with high probability, showing the effect is intrinsic to the bistable dynamics (with the concrete 20× value realized by our chosen Δ/σ ratio). revision: yes

Circularity Check

0 steps flagged

No significant circularity; derivation relies on independent simulation validation

full rationale

The paper states a reformulation of BMRUs for first-quadrant fixed-threshold operation and asserts that this preserves expressivity and trainability, but provides no equations reducing any claimed performance metric (noise suppression, power scaling, or one-to-one mapping fidelity) directly to fitted parameters or prior results by construction. Transistor-level simulations in 180 nm CMOS are presented as an external check showing agreement with the software model, and power analyses are derived from those simulations rather than tautologically from the reformulation inputs. No load-bearing self-citations, uniqueness theorems, or ansatzes are exhibited in the text that collapse the central claims to their own definitions.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on the domain assumption that BMRUs possess discrete outputs and hysteretic dynamics that can be directly realized in current-mode analog circuits, plus the modeling choice of fixed thresholds after reformulation; no free parameters or invented entities are explicitly introduced in the abstract.

axioms (2)
  • domain assumption BMRUs constitute a class of RNNs with discrete-valued outputs and hysteretic dynamics that admit direct analog mapping
    Invoked as the foundation for the circuit design and noise-suppression argument.
  • ad hoc to paper Reformulation to first-quadrant operation with fixed thresholds preserves expressivity and trainability
    Required to establish the one-to-one parameter-circuit correspondence.

pith-pipeline@v0.9.1-grok · 5842 in / 1447 out tokens · 33228 ms · 2026-06-30T22:18:58.237621+00:00 · methodology

0 comments
read the original abstract

Always-on AI applications, from environmental sensors to biomedical implants, require ultra-low power consumption. Analog circuits offer a path to sub-microwatt inference, yet existing analog implementations are limited to feedforward architectures: extending them to recurrent dynamics has been considered impractical due to noise accumulation through temporal feedback. We demonstrate that this barrier can be overcome through hardware-software co-design. Specifically, we identify that Bistable Memory Recurrent Units (BMRUs), a class of Recurrent Neural Networks (RNNs) with discrete-valued outputs and hysteretic dynamics, admit an ultra-low power current-mode analog implementation which we design from first principles. The resulting circuit establishes a one-to-one correspondence between each learned parameter and a circuit element. The discrete outputs suppress analog noise by at least 20-fold at each cell boundary, breaking the noise accumulation that prevents analog recurrence. We reformulate BMRUs for first-quadrant operation with fixed thresholds, enabling the direct correspondence while preserving expressivity and trainability. Transistor-level simulations in 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) show near-perfect agreement between software predictions and circuit-level behavior, with the software model thereby serving as a high-fidelity simulator of the physical hardware at low computational cost. We leverage this fidelity to conduct large-scale noise immunity and power scaling analyses: the power cost of adding recurrence scales linearly with state dimension, while the feedforward layers dominating total power scale quadratically, meaning recurrence is added at linear marginal cost relative to the feedforward backbone. End-to-end keyword spotting achieves sub-microwatt inference at the RNN core.

Figures

Figures reproduced from arXiv: 2605.15216 by Arthur Fyon, Damien Ernst, Guillaume Drion, Jean-Michel Redout\'e, Julien Brandoit, Loris Mendolia.

Figure 1
Figure 1. Figure 1: Current-mode analog implementation and FQ BMRU formulation. A. Schematic of the ultra-low power current-mode bistable cell (top) and associated input-output current relationship (bottom). All thresholds and output gain are independently tunable via bias currents. B. FQ BMRU equations (top) and input candidate versus state relationship (bottom), with α, βlo and βhi as learnable parameters. The correspondenc… view at source ↗
Figure 2
Figure 2. Figure 2: Analog CMOS implementation of a complete BMRU-based RNN for “yes” KWS. A. Complete network architecture where all operations are computed using analog primitives whose behavior emerges from the physical properties of subthreshold transistors (top). For this proof of concept, a minimal configuration with N = 2 layers and state dimension d = 4 is implemented. KWS task for “yes” recognition. MFCC extraction o… view at source ↗
Figure 3
Figure 3. Figure 3: Large-scale noise robustness analysis across three benchmarks (sMNIST, pMNIST and dKWS). Accuracy as a function of injected noise level (relative to measured analog noise from transistor-level simulations) for FQ BMRU, LRU, and minGRU. At analog noise level, FQ BMRU and minGRU maintain full accuracy, while LRU fails catastrophically. FQ BMRU exhibits robust performance up to approximately 2× the analog noi… view at source ↗
Figure 4
Figure 4. Figure 4: illustrates the fundamental current mirror topology used to implement weighted connections. In subthreshold operation, a diode-connected input transistor converts an input current Ix into a gate voltage Vx = Vy, which is shared with the output transistor. Since both transistors operate at identical gate-source voltages, their drain currents are primarily determined by their width ratio: Iy ≈ Wout Win Ix. (… view at source ↗
Figure 5
Figure 5. Figure 5: Binary-weighted PMOS current mirror for programmable weight implementation. The effective output current is set by enabling combinations of binary-scaled mirror branches, allowing discrete (quantized) weight tuning via a shift register. P − 1 V1 · · · P − d Vd P − b V − b,j N + 1 V1 · · · N + d Vd N + b V + b,j PReLU w − 1 I1 w − d Id I − b,j w + 1 I1 w + d Id I + b,j ReLU Pd i=1 w + i Ii − w − i Ii  + I… view at source ↗
Figure 6
Figure 6. Figure 6: FC layer with ReLU activation. PMOS mirrors (top) implement negative weights; NMOS mirrors (bottom) implement positive weights. The diode-connected PMOS harvests net positive current. current flows from the supply, implementing ReLU activation and providing output voltage Vout,j for subsequent stages. For layers requiring anti-ReLU activation, the output transistor is replaced with a diode-connected NMOS t… view at source ↗
Figure 7
Figure 7. Figure 7: FC layer with anti-ReLU activation. Same structure as [PITH_FULL_IMAGE:figures/full_fig_p029_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: CMOS implementation of the FQ BMRU cell. Top left: conceptual dual-Heaviside feedback architecture. Top right (blue): single Heaviside element H1 using 5 transistors. Bottom (red): complete Schmitt trigger with feedback, using 9 transistors total. The top right panel (blue) of [PITH_FULL_IMAGE:figures/full_fig_p030_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Tunability of the CMOS implementation of the FQ BMRU cell. Input-output current relationship of the CMOS implementation of the FQ BMRU cell. All thresholds and output gain are independently tunable via bias currents. an NMOS transistor (M8). This feedback current is mirrored through a PMOS current mirror (M7 and M9), and injected back into the comparator branch of H1 (M1, M2, and M9), thereby increasing th… view at source ↗
Figure 10
Figure 10. Figure 10: CMOS FQ BMRU cell simulation results. Transient simulation under triangular input current for different operating temperatures (left). DC sweep demonstrating hysteretic behavior for different operating temperatures (middle). Monte Carlo analysis with 3σ process variation at room temperature (right). Baseline parameters: Igain = 486 pA, Ithresh = 368 pA, Iwidth = 216 pA. Transient response and DC character… view at source ↗
Figure 11
Figure 11. Figure 11: Tunability of CMOS FQ BMRU cell parameters. Igain sweep from 0 to 500 pA for different operating temperatures (left). Ithresh sweep from 100 pA to 400 pA with Iwidth = 50 pA (middle). Iwidth sweep from 10 pA to 300 pA (right). Baseline parameters as in [PITH_FULL_IMAGE:figures/full_fig_p032_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Component-level power breakdown across 50 inferences. Power consumption of FQ BMRU cells versus FC layers for 50 inference samples. The approximately even split at d = 4 indicates that both components contribute comparably to efficiency. FQ BMRU cells exhibit substantially lower power variance, consistent with stable discrete-output dynamics [PITH_FULL_IMAGE:figures/full_fig_p033_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Illustration of 20× error suppression at BMRU cell boundaries. During inference for the sample in [PITH_FULL_IMAGE:figures/full_fig_p034_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Hardware inference traces from Cadence Spectre simulation (seed 45). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “down”. Hardware prediction via majority vote: “background”. Software prediction: “background” [PITH_FULL_IMAGE:figures/full_fig_p036_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Hardware inference traces from Cadence Spectre simulation (seed 47). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 36 [PITH_FULL_IMAGE:figures/full_fig_p036_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Hardware inference traces from Cadence Spectre simulation (seed 48). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 37 [PITH_FULL_IMAGE:figures/full_fig_p037_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Hardware inference traces from Cadence Spectre simulation (seed 49). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “back￾ground”. Software prediction: “background”. In this case, both implementations misclassify the sample. Note that the spoken “yes” has an… view at source ↗
Figure 18
Figure 18. Figure 18: Hardware inference traces from Cadence Spectre simulation (seed 50). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 38 [PITH_FULL_IMAGE:figures/full_fig_p038_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Hardware inference traces from Cadence Spectre simulation (seed 52). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: background noise (no speech). Hardware prediction via majority vote: “background”. Software prediction: “background” [PITH_FULL_IMAGE:figures/full_fig_p039_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Hardware inference traces from Cadence Spectre simulation (seed 66). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “up”. Hardware prediction via majority vote: “background”. Software prediction: “background”. 39 [PITH_FULL_IMAGE:figures/full_fig_p039_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: Hardware inference traces from Cadence Spectre simulation (seed 67). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “back￾ground”. Software prediction: “yes”. This is the only case across 50 test samples where hardware and software predictions differ [PITH_… view at source ↗
Figure 22
Figure 22. Figure 22: Hardware inference traces from Cadence Spectre simulation (seed 68). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 40 [PITH_FULL_IMAGE:figures/full_fig_p040_22.png] view at source ↗
Figure 23
Figure 23. Figure 23: Hardware inference traces from Cadence Spectre simulation (seed 61). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “right”. Hardware prediction via majority vote: “background”. Software prediction: “background” [PITH_FULL_IMAGE:figures/full_fig_p041_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: PVT corner validation from Cadence Spectre simulation (seed 51). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each PVT condition (bottom). All five process corners (TT, FF, SS, FS, SF), three temperatures (−27◦C, 27◦C, 81◦C), and ±10% supply voltage variation are evaluated. Spoken word: “yes”. Correct classif… view at source ↗
Figure 25
Figure 25. Figure 25: PVT corner validation from Cadence Spectre simulation (seed 66). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each PVT condition (bottom). All five process corners (TT, FF, SS, FS, SF), three temperatures (−27◦C, 27◦C, 81◦C), and ±10% supply voltage variation are evaluated. Input: background noise. Correct cl… view at source ↗
Figure 26
Figure 26. Figure 26: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 51). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 11.5%. 42… view at source ↗
Figure 27
Figure 27. Figure 27: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 45). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “down”. Nominal prediction: “background”. Impaired sample rate: 0… view at source ↗
Figure 28
Figure 28. Figure 28: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 47). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0%. 43 [… view at source ↗
Figure 29
Figure 29. Figure 29: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 48). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0.5% [PI… view at source ↗
Figure 30
Figure 30. Figure 30: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 49). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “background” (misclassified under nomi… view at source ↗
Figure 31
Figure 31. Figure 31: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 50). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0% [PITH… view at source ↗
Figure 32
Figure 32. Figure 32: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 52). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Input: background noise (no speech). Nominal prediction: “background”. Impaire… view at source ↗
Figure 33
Figure 33. Figure 33: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 66). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “up”. Nominal prediction: “background”. Impaired sample rate: 0% … view at source ↗
Figure 34
Figure 34. Figure 34: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 67). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal hardware pre￾diction: “background” (already in dis… view at source ↗
Figure 35
Figure 35. Figure 35: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 68). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0% [PITH… view at source ↗
Figure 36
Figure 36. Figure 36: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 61). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “right”. Nominal prediction: “background”. Impaired sample rate: … view at source ↗
Figure 37
Figure 37. Figure 37: Multi-class KWS evaluation (11 classes), "three" spoken. A. 2 × 4 network. Logit time evolution (left) and integrated logits used for the final classification decision (right). The classification is correct, but the narrow decision margins leave the prediction vulnerable to mismatch. B. 2 × 16 network. Logit time evolution (left) and integrated logits (right). The classification is correct and the decisio… view at source ↗
Figure 38
Figure 38. Figure 38: Intermediate signal comparison between software and hardware (layer-1 candidates, seed 51). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the first recurrent layer for a representative “yes” inference sample. 49 [PITH_FULL_IMAGE:figures/full_fig_p049_38.png] view at source ↗
Figure 39
Figure 39. Figure 39: Intermediate signal comparison between software and hardware (layer-1 states, seed 51). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the first recurrent layer for a representative “yes” inference sample. 50 [PITH_FULL_IMAGE:figures/full_fig_p050_39.png] view at source ↗
Figure 40
Figure 40. Figure 40: Intermediate signal comparison between software and hardware (layer-2 candidates, seed 51). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the second recurrent layer for a representative “yes” inference sample. 51 [PITH_FULL_IMAGE:figures/full_fig_p051_40.png] view at source ↗
Figure 41
Figure 41. Figure 41: Intermediate signal comparison between software and hardware (layer-2 states, seed 51). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the second recurrent layer for a representative “yes” inference sample. 52 [PITH_FULL_IMAGE:figures/full_fig_p052_41.png] view at source ↗
Figure 42
Figure 42. Figure 42: Intermediate signal comparison between software and hardware (layer-2 output after skip connection, seed 51). Overlay of the 4 software-predicted and Cadence-simulated output signals of the second recurrent layer, after the skip connection, for a representative “yes” inference sample. 53 [PITH_FULL_IMAGE:figures/full_fig_p053_42.png] view at source ↗
Figure 43
Figure 43. Figure 43: Intermediate signal comparison between software and hardware (output logits, seed 51). Overlay of the software-predicted and Cadence-simulated output logit currents for a representative “yes” inference sample. 54 [PITH_FULL_IMAGE:figures/full_fig_p054_43.png] view at source ↗
Figure 44
Figure 44. Figure 44: Intermediate signal comparison between software and hardware (layer-1 candidates, seed 66). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the first recurrent layer for a representative “background” inference sample. 55 [PITH_FULL_IMAGE:figures/full_fig_p055_44.png] view at source ↗
Figure 45
Figure 45. Figure 45: Intermediate signal comparison between software and hardware (layer-1 states, seed 66). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the first recurrent layer for a representative “background” inference sample. 56 [PITH_FULL_IMAGE:figures/full_fig_p056_45.png] view at source ↗
Figure 46
Figure 46. Figure 46: Intermediate signal comparison between software and hardware (layer-2 candidates, seed 66). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the second recurrent layer for a representative “background” inference sample. 57 [PITH_FULL_IMAGE:figures/full_fig_p057_46.png] view at source ↗
Figure 47
Figure 47. Figure 47: Intermediate signal comparison between software and hardware (layer-2 states, seed 66). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the second recurrent layer for a representative “background” inference sample. 58 [PITH_FULL_IMAGE:figures/full_fig_p058_47.png] view at source ↗
Figure 48
Figure 48. Figure 48: Intermediate signal comparison between software and hardware (layer-2 output after skip connection, seed 66). Overlay of the 4 software-predicted and Cadence-simulated output signals of the second recurrent layer, after the skip connection, for a representative “background” inference sample. 59 [PITH_FULL_IMAGE:figures/full_fig_p059_48.png] view at source ↗
Figure 49
Figure 49. Figure 49: Intermediate signal comparison between software and hardware (output logits, seed 66). Overlay of the software-predicted and Cadence-simulated output logit currents for a representative “background” inference sample. 60 [PITH_FULL_IMAGE:figures/full_fig_p060_49.png] view at source ↗

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  1. A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

    eess.SP 2026-05 unverdicted novelty 7.0

    A fully tunable ultra-low-power current-mode bistable memory cell using nine standard CMOS transistors enables spike-based logic gates and noise-immune recurrent neural units.

  2. A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

    eess.SP 2026-05 unverdicted novelty 6.0

    A nine-transistor current-mode bistable memory cell in 180 nm CMOS is presented with independent tuning of threshold, hysteresis, and gain, shown via schematic simulations for spike-based logic gates and recurrent neu...

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