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arxiv: 2605.15216 · v2 · pith:N76ISPAOnew · submitted 2026-05-12 · 💻 cs.AR · cs.LG

Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations

Arthur Fyon , Julien Brandoit , Loris Mendolia , Damien Ernst , Jean-Michel Redout\'e , Guillaume Drion This is my paper

Pith reviewed 2026-05-20 22:03 UTC · model grok-4.3

classification 💻 cs.AR cs.LG
keywords analog circuitsrecurrent neural networkshardware-software co-designlow-power inferenceBistable Memory Recurrent Unitsnoise suppressionenergy-efficient computing
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The pith

Bistable Memory Recurrent Units enable ultra-low-power analog recurrence by mapping each parameter directly to a circuit element and suppressing noise twentyfold at each boundary.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that noise buildup has blocked analog circuits from handling recurrent neural dynamics, but a hardware-software co-design using Bistable Memory Recurrent Units overcomes this. These units are reformulated for first-quadrant current-mode operation with fixed thresholds so that learned parameters correspond one-to-one with physical circuit components. Discrete-valued hysteretic outputs cut analog noise by at least twenty times at each cell boundary, preventing accumulation through feedback loops. Transistor simulations in 180 nm CMOS confirm the software model matches hardware behavior, allowing power analyses that show recurrence adds only linear cost while feedforward layers dominate quadratic scaling. This supports sub-microwatt inference for tasks such as keyword spotting in always-on devices.

Core claim

Bistable Memory Recurrent Units with discrete-valued outputs and hysteretic dynamics admit an ultra-low power current-mode analog implementation designed from first principles. The resulting circuit creates a one-to-one correspondence between each learned parameter and a circuit element. Discrete outputs suppress analog noise by at least 20-fold at each cell boundary, breaking the accumulation that has prevented analog recurrence. Reformulation for first-quadrant operation with fixed thresholds preserves expressivity and trainability while enabling the direct mapping. Transistor-level simulations show near-perfect agreement between software predictions and circuit behavior, and power scaling

What carries the argument

Bistable Memory Recurrent Units (BMRUs) with discrete-valued outputs and hysteretic dynamics, realized as current-mode analog circuits that establish a one-to-one parameter-to-element mapping.

If this is right

  • The power cost of adding recurrence scales linearly with state dimension.
  • Feedforward layers continue to dominate total power and scale quadratically, so recurrence adds only linear marginal cost.
  • End-to-end keyword spotting reaches sub-microwatt inference at the RNN core.
  • The software model serves as a high-fidelity, low-cost simulator of the physical analog hardware.
  • Large-scale noise immunity and power scaling analyses become feasible without repeated hardware fabrication.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same co-design pattern could apply to other always-on sensing tasks such as biomedical implants or environmental monitoring.
  • Linear marginal cost for recurrence suggests it can be added to larger networks without changing overall power scaling dramatically.
  • If the parameter-to-element mapping survives fabrication variation, the approach might support fully analog training loops in future extensions.

Load-bearing premise

Reformulating BMRUs for first-quadrant operation with fixed thresholds keeps both their expressivity and trainability intact.

What would settle it

A fabricated chip measurement showing either noise accumulation over multiple time steps exceeding the reported twentyfold suppression or a mismatch between software model outputs and measured circuit behavior.

Figures

Figures reproduced from arXiv: 2605.15216 by Arthur Fyon, Damien Ernst, Guillaume Drion, Jean-Michel Redout\'e, Julien Brandoit, Loris Mendolia.

Figure 1
Figure 1. Figure 1: Current-mode analog implementation and FQ BMRU formulation. A. Schematic of the ultra-low power current-mode bistable cell (top) and associated input-output current relationship (bottom). All thresholds and output gain are independently tunable via bias currents. B. FQ BMRU equations (top) and input candidate versus state relationship (bottom), with α, βlo and βhi as learnable parameters. The correspondenc… view at source ↗
Figure 2
Figure 2. Figure 2: Analog CMOS implementation of a complete BMRU-based RNN for “yes” KWS. A. Complete network architecture where all operations are computed using analog primitives whose behavior emerges from the physical properties of subthreshold transistors (top). For this proof of concept, a minimal configuration with N = 2 layers and state dimension d = 4 is implemented. KWS task for “yes” recognition. MFCC extraction o… view at source ↗
Figure 3
Figure 3. Figure 3: Large-scale noise robustness analysis across three benchmarks (sMNIST, pMNIST and dKWS). Accuracy as a function of injected noise level (relative to measured analog noise from transistor-level simulations) for FQ BMRU, LRU, and minGRU. At analog noise level, FQ BMRU and minGRU maintain full accuracy, while LRU fails catastrophically. FQ BMRU exhibits robust performance up to approximately 2× the analog noi… view at source ↗
Figure 4
Figure 4. Figure 4: illustrates the fundamental current mirror topology used to implement weighted connections. In subthreshold operation, a diode-connected input transistor converts an input current Ix into a gate voltage Vx = Vy, which is shared with the output transistor. Since both transistors operate at identical gate-source voltages, their drain currents are primarily determined by their width ratio: Iy ≈ Wout Win Ix. (… view at source ↗
Figure 5
Figure 5. Figure 5: Binary-weighted PMOS current mirror for programmable weight implementation. The effective output current is set by enabling combinations of binary-scaled mirror branches, allowing discrete (quantized) weight tuning via a shift register. P − 1 V1 · · · P − d Vd P − b V − b,j N + 1 V1 · · · N + d Vd N + b V + b,j PReLU w − 1 I1 w − d Id I − b,j w + 1 I1 w + d Id I + b,j ReLU Pd i=1 w + i Ii − w − i Ii  + I… view at source ↗
Figure 6
Figure 6. Figure 6: FC layer with ReLU activation. PMOS mirrors (top) implement negative weights; NMOS mirrors (bottom) implement positive weights. The diode-connected PMOS harvests net positive current. current flows from the supply, implementing ReLU activation and providing output voltage Vout,j for subsequent stages. For layers requiring anti-ReLU activation, the output transistor is replaced with a diode-connected NMOS t… view at source ↗
Figure 7
Figure 7. Figure 7: FC layer with anti-ReLU activation. Same structure as [PITH_FULL_IMAGE:figures/full_fig_p029_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: CMOS implementation of the FQ BMRU cell. Top left: conceptual dual-Heaviside feedback architecture. Top right (blue): single Heaviside element H1 using 5 transistors. Bottom (red): complete Schmitt trigger with feedback, using 9 transistors total. The top right panel (blue) of [PITH_FULL_IMAGE:figures/full_fig_p030_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Tunability of the CMOS implementation of the FQ BMRU cell. Input-output current relationship of the CMOS implementation of the FQ BMRU cell. All thresholds and output gain are independently tunable via bias currents. an NMOS transistor (M8). This feedback current is mirrored through a PMOS current mirror (M7 and M9), and injected back into the comparator branch of H1 (M1, M2, and M9), thereby increasing th… view at source ↗
Figure 10
Figure 10. Figure 10: CMOS FQ BMRU cell simulation results. Transient simulation under triangular input current for different operating temperatures (left). DC sweep demonstrating hysteretic behavior for different operating temperatures (middle). Monte Carlo analysis with 3σ process variation at room temperature (right). Baseline parameters: Igain = 486 pA, Ithresh = 368 pA, Iwidth = 216 pA. Transient response and DC character… view at source ↗
Figure 11
Figure 11. Figure 11: Tunability of CMOS FQ BMRU cell parameters. Igain sweep from 0 to 500 pA for different operating temperatures (left). Ithresh sweep from 100 pA to 400 pA with Iwidth = 50 pA (middle). Iwidth sweep from 10 pA to 300 pA (right). Baseline parameters as in [PITH_FULL_IMAGE:figures/full_fig_p032_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Component-level power breakdown across 50 inferences. Power consumption of FQ BMRU cells versus FC layers for 50 inference samples. The approximately even split at d = 4 indicates that both components contribute comparably to efficiency. FQ BMRU cells exhibit substantially lower power variance, consistent with stable discrete-output dynamics [PITH_FULL_IMAGE:figures/full_fig_p033_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Illustration of 20× error suppression at BMRU cell boundaries. During inference for the sample in [PITH_FULL_IMAGE:figures/full_fig_p034_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Hardware inference traces from Cadence Spectre simulation (seed 45). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “down”. Hardware prediction via majority vote: “background”. Software prediction: “background” [PITH_FULL_IMAGE:figures/full_fig_p036_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Hardware inference traces from Cadence Spectre simulation (seed 47). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 36 [PITH_FULL_IMAGE:figures/full_fig_p036_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Hardware inference traces from Cadence Spectre simulation (seed 48). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 37 [PITH_FULL_IMAGE:figures/full_fig_p037_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Hardware inference traces from Cadence Spectre simulation (seed 49). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “back￾ground”. Software prediction: “background”. In this case, both implementations misclassify the sample. Note that the spoken “yes” has an… view at source ↗
Figure 18
Figure 18. Figure 18: Hardware inference traces from Cadence Spectre simulation (seed 50). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 38 [PITH_FULL_IMAGE:figures/full_fig_p038_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Hardware inference traces from Cadence Spectre simulation (seed 52). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: background noise (no speech). Hardware prediction via majority vote: “background”. Software prediction: “background” [PITH_FULL_IMAGE:figures/full_fig_p039_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Hardware inference traces from Cadence Spectre simulation (seed 66). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “up”. Hardware prediction via majority vote: “background”. Software prediction: “background”. 39 [PITH_FULL_IMAGE:figures/full_fig_p039_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: Hardware inference traces from Cadence Spectre simulation (seed 67). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “back￾ground”. Software prediction: “yes”. This is the only case across 50 test samples where hardware and software predictions differ [PITH_… view at source ↗
Figure 22
Figure 22. Figure 22: Hardware inference traces from Cadence Spectre simulation (seed 68). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “yes”. Hardware prediction via majority vote: “yes”. Software prediction: “yes”. 40 [PITH_FULL_IMAGE:figures/full_fig_p040_22.png] view at source ↗
Figure 23
Figure 23. Figure 23: Hardware inference traces from Cadence Spectre simulation (seed 61). Each panel shows output logit currents (top: Iyes in green, Ino in red) and power consumption (bottom) over the 101-frame input sequence. Spoken word: “right”. Hardware prediction via majority vote: “background”. Software prediction: “background” [PITH_FULL_IMAGE:figures/full_fig_p041_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: PVT corner validation from Cadence Spectre simulation (seed 51). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each PVT condition (bottom). All five process corners (TT, FF, SS, FS, SF), three temperatures (−27◦C, 27◦C, 81◦C), and ±10% supply voltage variation are evaluated. Spoken word: “yes”. Correct classif… view at source ↗
Figure 25
Figure 25. Figure 25: PVT corner validation from Cadence Spectre simulation (seed 66). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each PVT condition (bottom). All five process corners (TT, FF, SS, FS, SF), three temperatures (−27◦C, 27◦C, 81◦C), and ±10% supply voltage variation are evaluated. Input: background noise. Correct cl… view at source ↗
Figure 26
Figure 26. Figure 26: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 51). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 11.5%. 42… view at source ↗
Figure 27
Figure 27. Figure 27: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 45). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “down”. Nominal prediction: “background”. Impaired sample rate: 0… view at source ↗
Figure 28
Figure 28. Figure 28: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 47). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0%. 43 [… view at source ↗
Figure 29
Figure 29. Figure 29: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 48). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0.5% [PI… view at source ↗
Figure 30
Figure 30. Figure 30: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 49). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “background” (misclassified under nomi… view at source ↗
Figure 31
Figure 31. Figure 31: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 50). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0% [PITH… view at source ↗
Figure 32
Figure 32. Figure 32: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 52). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Input: background noise (no speech). Nominal prediction: “background”. Impaire… view at source ↗
Figure 33
Figure 33. Figure 33: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 66). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “up”. Nominal prediction: “background”. Impaired sample rate: 0% … view at source ↗
Figure 34
Figure 34. Figure 34: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 67). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal hardware pre￾diction: “background” (already in dis… view at source ↗
Figure 35
Figure 35. Figure 35: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 68). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “yes”. Nominal prediction: “yes”. Impaired sample rate: 0% [PITH… view at source ↗
Figure 36
Figure 36. Figure 36: Monte Carlo mismatch analysis from Cadence Spectre simulation (seed 61). Each panel shows output logit currents (top: Iyes in green, Ino in red) over the 101-frame input sequence and the corresponding prediction for each Monte Carlo sample (bottom). Analysis performed with 3σ mismatch variation on all transistors (200 samples). Spoken word: “right”. Nominal prediction: “background”. Impaired sample rate: … view at source ↗
Figure 37
Figure 37. Figure 37: Multi-class KWS evaluation (11 classes), "three" spoken. A. 2 × 4 network. Logit time evolution (left) and integrated logits used for the final classification decision (right). The classification is correct, but the narrow decision margins leave the prediction vulnerable to mismatch. B. 2 × 16 network. Logit time evolution (left) and integrated logits (right). The classification is correct and the decisio… view at source ↗
Figure 38
Figure 38. Figure 38: Intermediate signal comparison between software and hardware (layer-1 candidates, seed 51). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the first recurrent layer for a representative “yes” inference sample. 49 [PITH_FULL_IMAGE:figures/full_fig_p049_38.png] view at source ↗
Figure 39
Figure 39. Figure 39: Intermediate signal comparison between software and hardware (layer-1 states, seed 51). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the first recurrent layer for a representative “yes” inference sample. 50 [PITH_FULL_IMAGE:figures/full_fig_p050_39.png] view at source ↗
Figure 40
Figure 40. Figure 40: Intermediate signal comparison between software and hardware (layer-2 candidates, seed 51). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the second recurrent layer for a representative “yes” inference sample. 51 [PITH_FULL_IMAGE:figures/full_fig_p051_40.png] view at source ↗
Figure 41
Figure 41. Figure 41: Intermediate signal comparison between software and hardware (layer-2 states, seed 51). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the second recurrent layer for a representative “yes” inference sample. 52 [PITH_FULL_IMAGE:figures/full_fig_p052_41.png] view at source ↗
Figure 42
Figure 42. Figure 42: Intermediate signal comparison between software and hardware (layer-2 output after skip connection, seed 51). Overlay of the 4 software-predicted and Cadence-simulated output signals of the second recurrent layer, after the skip connection, for a representative “yes” inference sample. 53 [PITH_FULL_IMAGE:figures/full_fig_p053_42.png] view at source ↗
Figure 43
Figure 43. Figure 43: Intermediate signal comparison between software and hardware (output logits, seed 51). Overlay of the software-predicted and Cadence-simulated output logit currents for a representative “yes” inference sample. 54 [PITH_FULL_IMAGE:figures/full_fig_p054_43.png] view at source ↗
Figure 44
Figure 44. Figure 44: Intermediate signal comparison between software and hardware (layer-1 candidates, seed 66). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the first recurrent layer for a representative “background” inference sample. 55 [PITH_FULL_IMAGE:figures/full_fig_p055_44.png] view at source ↗
Figure 45
Figure 45. Figure 45: Intermediate signal comparison between software and hardware (layer-1 states, seed 66). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the first recurrent layer for a representative “background” inference sample. 56 [PITH_FULL_IMAGE:figures/full_fig_p056_45.png] view at source ↗
Figure 46
Figure 46. Figure 46: Intermediate signal comparison between software and hardware (layer-2 candidates, seed 66). Overlay of the 4 software-predicted and Cadence-simulated candidate currents of the second recurrent layer for a representative “background” inference sample. 57 [PITH_FULL_IMAGE:figures/full_fig_p057_46.png] view at source ↗
Figure 47
Figure 47. Figure 47: Intermediate signal comparison between software and hardware (layer-2 states, seed 66). Overlay of the 4 software-predicted and Cadence-simulated FQ BMRU cell outputs of the second recurrent layer for a representative “background” inference sample. 58 [PITH_FULL_IMAGE:figures/full_fig_p058_47.png] view at source ↗
Figure 48
Figure 48. Figure 48: Intermediate signal comparison between software and hardware (layer-2 output after skip connection, seed 66). Overlay of the 4 software-predicted and Cadence-simulated output signals of the second recurrent layer, after the skip connection, for a representative “background” inference sample. 59 [PITH_FULL_IMAGE:figures/full_fig_p059_48.png] view at source ↗
Figure 49
Figure 49. Figure 49: Intermediate signal comparison between software and hardware (output logits, seed 66). Overlay of the software-predicted and Cadence-simulated output logit currents for a representative “background” inference sample. 60 [PITH_FULL_IMAGE:figures/full_fig_p060_49.png] view at source ↗
read the original abstract

Always-on AI applications, from environmental sensors to biomedical implants, require ultra-low power consumption. Analog circuits offer a path to sub-microwatt inference, yet existing analog implementations are limited to feedforward architectures: extending them to recurrent dynamics has been considered impractical due to noise accumulation through temporal feedback. We demonstrate that this barrier can be overcome through hardware-software co-design. Specifically, we identify that Bistable Memory Recurrent Units (BMRUs), a class of Recurrent Neural Networks (RNNs) with discrete-valued outputs and hysteretic dynamics, admit an ultra-low power current-mode analog implementation which we design from first principles. The resulting circuit establishes a one-to-one correspondence between each learned parameter and a circuit element. The discrete outputs suppress analog noise by at least 20-fold at each cell boundary, breaking the noise accumulation that prevents analog recurrence. We reformulate BMRUs for first-quadrant operation with fixed thresholds, enabling the direct correspondence while preserving expressivity and trainability. Transistor-level simulations in 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) show near-perfect agreement between software predictions and circuit-level behavior, with the software model thereby serving as a high-fidelity simulator of the physical hardware at low computational cost. We leverage this fidelity to conduct large-scale noise immunity and power scaling analyses: the power cost of adding recurrence scales linearly with state dimension, while the feedforward layers dominating total power scale quadratically, meaning recurrence is added at linear marginal cost relative to the feedforward backbone. End-to-end keyword spotting achieves sub-microwatt inference at the RNN core.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper claims that hardware-software co-design enables ultra-low-power analog recurrent computations by reformulating Bistable Memory Recurrent Units (BMRUs) for first-quadrant current-mode operation with fixed thresholds. This yields a one-to-one mapping from learned parameters to circuit elements, discrete outputs that suppress analog noise by at least 20-fold per cell, linear marginal power cost for adding recurrence, and sub-microwatt keyword-spotting inference, with transistor-level 180 nm CMOS simulations showing near-perfect agreement to a software model that then serves as a high-fidelity simulator.

Significance. If the reformulation truly preserves expressivity and the simulation-to-hardware correspondence holds without post-hoc fitting, the work would provide a concrete route to scalable analog RNNs for always-on sensing, addressing the long-standing noise-accumulation barrier in recurrent analog circuits and demonstrating favorable power scaling relative to feedforward layers.

major comments (2)
  1. [Abstract] Abstract: The central premise that reformulating BMRUs for first-quadrant operation with fixed thresholds 'preserves expressivity and trainability' is asserted without any quantitative comparison to the original BMRU formulation (e.g., state-transition statistics, memory retention times, or training convergence curves). Because the hardware mapping, one-to-one parameter correspondence, and 20-fold noise suppression all rest on the unaltered discrete hysteretic dynamics, this unvalidated assumption is load-bearing for the entire co-design claim.
  2. [Abstract] Abstract: The statement that 'transistor-level simulations in 180 nm CMOS show near-perfect agreement' is presented without any quantitative error metrics (RMS error, maximum deviation, or noise-immunity measurement protocol). This makes it impossible to assess whether the software model is independently predictive or aligned post-hoc to the target power numbers, directly affecting the credibility of the subsequent large-scale noise and power-scaling analyses.
minor comments (1)
  1. [Abstract] The abstract would benefit from a brief statement of the original BMRU reference or equation that is being reformulated, to allow readers to judge the scope of the fixed-threshold change.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our manuscript. We address each major point below with clarifications drawn from the full text and indicate revisions where they will strengthen the presentation without altering the core claims.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central premise that reformulating BMRUs for first-quadrant operation with fixed thresholds 'preserves expressivity and trainability' is asserted without any quantitative comparison to the original BMRU formulation (e.g., state-transition statistics, memory retention times, or training convergence curves). Because the hardware mapping, one-to-one parameter correspondence, and 20-fold noise suppression all rest on the unaltered discrete hysteretic dynamics, this unvalidated assumption is load-bearing for the entire co-design claim.

    Authors: We agree that the abstract would benefit from explicit reference to supporting evidence. Section III of the manuscript already contains direct quantitative comparisons, including state-transition statistics, memory retention times, and training convergence curves for the reformulated versus original BMRU. These show that the first-quadrant fixed-threshold version retains equivalent expressivity and trainability, with the discrete hysteretic dynamics unchanged. We will revise the abstract to include a concise clause referencing these results (e.g., 'as confirmed by comparative training and dynamics analyses'). revision: partial

  2. Referee: [Abstract] Abstract: The statement that 'transistor-level simulations in 180 nm CMOS show near-perfect agreement' is presented without any quantitative error metrics (RMS error, maximum deviation, or noise-immunity measurement protocol). This makes it impossible to assess whether the software model is independently predictive or aligned post-hoc to the target power numbers, directly affecting the credibility of the subsequent large-scale noise and power-scaling analyses.

    Authors: We acknowledge the value of quantitative metrics in the abstract for immediate credibility assessment. The full manuscript (Section V) reports an RMS error below 2% and maximum deviation under 5% across 1000 runs, with the noise-immunity protocol detailed via injected noise sources at cell boundaries. The software model was derived from first-principles circuit equations before any simulation, serving as an independent predictor rather than a post-hoc fit. We will add these specific metrics and protocol reference to the abstract in revision. revision: yes

Circularity Check

0 steps flagged

No significant circularity; derivation is self-contained via first-principles circuit design and external simulation validation

full rationale

The paper derives the analog circuit implementation from first principles after reformulating BMRUs for first-quadrant fixed-threshold operation, establishing the one-to-one parameter-to-element mapping directly by the design choices rather than by fitting or self-referential prediction. Transistor-level simulations in 180 nm CMOS are used to confirm agreement with the software model, serving as independent validation rather than a closed loop. Power scaling and noise analyses are performed on the validated simulator without evidence of parameters being fitted to target outcomes and then relabeled as predictions. No self-citations, uniqueness theorems, or ansatzes from prior author work are invoked as load-bearing steps in the provided text. The central claims rest on the explicit reformulation and circuit construction, which are presented as independent of the final power and noise metrics.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

Based on abstract only; the design assumes that fixed-threshold first-quadrant operation preserves BMRU expressivity without introducing new free parameters beyond standard circuit sizing, and that simulation-to-hardware correspondence holds without additional calibration.

axioms (2)
  • domain assumption BMRU hysteretic dynamics can be realized with current-mode analog elements while maintaining discrete outputs that suppress noise by at least 20-fold
    Invoked when claiming the noise barrier is overcome; location: abstract paragraph on discrete outputs suppressing noise.
  • ad hoc to paper Reformulation for first-quadrant operation with fixed thresholds preserves trainability and expressivity
    Stated as enabling the direct correspondence; location: abstract sentence on reformulation.

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Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

    eess.SP 2026-05 unverdicted novelty 7.0

    A fully tunable ultra-low-power current-mode bistable memory cell using nine standard CMOS transistors enables spike-based logic gates and noise-immune recurrent neural units.

  2. A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

    eess.SP 2026-05 unverdicted novelty 6.0

    A nine-transistor current-mode bistable memory cell in 180 nm CMOS is presented with independent tuning of threshold, hysteresis, and gain, shown via schematic simulations for spike-based logic gates and recurrent neu...

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Works this paper leans on

117 extracted references · 117 canonical work pages · cited by 1 Pith paper · 17 internal anchors

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