FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing

Alexander Louis-Ferdinand Jung; Jannik Steinmetz; Konstantin L\"ubeck; Mika Markus M\"uller; Oliver Bringmann

REVIEW 3 major objections 5 minor 19 references

FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read FlexiSAGA shows that a configurable systolic array switching among seven dataflows runs pruned DNNs 1.41x to 4.28x faster than dense and beats commercial CPU/GPU runtimes and two prior sparse accelerators.

desk verdict FlexiSAGA is a serious, detailed systolic-array design with a genuinely new sparse format, but the headline 'whole DNN' speedup is really a CONV/FC-only speedup, and the commercial baselines are not apples-to-apples. read the letter →

arxiv 2506.01566 v1 pith:NRTUOAZN submitted 2025-06-02 cs.PF cs.AIcs.ARcs.LG

Mika Markus Müller , Konstantin Lübeck , Alexander Louis-Ferdinand Jung , Jannik Steinmetz , Oliver Bringmann This is my paper

classification cs.PFcs.AIcs.ARcs.LG

keywords systolicarraysparseGEMMDNNinferenceweightpruningstructuredsparsitydataflowflexibilitycompressedblockhardwareaccelerator

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a single reconfigurable systolic-array GEMM accelerator can process both dense and pruned deep neural networks efficiently by selecting, per operator, one of seven dataflows. For the four CIFAR-10 networks tested, the authors report whole-network sparse-over-dense inference speedups of 1.41x to 4.28x, and they say these beat commercial CPU and GPU inference runtimes as well as the operator speedups previously reported for two sparse accelerators. The reason the speedups appear is that the architecture combines two sparse weight formats, including a new compressed sparse block (CSB) format that merges non-zero columns, with a pruning method that creates zero rows and columns aligned to the array's tile shape. A sympathetic reader would take the paper's contribution to be a demonstration that dataflow flexibility and co-designed pruning, not a single specialized sparse dataflow, are what unlock sparse DNN acceleration.

What carries the argument

The central mechanism is per-operator dataflow selection on a reconfigurable systolic array, driven by two sparse weight encodings and a compatible pruning method. The two-stage bitmap format uses a column bit array plus an element bit array to skip zero columns during load; the compressed sparse block (CSB) format goes further by merging several non-zero columns into one and storing a column-index array so the controller can track which input rows are needed, which is what the csOS dataflow exploits. The pruning method is the third piece: it removes structured zero rows or columns of length n, so that the sparse patterns the decoder can skip are present in the actual network weights. Together these let the controller skip zero-column loads and zero-weight multiply-accumulates, and the architecture's configurable aspect ratio changes how many processing elements face the memory interface.

What would settle it

Synthesize a cycle-accurate or measured-SRAM version of FlexiSAGA, run the same four CIFAR-10 networks, and check whether the whole-network sparse-over-dense speedups still reach 1.41x to 4.28x; separately, re-measure the baseline sparse accelerators at the same input resolutions and per-layer sparsity distributions and see whether FlexiSAGA's mean operator speedups still exceed theirs.

Watch

Extended reading notes

Core claim

On the paper's own terms, FlexiSAGA is a tiled systolic array whose processing elements, load/store units, and decompression unit can be configured in height, width, register width, and memory-port count, and whose controller schedules any of seven dataflows: dense input-, weight-, or output-stationary (dIS, dWS, dOS), sparse output-, weight-, or input-stationary (sOS, sWS, sIS), and a sparse output-stationary variant using the new compressed sparse block format (csOS). Sparse tiles are stored either in the two-stage bitmap format, which skips entire zero columns, or in the CSB format, which greedily merges multiple sparse columns into one so that a combined column can be loaded as a single unit. The pruning method, based on structured sparsity learning, zeros out row or column vectors of length n inside each im2col-transformed weight tile, so the resulting sparsity pattern is visible to the decompression and controller logic. The authors report that with per-operator dataflow selection, the whole-network sparse-over-dense speedup reaches 4.28 for AlexNet and no less than 1.41 for ResNet50, and that the mean operator-wise speedups against the one-sided sparse accelerators used as baselines are higher on all three compared networks.

Load-bearing premise

All reported speedups assume an SRAM that reads and writes in a single cycle with eight memory ports; if real SRAM latency, port contention, or refresh behavior makes sparse accesses slower than one cycle, the speedups shrink.

Editorial extensions

If this is right

Whole pruned-network inference on AlexNet, VGG16, GoogLeNet, and ResNet50 is 1.41x to 4.28x faster than dense inference on the same FlexiSAGA array, with the best speedup on AlexNet and the smallest on ResNet50.
For every DNN operator, choosing the dataflow with the minimum runtime across the seven options matters: the sparse dataflows, and csOS in particular, dominate the minimum-runtime choices across DNNs and array sizes.
Because sparsity is exploited only in the weight matrix, deployment does not require on-device zero detection in inputs; the sparse weight tiles are prepared once before inference.
The design-space exploration for AlexNet shows that an unbalanced array shape with column-vector pruning can give the lowest whole-network runtime, because more processing elements face the memory interface, and that the optimal dataflow differs between convolution and fully-connected operators.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

One implication not drawn in the paper is that the sparse CSB merged-column idea could apply to any GEMM with structured column patterns, not just DNN weights, since the controller only needs the column-index array to track which input rows are active.
The paper's comparison to the two prior sparse accelerators relies on speedup numbers reported there under different input resolutions and sparsity; a same-workload rerun would be the natural next test, but the paper itself does not perform it.
The conclusion points toward multi-head attention as the next operator class; the dataflow-selection principle suggests attention weight sparsity could be exploited by reusing the sparse output-stationary paths rather than adding a separate transformer unit.

Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

FlexiSAGA is a solid systems paper. The genuinely new piece is the CSB sparse format, which merges non-zero columns to cut memory traffic, and the co-design pruning search that picks both the systolic array shape and the pruning vector length. The seven dataflows are described carefully with step-by-step examples, and the RTL simulator gives concrete cycle counts. The design space exploration is a nice touch and shows real effort. I also credit the authors for disclosing in Section 6.2 that their dense and sparse runtimes are the clock cycle sums of the CONV and FC operators only. That is the right kind of transparency.

The soft spots are real, though not fatal. The abstract's "whole DNN" speedup of 1.41 to 4.28 is not backed by the reported measurement. Excluding ReLU, pooling, batch norm, and shortcut additions from both numerator and denominator changes what is being measured. The authors assert those layers are "very small" but give no cycle breakdown. For ResNet50, with its skip connections and batch norms, that assertion is not safe. Comparing that CONV/FC-only ratio to DeepSparse and TensorRT numbers that include the full DNN inflates FlexiSAGA's advantage. The paper would be more honest labeling this a "GEMM-layer" speedup and then arguing, with data, that the non-GEMM fraction is negligible.

The memory model is another soft spot. Unit read and write latencies with eight ports is a cycle-approximate assumption. Sparse access patterns could easily see contention or extra latency on real SRAM. That could shrink the speedups, though probably not eliminate them. I would like to see a sensitivity analysis.

The SCNN and SparTen operator comparisons are also shaky: those results come from [8] and were presumably generated with different input resolutions and sparsity levels than CIFAR-10. The paper should say so when presenting the comparison.

On the plus side, the paper does not fit parameters to produce speedups; the results come from an RTL simulator, and the architecture is described well enough to be reconstructed. No code is released, which is a reproducibility minus, but this is still a serious attempt.

Who is this for? People working on sparse systolic accelerators and hardware-aware pruning will find the CSB format and the dataflow evaluation useful. It is not a breakthrough, but it is a credible subfield contribution. It deserves peer review, with major revisions to fix the evaluation framing and add the missing sensitivity and breakdown data. My recommendation: send it out, ask for a meaningful revision, and see if the claims are reworded to match the actual measurements.

Referee Report

3 major / 5 minor

Summary. The paper presents FlexiSAGA, a configurable systolic-array accelerator for dense and sparse GEMM operations, supporting seven dataflows and a new compressed sparse block (CSB) format. It also introduces a structured pruning method tailored to the accelerator's sparse formats, enabling a DNN/HW co-design flow. The authors evaluate FlexiSAGA on AlexNet, VGG16, GoogLeNet, and ResNet50 for CIFAR-10 classification using an RTL simulator with a cycle-approximate SRAM memory model. They report sparse-over-dense whole-DNN inference speedups of 1.41–4.28 and compare these with DeepSparse on Intel Xeon, TensorRT on Nvidia Orin, and operator-level results from SCNN and SparTen.

Significance. If the results hold, FlexiSAGA provides a flexible and practical approach to exploiting weight sparsity in DNN inference, with a novel sparse format, a well-defined dataflow design space, and a pruning method that is co-designed with the hardware. The use of an RTL simulator with concrete cycle counts and a thorough design-space exploration are notable strengths. However, the headline claim of a 'whole DNN' speedup is not supported by the reported measurements, which cover only CONV/FC operators, and the comparisons with commercial baselines are therefore not apples-to-apples. The central architecture and dataflow ideas are valuable and likely correct, but the evaluation methodology needs substantial revision before the main claims can be accepted.

major comments (3)

[Section 6.2, Fig. 8(a), Fig. 9] The 'whole DNN' sparse-over-dense speedup is computed as the ratio of clock-cycle sums of the unpruned and pruned CONV and FC operators only. Non-CONV/FC layers (ReLU, batch norm, pooling, shortcut additions, softmax) are not executed on FlexiSAGA and are excluded from both numerator and denominator. The paper asserts in Section 6.2 that these layers are 'very small' but provides no cycle or time breakdown, which is especially problematic for ResNet50 with its numerous element-wise addition and batch-norm operations. Meanwhile, the DeepSparse and TensorRT baselines report speedups over the full DNN, including all layers. This makes Fig. 9 an apples-to-oranges comparison and does not support the abstract's 'whole DNN sparse-over-dense inference speedup' claim. Please either rename the metric to 'CONV/FC operator speedup,' add a justified estimate of non-GEMM cycles to the FlexiSAGA totals, or compare against operator-level baselines only.
[Section 6.1] All FlexiSAGA cycle counts are produced by a cycle-approximate SRAM memory model with unit read and write latencies and eight ports. The sparse dataflows involve irregular, data-dependent access patterns, such as skipping zero columns or merging columns in the CSB format. Multi-cycle memory latencies, bank conflicts, or refresh effects would disproportionately affect these irregular accesses relative to dense streaming, so the reported sparse-over-dense speedups could shrink substantially. Since every speedup in the paper is a ratio of cycle counts, this assumption is load-bearing. Please provide a sensitivity analysis (e.g., 2-cycle and 4-cycle latencies) or a technology-based justification that unit latency is a conservative bound for the target SRAM implementation.
[Section 6.3, Fig. 10] The operator-wise comparison with SCNN and SparTen is not controlled. The SCNN and SparTen speedups are taken from [8], which uses different input resolutions, different sparsity distributions, and presumably different pruning criteria, while the FlexiSAGA results are obtained on CIFAR-10 with structured pruning tailored to the FlexiSAGA tile size. Without matching sparsity levels and input shapes, the claim that 'FlexiSAGA shows better results for all three DNNs' is not a fair comparison. Please either use the same sparsity/input configurations for all architectures or explicitly state that the comparison is indicative only and not a controlled benchmark.

minor comments (5)

[Section 6.2] The term 'whole DNN' is used misleadingly in several places, including the abstract and Section 6.2 title. Please use 'CONV/FC operator runtime' or define clearly that the DNN runtime excludes non-GEMM layers.
[Section 5] The pruning algorithm's termination condition is 'until the DNN training cannot reach accuracy a-epsilon anymore after a fixed amount of training epochs'; the fixed amount is never specified. Please state the number of epochs used.
[Section 6.4, Fig. 11] The DSE heatmap does not show a colorbar, making it difficult to interpret the cycle-count ranges. Adding a colorbar and possibly annotating the optimum values would improve readability.
[Section 3, Fig. 1(a)] The memory footprint comparison would be clearer if the caption stated the element width (32-bit) and the exact matrix dimensions and sparsity distribution; currently these details are only in the text.
[Section 6.1] The comparison baselines use different pruning methods: the authors' own method with n=1 for DeepSparse and Nvidia 2:4 sparsity for TensorRT. This asymmetry should be explicitly acknowledged in the text, as it affects how the speedups should be interpreted.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: FlexiSAGA's speedups are measured cycle counts, not fitted or defined by its own inputs.

full rationale

The central sparse-over-dense speedups (1.41 up to 4.28) are obtained by dividing measured cycle counts from the Amaranth RTL simulator on the same FlexiSAGA instance for unpruned vs. pruned CONV/FC operators (Sec. 6.1-6.2). No parameter is fitted to the reported speedup values: per-operator cycle counts are measured exhaustively over dataflows, and the pruning method is evaluated on the same architecture as a DNN/HW co-design flow, which is standard systems practice rather than a definitional reduction. Nothing in the sparse formats or dataflows is defined in terms of the reported speedup, and no load-bearing result rests on the authors' own prior work: the two-stage bitmap format and structured-sparsity basis are cited to external works [17,19], and the UltraTrail memory model [2] is only an experimental setup assumption. The comparison to SCNN/SparTen/DeepSparse does raise validity questions: FlexiSAGA's 'whole DNN' total excludes non-GEMM layers while the commercial baselines include them, and the paper's assertion that those layers are 'very small' is unsupported. However, that is a comparability or correctness concern, not circular reasoning. I therefore find no circular step.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

All three pruning hyperparameters are user-chosen, the memory model is a stated assumption, and no invented physical entities are introduced. The CSB format is a data structure, not an entity with a falsifiable handle.

free parameters (3)

Pruning sparsity schedule (initial s_j, step delta_j, tolerance epsilon) = s_j=0.7, delta_j=0.01, epsilon=a*0.02
Chosen by hand; directly controls achieved sparsity and therefore the reported speedup.
Pruning vector length n and orientation = n=1, 4, 8, 16; row or column
Selected per experiment or design space exploration; affects structured sparsity per layer and the final speedup.
Systolic array size and shape = 4x4, 8x8, 16x16, 4x18, 6x12, etc.
Architecture configuration chosen in the DSE; speedup varies strongly with it.

assumptions (4)

domain assumption Cycle-approximate SRAM model with unit latency and 8 ports is representative of real memory
Section 6.1; all FlexiSAGA cycle counts and speedups assume this memory model.
standard math CONV operators can be mapped to GEMM via im2col without loss
Section 1, standard technique [3]; used to process all CONV layers as tiled GEMM.
domain assumption Pruned DNNs maintain accuracy within 2% after retraining
Section 6.1; no per-model final accuracy table is given, only target epsilon=a*0.02.
domain assumption Operator-wise SCNN and SparTen results in [8] are directly comparable
Section 6.3; speedups taken from literature without reimplementation, and dataset or input shapes may differ.

how reviews work

0 comments

Cite this review

Pith. "Pith review of FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing." pith.science (2026). https://pith.science/paper/NRTUOAZN

@misc{pith2026250601566,
  author       = {Pith},
  title        = {Pith review of: FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NRTUOAZN}},
  note         = {Machine review of arXiv:2506.01566}
}

read the original abstract

Artificial Intelligence (AI) algorithms, such as Deep Neural Networks (DNNs), have become an important tool for a wide range of applications, from computer vision to natural language processing. However, the computational complexity of DNN inference poses a significant challenge, particularly for processing on resource-constrained edge devices. One promising approach to address this challenge is the exploitation of sparsity in DNN operator weights. In this work, we present FlexiSAGA, an architecturally configurable and dataflow-flexible AI hardware accelerator for the sparse and dense processing of general matrix multiplications (GEMMs). FlexiSAGA supports seven different sparse and dense dataflows, enabling efficient processing of resource intensive DNN operators. Additionally, we propose a DNN pruning method specifically tailored towards the FlexiSAGA architecture, allowing for near-optimal processing of dense and sparse convolution and fully-connected operators, facilitating a DNN/HW co-design flow. Our results show a whole DNN sparse-over-dense inference speedup ranging from 1.41 up to 4.28, outperforming commercial and literature-reported accelerator platforms.

Figures

Figures reproduced from arXiv: 2506.01566 by the authors.

**Figure 1.** (a) Memory footprint comparison of different sparse matrix formats and no compression for a 128×512 matrix of 32bit values with varying sparsities and uniformly distributed zero elements. (b) Two-stage bitmap format example. (c) Compressed sparse block (CSB) format example. sparse column (CSC) format, but it stores a matrix by columns instead of rows. The non-zero elements are also stored in an array, along with the… view at source ↗

**Figure 2.** (a) Block diagram of the FlexiSAGA architecture. (b) Visualization of the three dense tiled GEMM dataflows supported by the FlexiSAGA architecture. the column index is stored. The row index is implicitly encoded in the order of the column index array. For each column starting from the first, we use greedy search to find matching columns to merge with. Columns match if the position of the non-zero elements of one col… view at source ↗

**Figure 3.** Example for processing single tile using the sparse tiled GEMM output stationary dataflow (sOS) on a FlexiSAGA architecture of size 2×3. Sparse Output Stationary Dataflow (sOS) [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗

Figures from the paper (8 more)

**Figure 4.** Figure 4: Example for processing single tile using the sparse tiled GEMM weight stationary dataflow (sWS) on a FlexiSAGA architecture of size 2×3. a d e b c 0 0 0 0 0 0 0 A B C D E F c E F b C D a A B Step 0 e E c F 0 C b D d A a B Step 5 e E c F 0 C b D d⋅A d B a⋅B d A d⋅A Ste…

**Figure 5.** Figure 5: Example for processing single tile using the sparse tiled GEMM input stationary dataflow (sIS) on a FlexiSAGA architecture of size 2×3. steps 5 to 9, the partial sums are cleared and the second column of the input tile is propagated through the SA in the same manner as…

**Figure 6.** Figure 6: Example for processing single tile using the sparse tiled GEMM output stationary dataflow (csOS) using the CSB format on a FlexiSAGA architecture of size 2×3. In steps 5 to 9, the partial sums are cleared and the next non-zero row of the weight tile is propagated thro…

**Figure 7.** Figure 7: Operator and operator block sparsities for different DNNs and vector lengths n and vector orientations. 6 Results 6.1 Experimental Setup To evaluate the FlexiSAGA architecture, we implemented a configurable virtual prototype (VP) using the Amaranth HDL [1] which allows…

**Figure 8.** Figure 8: (a) Comparison of whole DNN runtimes in clock cycles for different FlexiSAGA systolic array sizes. (b) Distribution of selected dataflows with minimal runtime per DNN operator across all DNNs and all FlexiSAGA sizes. The overall sparsity shows only slight variations fo…

**Figure 9.** Figure 9: Whole DNN sparse-over-dense speedup comparison between an Nvidia Orin GPU (2:4 sparsity), Nvidia Orin ARM CPU and Intel Xeon CPU (DeepSparse), and FlexiSAGA with different systolic array sizes [PITH_FULL_IMAGE:figures/full_fig_p013_9.png]

**Figure 10.** Figure 10: Operator-wise sparse-over-dense speedup comparison between one-sided SCNN, one-sided SparTen, and FlexiSAGA 8×8 for AlexNet, VGG16, and GoogLeNet convolution operators. where some operators have such a high sparsity that they can almost be skipped entirely, leading to…

**Figure 11.** Figure 11: Design space exploration comparing the runtime in clock cycles of two AlexNet operators mapped onto a FlexiSAGA architecture of different shapes comprised of 72 PEs for all dataflows and different pruning parameters. explained by the linear scaling of the memory inter…

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

19 extracted references · 18 canonical work pages

[8]

et al.: SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks

Gonidmalla A. et al.: SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks. In: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. p. 151–165. MICRO ’52, New York, NY, USA (2019)

work page 2019
[1]

Amaranth HDL.https://github.com/amaranth-lang/amaranth(Mar 2025) 16 M. M. Müller and K. Lübeck et al

work page 2025
[2]

et al.: UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Ac- celerator for Efficient Keyword Spotting

Bernardo P.P. et al.: UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Ac- celerator for Efficient Keyword Spotting. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems39(11), 4240–4251 (2020)

work page 2020
[3]

In: Tenth International Workshop on Frontiers in Handwriting Recognition

Chellapilla, K., Puri, S., Simard, P.: High Performance Convolutional Neural Net- works for Document Processing. In: Tenth International Workshop on Frontiers in Handwriting Recognition. Suvisoft, La Baule, France (Oct 2006)

work page 2006
[4]

et al.: Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

Chen, Y.H. et al.: Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE Journal of Solid-State Circuits52(1), 127–138 (Jan 2017)

work page 2017
[5]

IEEE Transactions on Pattern Analysis and Machine Intelligence46(12), 10558–10578 (2024)

Cheng, H., Zhang, M., Shi, J.Q.: A Survey on Deep Neural Network Pruning: Taxonomy, Comparison, Analysis, and Recommendations. IEEE Transactions on Pattern Analysis and Machine Intelligence46(12), 10558–10578 (2024)

work page 2024
[6]

In: 20th International Symposium on Qual- ity Electronic Design (ISQED)

Ganguly, A., Muralidhar, R., Singh, V.: Towards Energy Efficient non-von Neu- mann Architectures for Deep Learning. In: 20th International Symposium on Qual- ity Electronic Design (ISQED). pp. 335–342 (2019)

work page 2019
[7]

et al.: Gemmini: Enabling Systematic Deep-Learning Architecture Eval- uation via Full-Stack Integration

Genc, H. et al.: Gemmini: Enabling Systematic Deep-Learning Architecture Eval- uation via Full-Stack Integration. In: Proceedings of the 58th Annual Design Au- tomation Conference (DAC) (2021)

work page 2021

Show all 19 references

[9]

et al.: Deep Residual Learning for Image Recognition (2015)

He, K. et al.: Deep Residual Learning for Image Recognition (2015)

2015
[10]

et al.: How Well Do Sparse ImageNet Models Transfer? In: 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Iofinova, E. et al.: How Well Do Sparse ImageNet Models Transfer? In: 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR). IEEE (Jun 2022)

2022
[11]

Communications of the ACM60(6), 84–90 (May 2017)

Krizhevsky, A., Sutskever, I., Hinton, G.E.: ImageNet Classification with Deep Convolutional Neural Networks. Communications of the ACM60(6), 84–90 (May 2017)

2017
[12]

et al.: Sparse Fine-tuning for Inference Acceleration of Large Language Models (2023)

Kurtic, E. et al.: Sparse Fine-tuning for Inference Acceleration of Large Language Models (2023)

2023
[13]

et al.: Accelerating Sparse Deep Neural Networks (2021)

Mishra, A. et al.: Accelerating Sparse Deep Neural Networks (2021)

2021
[14]

et al.: SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

Parashar, A. et al.: SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. In: Proceedings of the 44th Annual International Symposium on Computer Architecture. p. 27–40. ISCA ’17, Association for Computing Machinery, New York, NY, USA (2017)

2017
[15]

et al.: PyTorch: An Imperative Style, High-Performance Deep Learning Library

Paszke, A. et al.: PyTorch: An Imperative Style, High-Performance Deep Learning Library. In: Advances in Neural Information Processing Systems. vol. 32. Curran Associates, Inc. (2019)

2019
[16]

Simonyan, K., Zisserman, A.: Very Deep Convolutional Networks for Large-Scale Image Recognition (2015)

2015
[17]

ACMTransactionsonArchitectureandCodeOptimization19(3),1–26(May2022)

Soltaniyeh, M., Martin, R.P., Nagarakatte, S.: An Accelerator for Sparse Convolu- tional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication. ACMTransactionsonArchitectureandCodeOptimization19(3),1–26(May2022)
[18]

et al.: Going Deeper with Convolutions

Szegedy, C. et al.: Going Deeper with Convolutions. In: 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). p. 1–9 (Jun 2015)

2015
[19]

et al.: Learning Structured Sparsity in Deep Neural Networks

Wen, W. et al.: Learning Structured Sparsity in Deep Neural Networks. In: Ad- vances in Neural Information Processing Systems. vol. 29. Curran Associates, Inc. (2016)

2016

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [8]

et al.: SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks

Gonidmalla A. et al.: SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks. In: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. p. 151–165. MICRO ’52, New York, NY, USA (2019)

work page 2019

[2] [1]

Amaranth HDL.https://github.com/amaranth-lang/amaranth(Mar 2025) 16 M. M. Müller and K. Lübeck et al

work page 2025

[3] [2]

et al.: UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Ac- celerator for Efficient Keyword Spotting

Bernardo P.P. et al.: UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Ac- celerator for Efficient Keyword Spotting. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems39(11), 4240–4251 (2020)

work page 2020

[4] [3]

In: Tenth International Workshop on Frontiers in Handwriting Recognition

Chellapilla, K., Puri, S., Simard, P.: High Performance Convolutional Neural Net- works for Document Processing. In: Tenth International Workshop on Frontiers in Handwriting Recognition. Suvisoft, La Baule, France (Oct 2006)

work page 2006

[5] [4]

et al.: Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

Chen, Y.H. et al.: Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE Journal of Solid-State Circuits52(1), 127–138 (Jan 2017)

work page 2017

[6] [5]

IEEE Transactions on Pattern Analysis and Machine Intelligence46(12), 10558–10578 (2024)

Cheng, H., Zhang, M., Shi, J.Q.: A Survey on Deep Neural Network Pruning: Taxonomy, Comparison, Analysis, and Recommendations. IEEE Transactions on Pattern Analysis and Machine Intelligence46(12), 10558–10578 (2024)

work page 2024

[7] [6]

In: 20th International Symposium on Qual- ity Electronic Design (ISQED)

Ganguly, A., Muralidhar, R., Singh, V.: Towards Energy Efficient non-von Neu- mann Architectures for Deep Learning. In: 20th International Symposium on Qual- ity Electronic Design (ISQED). pp. 335–342 (2019)

work page 2019

[8] [7]

et al.: Gemmini: Enabling Systematic Deep-Learning Architecture Eval- uation via Full-Stack Integration

Genc, H. et al.: Gemmini: Enabling Systematic Deep-Learning Architecture Eval- uation via Full-Stack Integration. In: Proceedings of the 58th Annual Design Au- tomation Conference (DAC) (2021)

work page 2021