REVIEW 4 major objections 3 minor 1 cited by
This paper introduces the wa-hls4ml dataset of 683,176 fully synthesized neural networks and shows that GNN- and transformer-based surrogate models predict FPGA resource usage and latency within a few percent on the synthetic test set, redu
Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →
T0 review · deepseek-v4-flash
2026-08-03 23:38 UTC pith:SH6ILEYE
load-bearing objection Large, open hls4ml synthesis dataset and a reasonable benchmark package; the abstract overstates the surrogate accuracy and Table 4 has at least one implausible value. the 4 major comments →
wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
The central claim is that resource and latency outcomes of hls4ml logic synthesis can be predicted from a per-layer description of the neural network architecture without running synthesis. The authors represent each layer as a node with an 18-dimensional feature vector—input/output dimensions, precision, reuse factor, strategy, layer/activation type, filters, kernel size, stride, padding, batch normalization, and I/O type—and connect nodes along the sequential dataflow. A GATv2-based graph neural network and a transformer trained on 683,176 synthesized samples achieve the stated few-percent accuracy on the synthetic test set, while the included exemplar models reveal that this representatio
What carries the argument
The key machinery is the per-layer 18-dimensional feature vector plus the network-as-graph encoding, processed by a five-layer GATv2 graph attention network or a two-block transformer with a [CLS] token. The GNN's attention weights dynamically determine which layer relationships matter, and learnable pooling—additive, mean, and max—aggregates node embeddings into a graph-level prediction of six targets: LUTs, FFs, DSPs, BRAM, latency cycles, and initiation interval. The transformer treats each layer as a token with positional encoding and uses the [CLS] output to regress the same six targets.
Load-bearing premise
That each layer's local attributes and the sequential order of layers fully determine the post-synthesis resource and latency counts, so a model trained on those features can predict unseen architectures; the exemplar results show this premise weakens outside the training distribution.
What would settle it
Synthesize a neural network with a skip connection or other cross-layer interaction that is absent from the training set, run the surrogate, and compare predictions against actual logic synthesis; if the error substantially exceeds the few-percent accuracy reported on the synthetic test set, the claim that the per-layer feature representation suffices is falsified.
If this is right
- If a designer's target architecture is in-distribution, surrogate predictions within a few percent let them evaluate design alternatives in seconds rather than hours, without running synthesis.
- The open benchmark and standardized metrics (R², SMAPE, RMSE, RPE box plots) give the community a common ground for comparing future resource and latency estimators.
- The dataset's full synthesis artifacts—HLS code, intermediate representations, reports, and logs—support downstream tasks beyond regression, such as code- and IR-driven learning and LLM-based HLS assistants.
- The authors' own exemplar results imply that broader architectural diversity, not just more samples, is needed for surrogates to generalize to realistic scientific models.
- Extending the dataset with skip connections, larger reuse ranges, and more target boards is the stated direction for closing the exemplar gap.
Where Pith is reading between the lines
- The sharp exemplar drop suggests the 18-dimensional local feature vector omits cross-layer interactions such as skip connections and layer fusion that materially change synthesis outcomes; adding explicit graph-level or pairwise features would be a testable fix.
- Because the dataset stores the full hls4ml project for every sample, the same prediction problem can be re-targeted to other high-level synthesis tools or FPGA families by re-synthesizing a subset, making the benchmark portable.
- While generalization improves, a practical workaround is to use the surrogate only for early design-space pruning and verify the final candidate with a real synthesis run.
- The negative R² values on several exemplar metrics, such as the Quarks model, imply that current surrogates are worse than predicting the dataset mean for those cases, so users should not trust them outside the synthetic distribution without additional validation.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper introduces wa-hls4ml, an open benchmark and dataset of 683,176 hls4ml-synthesized neural networks (fully connected, 1D/2D convolutional) targeting Xilinx FPGAs, with train/validation/test splits of 478,220/102,472/102,484 samples plus 887 exemplar samples from scientific applications. It defines evaluation metrics (R^2, SMAPE, RMSE, RPE) and presents three surrogate models: a rule4ml-style MLP baseline, a GATv2-based GNN, and a small transformer, each predicting BRAM, DSP, FF, LUT, clock cycles, and initiation interval. The test-set results show strong in-distribution performance for several targets (e.g., transformer R^2 = 0.95 for cycles and II), while exemplar results show substantial degradation. The abstract claims the models 'generally predict latency and resources for the 75% percentile within several percent' on the synthetic test set.
Significance. The dataset and benchmark, if adopted, are a genuinely useful community resource: the scale (683k fully synthesized samples), the open release of full synthesis projects/logs, and the explicit exemplar-based evaluation of distribution shift are all strengths. The GNN and transformer surrogates are reasonable first attempts and show promising in-distribution results on several targets. However, the paper's headline accuracy claim overstates what the reported metrics support, and several evaluation inconsistencies affect the comparability of the results. The benchmark contribution is likely significant; the surrogate-model evaluation needs to be tightened before the paper can be accepted.
major comments (4)
- [Abstract; §5.2; Eq. (2)] The central claim that the models 'generally predict latency and resources for the 75% percentile within several percent' is not supported by Table 4. Mean SMAPE values on the synthetic test set are 10–20% for most metrics (GNN: BRAM 19.5%, DSP 15.1%, FF 11.6%, LUT 11.4%, Cycles 15.7%, II 13.4%; transformer: BRAM 14.1%, DSP 10.8%, Cycles 10.1%, II 14.1%). Only transformer FF/LUT are near 2.9%. If the claim is based on the 75th percentile of RPE, the paper must report those quantile values directly; the box plots alone do not permit numerical verification. Moreover, Eq. (2) and Eq. (4) add 1 to the denominator, so the reported 'percentages' are not standard relative errors and can be materially smaller than true percentage errors for small resources such as BRAM. The abstract should be revised to match the reported metrics or supplemented with exact quantile evidence.
- [§2 (Dataset split)] The manuscript does not state whether the train/validation/test split is performed at the sample level or at the level of distinct model architectures. Since §2.1.1 explains that each architecture is synthesized multiple times with different reuse factors, a sample-level random split can place near-duplicate architectures in both training and test sets, potentially inflating the in-distribution test metrics in Table 4. Please specify the split procedure explicitly and, ideally, report additional metrics on a split that is disjoint at the architecture level.
- [Figure 10 caption; Table 5] The GNN's exemplar evaluation appears to use different data from the other models. The caption of Figure 10 states 'Activation layers are removed from the exemplar set to keep a similar input structure as the GNN was trained on,' while no such caveat accompanies the MLP or transformer figures. If the GNN rows in Table 5 are computed on a modified exemplar set, then the cross-model comparisons in Table 5 are not apples-to-apples. The preprocessing must either be applied consistently to all models or the GNN exemplar results should be clearly separated from the others.
- [§5.2; Table 4 (Dense)] The text states 'For dense layers, all models show improved performance compared to the overall set,' but Table 4 directly contradicts this for the GNN and transformer. In the dense subset, the GNN has R^2 = -0.51 for BRAM and -0.74 for DSP, whereas the overall test set has R^2 = 0.51 and 0.89; the transformer has identical R^2 for BRAM (0.39) and DSP (0.29) in both rows. Since dense networks are the largest category in the dataset, this discrepancy is consequential for the claim that the surrogates perform well in-distribution. Please correct the interpretation or clarify what subset the 'Dense' row actually represents.
minor comments (3)
- [§4.2.1] The description of the '18-dimensional feature vector' is ambiguous and appears inconsistent with the subsequent one-hot encoding and concatenation of global attributes. 'Three input and output dimensions' and the listed categorical features do not obviously sum to 18. Please provide the exact feature list and the dimensionality after preprocessing.
- [§4.2.3; §4.3.3] Training details are incomplete: no learning-rate schedule, dropout rate, weight decay, or random seeds are reported, and the GNN batch size is missing. Given that the paper proposes a benchmark, reporting these details is important for reproducibility.
- [Throughout] Minor typos and wording issues: 'convolutional modes also contain dense, flatten, and pooling layers' has a spacing error; 'an large impact' should be 'a large impact'; 'SMPAPE' appears in §5.2 and should be 'SMAPE'.
Circularity Check
No circularity: surrogate predictions are evaluated on held-out and out-of-distribution synthesis data, with ground truth from logic synthesis; self-citations are disclosed and non-load-bearing.
full rationale
The paper makes no derivation that reduces to its own inputs. The core claim is empirical: GNN and transformer models are trained on 478,220 synthesized samples and evaluated on a held-out 102,484-sample test set plus 887 exemplar samples. Ground truth comes from post-logic synthesis reports, not from the surrogate inputs, so there is no self-definitional or fitted-input-called-prediction structure. The 18-dimensional per-layer feature representation is a modeling assumption, not a circular one: the target values are independently obtained from "the resource and latency usage numbers for that network post-logic synthesis." Self-citations appear (e.g., rule4ml [30] for dataset generation and [29] for per-target MLP training methodology), but they are disclosed prior work used for generation details and do not establish the central result; the benchmark dataset and code are released openly. The paper is also self-critical rather than circular: it states that "the distributions between the exemplar models and test dataset tend to not overlap strongly" and that on the exemplar set "all three predictors show a drop in performance," with many negative R^2 values in Table 5. This out-of-distribution failure is strong evidence that the models are not trivially reproducing their training targets by construction. The apparent inconsistency between the abstract's "within several percent" claim and the Table 4 SMAPE values (roughly 10-20% for most metrics, and Eq. (2) includes a +1 denominator) is a reporting or accuracy concern, not circularity. Overall, the paper's evaluation chain is externally grounded in logic synthesis and held-out data, with no step that is equivalent to its inputs by definition.
Axiom & Free-Parameter Ledger
free parameters (3)
- Surrogate model learned weights (GNN, transformer, MLP) =
optimized on 478,220 training samples
- Architecture hyperparameters =
chosen by hand
- SMAPE epsilon =
1
axioms (5)
- domain assumption Vivado logic synthesis reports are ground truth for resource and latency.
- domain assumption The random/grid synthetic generator covers the hls4ml design space relevant to training a general surrogate.
- domain assumption The per-layer 18-feature representation loses no information needed for resource/latency prediction.
- standard math Train/validation/test sets are independent samples from the same synthetic generator with no leakage.
- standard math R², SMAPE, and RMSE with epsilon=1 are valid evaluation metrics.
read the original abstract
As machine learning (ML) is increasingly implemented in hardware to address real-time challenges in scientific applications, the development of advanced toolchains has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as hardware synthesis, are becoming limiting factors in the rapid iteration of designs. To mitigate these emerging constraints, multiple efforts have been undertaken to develop an ML-based surrogate model that estimates resource usage of ML accelerator architectures. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of over 680,000 fully connected and convolutional neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, and the average performance across a subset of the dataset. Additionally, we introduce GNN- and transformer-based surrogate models that predict latency and resources for ML accelerators. We present the architecture and performance of the models and find that the models generally predict latency and resources for the 75% percentile within several percent of the synthesized resources on the synthetic test dataset.
Figures
Forward citations
Cited by 1 Pith paper
-
DiffHLS: Differential Learning for High-Level Synthesis QoR Prediction with GNNs and LLM Code Embeddings
DiffHLS predicts HLS QoR via differential learning: separate GNN+LLM models for kernel baseline and design delta are composed to yield the final estimate, showing lower MAPE than GNN baselines on PolyBench.
Reference graph
Works this paper leans on
-
[1]
Stefan Abi-Karam, Rishov Sarkar, Allison Seigler, Sean Lowe, Zhigang Wei, Hanqiu Chen, Nanditha Rao, Lizy John, Aman Arora, and Cong Hao
-
[2]
H Abidi, A Boveia, V Cavaliere, D Furletov, A Gekow, CW Kalderon, and S Yoo. 2022. Charged Particle Tracking with Machine Learning on FPGAs. (2022). arXiv:2212.02348
Pith/arXiv arXiv 2022
-
[3]
2024.Vitis High-Level Synthesis User Guide (UG1399)(2024.2 ed.)
Advanced Micro Devices (Xilinx). 2024.Vitis High-Level Synthesis User Guide (UG1399)(2024.2 ed.). Advanced Micro Devices. https://docs.amd. com/r/en-US/ug1399-vitis-hls
2024
-
[4]
Jimmy Lei Ba, Jamie Ryan Kiros, and Geoffrey E Hinton. 2016. Layer Normalization
2016
-
[5]
Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, and Jason Cong. 2023. Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs. InAdvances in Neural Information Processing Systems, A. Oh, T. Naumann, A. Globerson, K. Saenko, M. Hardt, and S. Levine (Eds.), Vol. 36. Curran Associates, Inc., 45288. https://proceedin...
2023
-
[6]
Gergö Barany. 2017. Liveness-driven random program generation. InInternational Symposium on Logic-Based Program Synthesis and Transformation. Springer, 112–127
2017
-
[7]
Hendrik Borras, Giuseppe Di Guglielmo, Javier Duarte, Nicolò Ghielmetti, Ben Hawks, Scott Hauck, Shih-Chieh Hsu, Ryan Kastner, Jason Liang, Andres Meza, et al. 2022. Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark. In3rd Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench) at 5th Conference on Machine Learning and ...
Pith/arXiv arXiv 2022
-
[8]
Shaked Brody, Uri Alon, and Eran Yahav. 2022. How Attentive are Graph Attention Networks?. InInternational Conference on Learning Representations. arXiv. arXiv:2105.14491 https://openreview.net/forum?id=F72ximsx7C1
Pith/arXiv arXiv 2022
-
[9]
Javier Campos, Jovan Mitrevski, Nhan Tran, Zhen Dong, Amir Gholaminejad, Michael W Mahoney, and Javier Duarte. 2024. End-to-end codesign of Hessian-aware quantized neural networks for FPGAs.ACM Trans. Reconfigurable Technol. Syst.17, 3 (2024), 1. arXiv:2304.06745 doi:10.1145/3662000
Pith/arXiv arXiv 2024
-
[10]
Chao Chen, Bruno da Silva, Chenxi Yang, Caiyun Ma, Jianqing Li, and Chengyu Liu. 2023. AutoMLP: A framework for the acceleration of multi-layer perceptron models on FPGAs for real-time atrial fibrillation disease detection.IEEE Transactions on Biomedical Circuits and Systems(2023)
2023
-
[11]
Davide Chicco, Matthijs J Warrens, and Giuseppe Jurman. 2021. The coefficient of determination R-squared is more informative than SMAPE, MAE, MAPE, MSE and RMSE in regression analysis evaluation.PeerJ Comput. Sci.7 (2021), e623
2021
-
[12]
Claudionor N. Coelho Jr., Aki Kuusela, Shan Li, Hao Zhuang, Thea Aarrestad, Vladimir Loncar, Jennifer Ngadiuba, Maurizio Pierini, Adrian Alan Pol, and Sioni Summers. 2021. Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectors.Nat. Mach. Intell.3 (2021), 675. arXiv:2006.10159 doi:10.1038/s...
Pith/arXiv arXiv 2021
-
[13]
Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F.Y. Young, and Zhiru Zhang. 2018. Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. In2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 129–132. doi:10.1109/FCCM.2018.00029
arXiv 2018
-
[14]
Dana Diaconu, Lucian Petrica, Michaela Blott, and Miriam Leeser. 2022. Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations. In2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). 77–83. doi:10.1109/IPDPSW55747. 2022.00022
arXiv 2022
-
[15]
Javier Duarte, Song Han, Philip Harris, Sergo Jindariani, Edward Kreinar, Benjamin Kreis, Jennifer Ngadiuba, Maurizio Pierini, Ryan Rivera, Nhan Tran, et al . 2018. Fast inference of deep neural networks in FPGAs for particle physics.JINST13 (2018), P07027. arXiv:1804.06913 doi:10.1088/1748-0221/13/07/P07027
Pith/arXiv arXiv 2018
-
[16]
Javier Duarte, Nhan Tran, Ben Hawks, Christian Herwig, Jules Muhizi, Shvetank Prakash, and Vijay Janapa Reddi. 2022. FastML Science Benchmarks: Accelerating Real-Time Scientific Edge Machine Learning. In3rd Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench) at 5th Conference on Machine Learning and Systems (MLSys). arXiv:2207.07958
Pith/arXiv arXiv 2022
-
[17]
Farah et al Fahim. 2021. hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices. In1st TinyML Research Symposium. arXiv:2103.05579
Pith/arXiv arXiv 2021
-
[18]
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca Carloni, and Laura Pozzi. 2021. DB4HLS: A Database of High-Level Synthesis Design Space Explorations. arXiv:2101.00587 https://arxiv.org/abs/2101.00587
Pith/arXiv arXiv 2021
-
[19]
Matthias Fey and Jan Eric Lenssen. 2019. Fast Graph Representation Learning with PyTorch Geometric. InICLR 2019 (RLGM Workshop). arXiv. arXiv:1903.02428 doi:10.48550/arXiv.1903.02428
-
[20]
Berthié Gouin-Ferland, Mohammad Mehdi Rahimifar, Charles-Étienne Granger, Quentin Wingering, Ryan Coffee, and Audrey Corbeil Therrien
-
[21]
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada. 2009. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis.journal of information processing17 (2009), 242–254
2009
-
[22]
Usman Jamal, Zhuowei Li, Mihai T
M. Usman Jamal, Zhuowei Li, Mihai T. Lazarescu, and Luciano Lavagno. 2023. A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis.IEEE Access11 (2023), 85785–85798. doi:10.1109/ACCESS.2023.3303840
arXiv 2023
-
[23]
Diederik P. Kingma and Jimmy Ba. 2015. Adam: A Method for Stochastic Optimization. In3rd International Conference for Learning Representations. arXiv:1412.6980
Pith/arXiv arXiv 2015
-
[24]
Ilya Loshchilov and Frank Hutter. 2019. Decoupled Weight Decay Regularization. https://openreview.net/forum?id=Bkg6RiCqY7
2019
-
[25]
Jason Moss. 2024. xilinx-docker. https://gitlab.com/rjmoss/xilinx-docker
2024
-
[26]
Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, Alban Desmaison, Andreas Kopf, Edward Yang, Zachary DeVito, Martin Raison, Alykhan Tejani, Sasank Chilamkurthy, Benoit Steiner, Lu Fang, Junjie Bai, and Soumith Chintala. 2019. PyTorch: An Imperative Style, High...
Pith/arXiv arXiv 2019
-
[27]
Kedar Potdar, Taher Pardawala, and Chinmay Pai. 2017. A Comparative Study of Categorical Variable Encoding Techniques for Neural Network Classifiers.Int. J. Comput. Appl.175 (2017), 7
2017
-
[28]
Louis-Noel Pouchet and Tomofumi Yuki. 2018. PolyBench/C. https://sourceforge.net/projects/polybench/
2018
-
[29]
Hamza Ezzaoui Rahali, Mohammad Mehdi Rahimifar, Charles-Étienne Granger, Zhehui Wang, and Audrey C Therrien. 2024. Efficient compression at the edge for real-time data acquisition in a billion-pixel X-ray camera.Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment1058 (2024), 168829
2024
-
[30]
Mohammad Mehdi Rahimifar, Hamza Ezzaoui Rahali, and Audrey C Therrien. 2024. rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGA. (2024). arXiv:2408.05314
Pith/arXiv arXiv 2024
-
[31]
Brandon Reagen, Robert Adolf, Yakun Sophia Shao, Gu-Yeon Wei, and David Brooks. 2014. MachSuite: Benchmarks for accelerator design and customized architectures. In2014 IEEE International Symposium on Workload Characterization (IISWC). 110. doi:10.1109/IISWC.2014.6983050
arXiv 2014
-
[32]
Brandon Reagen, Robert Adolf, Yakun Sophia Shao, Gu-Yeon Wei, and David Brooks. 2014. Machsuite: Benchmarks for accelerator design and customized architectures. In2014 IEEE International Symposium on Workload Characterization (IISWC). IEEE, 110–119
2014
-
[33]
R. Sarkar, S. Abi-Karam, Y. He, L. Sathidevi, and C. Hao. 2023. FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference. In2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE Computer Society, Los Alamitos, CA, USA. arXiv:2204.13103 doi:10.1109/HPCA56546.2023.10071015
Pith/arXiv arXiv 2023
-
[34]
Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong. 2022. Automated Accelerator Optimization Aided by Graph Neural Networks. In 2022 59th ACM/IEEE Design Automation Conference (DAC)
2022
-
[35]
Gomez, Lukasz Kaiser, and Illia Polosukhin
Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N. Gomez, Lukasz Kaiser, and Illia Polosukhin. 2023. Attention Is All You Need. arXiv:1706.03762 [cs.CL] https://arxiv.org/abs/1706.03762
Pith/arXiv arXiv 2023
-
[36]
Petar Veli˘cković, Guillem Cucurull, Arantxa Casanova, Adriana Romero, Pietro Liò, and Yoshua Bengio. 2018. Graph Attention Networks. In International Conference on Learning Representations. arXiv:1710.10903 doi:10.48550/arXiv.1710.10903
-
[37]
Weil, Scott A
Sage A. Weil, Scott A. Brandt, Ethan L. Miller, Darrell D. E. Long, and Carlos Maltzahn. 2006. Ceph: a scalable, high-performance distributed file system. InProceedings of the 7th Symposium on Operating Systems Design and Implementation. USENIX Association, USA, 307
2006
-
[38]
Nan Wu, Hang Yang, Yuan Xie, Pan Li, and Cong Hao. 2022. High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. InProceedings of the 59th ACM/IEEE Design Automation Conference(San Francisco, California)(DAC ’22). Association for Computing Machinery, New York, NY, USA, 49–54. doi:10.1145/3489517.3530408
arXiv 2022
-
[39]
AMD Xilinx. 2023. Alveo U250 Datasheet. https://docs.amd.com/r/en-US/ds962-u200-u250/Alveo-Product-Details. Accessed: 2024-10-06. Manuscript submitted to ACM wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation 25 Appendices A Scatter Plots Fig. 13. Scatter plots of MLP predictions on the test set. The red line shows the ...
2023
-
[2022]
In2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)
Combining optimized quantization and machine learning for real-time data reduction at the edge. In2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC). IEEE, 1. Manuscript submitted to ACM 24 Hawks et al
-
[2024]
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond. (2024). arXiv:2405.00820
arXiv 2024
discussion (0)
Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.