AR-SFQ: Asynchronous Reset Library Using {\alpha}-Cell Design

Beyza Zeynep Ucpinar; Massoud Pedram; Mustafa Altay Karamuftuoglu; Sasan Razmkhah; Yasemin Kopur

REVIEW 3 major objections 6 minor 1 cited by

AR-SFQ: Asynchronous Reset Library Using {\alpha}-Cell Design

T0 review · 3 major / 6 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read Integrating a bidirectional α-cell gives RSFQ logic and memory cells an asynchronous reset, enabling each cell to execute ¬RES ∧ f(A,B) without extra area or bias overhead.

desk verdict A useful and plausibly working asynchronous reset extension of the group's own α-cell work, but the evidence base is thinner than the claims. read the letter →

arxiv 2501.09449 v1 pith:TSCJHXA6 submitted 2025-01-16 cond-mat.supr-con

Yasemin Kopur , Beyza Zeynep Ucpinar , Mustafa Altay Karamuftuoglu , Sasan Razmkhah , Massoud Pedram This is my paper · ORCID

classification cond-mat.supr-con

keywords RSFQsinglefluxquantumalpha-cellbidirectionalsignalpropagationasynchronousresetsuperconductorlogiccelllibrarystorage

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a bidirectional interconnect cell called the α-cell can be grafted onto ordinary RSFQ logic gates and memory cells to give each one an asynchronous reset: a pulse arriving through the output port reverses the stored data flow and returns the cell to its idle state. If true, this removes the need for a global clock or a separate reset network to clear pipeline stages, shift-register memory, and state machines, and it lets a single cell compute a reset-modified function such as $\neg\text{RES}\wedge f(A,B)$ without adding area or bias overhead. The authors support the claim with analog simulations of AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells, reporting parameter margins and reset timing windows for each.

What carries the argument

The α-cell is an interconnect cell with three inputs, two outputs, and asymmetric Josephson-junction loops that allow SFQ pulses to travel in both directions: forward it behaves as a Josephson transmission line, reverse it behaves as a confluence buffer performing parallel-to-serial conversion. It carries the argument by providing a reverse port through which a reset pulse can enter a logic or memory cell, decrement or clear the stored flux in the destructive-readout loop, and restore the cell to its idle state. The relevant physical mechanism is flux quantization in superconducting loops: stored flux is an integer multiple of $\Phi_0$, so a counter-propagating pulse can subtract one flux quantum, and the reset-modified function $\neg\text{RES}\wedge f(A,B)$ follows from the absence of inductive state in the reverse path.

What would settle it

Apply a reset pulse to an empty AND, OR, or XOR cell and then measure the loop current at the storage inductance; if any residual flux is stored (as the paper's multi-flux DRO does with negative-flux bias), the reverse path is stateful and the clean-reset claim fails. Alternatively, run a Monte Carlo yield simulation over the stated reset timing windows (e.g., AND reset between 6.84 ps before first input and 4.5 ps before clock, XOR between 15.14 ps and 10 ps) and count functional errors; any error at nominal bias would falsify the claimed reliability.

Watch

Extended reading notes

Core claim

The central discovery is that the α-cell's reverse signal path can be reused as a local reset mechanism. In each AR-SFQ cell, a reset pulse applied at the output pin travels backwards through the α-cell and discharges the flux stored in the cell's destructive-readout loop, reactivating the primary escape junctions and restoring the default state. Because the reverse path is designed without inductive elements, the reset is claimed to be memoryless: it does not store state in the reverse direction and does not generate a reverse pulse at the input port when the loop is empty. Functionally, every gate in the library executes $\neg\text{RES}\wedge f(A,B)$, and the same structure adds reset to DFF and TFF memory cells, gives the inverter a compact implementation using a multi-flux DRO with positive and negative flux cancellation, and turns the multi-flux DRO into a decrementable storage element that can hold up to four flux quanta and even store negative flux as a bias.

Load-bearing premise

The load-bearing premise is that a reset pulse travelling backward through the α-cell clears a gate's stored flux completely and leaves no state behind, so the cell always returns to its idle (0,0) or set state; if the reverse path can instead partially decrement stored flux or leave residual bias, the reset-modified functions $\neg\text{RES}\wedge f(A,B)$ would not hold for all input histories.

Editorial extensions

If this is right

Local reset of individual DFFs in a shift-register memory can clear a target address without shifting all bits through the chain, reducing clock cycles for memory rewrite.
Branch misprediction recovery can reset only the affected computational stages, preventing erroneous signals from propagating without a global reset.
Two α-DFF pairs with crossed reset outputs produce $A\wedge\neg B$ and $B\wedge\neg A$ and, merged through one CBU, yield $A\oplus B$, giving three functions from the same components.
The multi-flux DRO with α reset can act as an up-down counter, store up to four bits plus negative-flux bias, and support bidirectional counting.
The inverter is implemented more compactly by using the reset path as a negative-flux input to an MDRO, with higher error margin than a standard RSFQ inverter.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the memoryless reverse path holds, the α-reset pattern may extend to any DRO-style RSFQ cell, but the paper's own XOR timing violation (starred peak in Fig. 6) suggests that each cell's reset window, not the clock, becomes the new timing constraint that synthesis tools must satisfy.
The multi-flux DRO's demonstrated negative-flux storage implies that a reset pulse is physically a decrement by one flux quantum rather than an absolute clear; in cells whose loops can hold multiple quanta, an incomplete reset might leave residual bias, so the claimed clean idle state should be verified under multi-pulse reset sequences and process variation.
Combining α-reset DFFs to form AND-invert and XOR functions suggests a synthesis mapping where reset ports serve as logic inputs, not just control; this could reduce cell count for arithmetic datapaths, but it will require design tools that understand pulse-direction encoding.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The paper is a genuine, if incremental, extension of the group's own α-cell work: it systematically adds asynchronous reset to standard AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells, and it documents state machines, timing windows, and component values. That is a real contribution to the SFQ design library space, and the core idea—local reset without a global clock—is sensible and potentially useful for state machines and higher-fanin circuits.

What the paper does well: it gives concrete schematics with component values, reports critical margins for the logic gates, and shows analog simulation waveforms for the main cells. The state-machine descriptions for the DFF, TFF, and multi-flux DRO are clear. The architectural discussion about targeted resets in shift registers and branch prediction is plausible, even if speculative.

Where it is soft: the evidence outruns the claims. There is no Monte Carlo or process-variation analysis, no fabricated chip, no released netlists, and no margin values for the memory cells. The admitted XOR timing error (Fig. 6, star) is a red flag that should be explained. The paper also leans heavily on the group's own α-cell (ref [9]) and their qCS optimizer (ref [17]); that is not a problem per se, but it means independent verification is lacking.

On the stress-test concern: the negative-flux storage shown in §III.C is for a deliberately parameter-modified multi-flux DRO, not for the standard reset paths of the AND/OR gates, so I would not call it an outright internal contradiction. But the concern is fair as an unexamined risk. The authors claim the reverse path lacks inductive elements and therefore cannot retain state, yet they never show a simulation of a reset pulse arriving while a gate is already idle and then demonstrate that a subsequent operation is correct. Given that the reset mechanism does involve flux injection, that scenario should be explicitly tested. The paper currently asserts the behavior without providing the evidence.

The bottom line: this is a reasonable design-study paper for the superconducting electronics community. It is not ready for publication as-is, but it deserves peer review. A serious referee should ask for the missing margin analysis, explicit reset-on-idle simulations, netlists and process parameters, and a baseline comparison against conventional clocked reset. If those are added, the paper could be a useful library reference. If not, the claims should be scaled back to what is actually demonstrated.

Referee Report

3 major / 6 minor

Summary. The paper proposes an asynchronous reset RSFQ (AR-SFQ) cell library built around the α-cell, a bidirectional interconnect element previously introduced by the same group. The library includes AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells, each with an asynchronous reset signal applied through the α-cell. The central claim is that a reset pulse returns every cell to its idle state, so each gate executes the reset-modified function ¬RES ∧ f(A,B), and this is achieved without increasing area or bias overhead. Validation is performed with analog simulations, and component values and some critical margins are reported.

Significance. If correct, the library would be a practical contribution to RSFQ design, enabling localized asynchronous reset without a global clock and potentially simplifying state machines, branch prediction, and neuromorphic topologies. The manuscript has notable strengths: complete component lists for every cell, simulation waveforms for all cells, explicit critical margins and timing windows for the logic gates, and a clear statement of the intended logic function. These details make the design reproducible in principle. However, the central physical assumption that the reset path is non-stateful is in tension with the authors' own demonstration of negative-flux storage in the multi-flux DRO, and the reliability claims are not backed by process-variation or yield analysis. The work is therefore promising but needs substantial revision to establish correctness and robustness.

major comments (3)

[§III.C] The non-statefulness assumption for the reset path is contradicted by the manuscript's own results. Section II.B.1 states for the AND gate that 'the absence of inductive elements in the reverse direction, preventing it from retaining state information in the reverse direction,' but Section III.C, 'Negative pulse storage,' demonstrates that applying an α input with no prior data stores that input as negative flux in the multi-flux DRO loop. Since the reset port in every AR-SFQ cell is the same α-cell mechanism, a reset pulse arriving while a cell is already idle could write negative flux into the storage loop, corrupting the subsequent ¬RES ∧ f(A,B) behavior. No simulation evidence is provided that the reset path of the AND, OR, XOR, DFF, or TFF is non-stateful under idle conditions; the admitted XOR timing violation (Fig. 6, star) is consistent with exactly this failure mode. This is a load-bearing correctness issue, not a margin or timing concern.
[Conclusion] The manuscript claims reliability and correct functionality via analog simulations, but no margin values are given for the memory cells. Figure 10's caption states 'The circuit parameters and margin values are provided,' yet the figure lists only inductances and critical currents, with no margin or timing data for the DFF. Similarly, the TFF (Fig. 13) and multi-flux DRO (Fig. 16) lack margin values. No Monte Carlo or process-variation analysis appears anywhere in the paper. Since the reset mechanism's timing windows are given only for AND and XOR, the robustness of the reset path for OR, inverter, and all memory cells is unquantified, which is a significant gap for a cell-library paper.
[Conclusion] The conclusion states that the library is developed 'without increasing the overall area and bias overhead of individual cells,' but the manuscript provides no area, JJ-count, or bias-current comparison between the AR-SFQ cells and conventional RSFQ cells with reset functionality. The schematics show the α-cell added to each logic gate, which presumably adds junctions and wiring, so the claim is unsupported. A quantitative comparison of junction counts and bias current requirements is needed to substantiate this assertion.

minor comments (6)

[Fig. 10] The caption says margin values are provided, but the figure only gives component parameters; the margin values for the DFF are missing.
[References] References [11] and [16] appear to be the same paper (same title, same authors, same venue and year); [16] lacks volume/page details. This should be resolved.
[§II.B.2] The OR gate description is unclear about the effect of a reset signal that arrives before input data: it says the reset 'can suppress the first input signal' but also that if two pulses arrive after a premature reset the output is still logic-1. The exact intended behavior and timing constraints should be stated more precisely.
[§IV] The description of the α-DFF-based XOR (Fig. 19) would benefit from a timing diagram or explicit truth-table demonstration, since the claimed generation of A ∧ ¬B, B ∧ ¬A, and A ⊕ B from two DFFs and two α-cells is not obvious from the text alone.
[Abstract] The acronym is inconsistently given as AR-SFQ in the title/abstract and AR-RSFQ in the conclusion; please standardize.
There are several typographical and grammatical issues, e.g., 'the clock causes a large skew' in the abstract, 'whether' for 'whether' in §II.B.1, and 'α input' where 'an α input' is meant. A careful proofread is recommended.

Circularity Check

0 steps flagged · score 0.0 of 10

No construction-level circularity: the asynchronous reset behavior is demonstrated by time-domain analog simulations of each cell, not derived from a fitted input or a load-bearing self-citation chain.

full rationale

The AR-SFQ paper does not derive its central reset claim from an input that already contains it. The reset-modified function ¬RES ∧ f(A,B) is presented in the conclusion as the intended specification of the designed cells, and the paper supports it with time-domain analog simulations of the AND, OR, XOR, inverter, DFF, TFF, and multi-flux DRO cells (Figs. 2, 4, 6, 8, 11, 14, 17, 18), along with reported timing windows and critical margins obtained from those simulations. This is a design-verification chain, not a fit-then-predict cycle. The self-citations to the α-cell ([9]) and the qCS optimizer ([17]) are real but not load-bearing in a circular sense: the α-cell is re-exercised inside every simulated gate, and qCS is used to optimize component values rather than to supply the reset property as an assumption. The most serious concern is an internal-consistency risk, not circularity: §III.C states that 'applying an α input when no prior data is present results in the storage of this input as a negative flux in the loop,' while §II.B.1 asserts for the AND gate 'the absence of inductive elements in the reverse direction, preventing it from retaining state information in the reverse direction.' If the reverse reset path of the logic cells behaves like the multi-flux DRO's negative-flux storage, an idle cell could be left in a negative-flux state by a reset pulse and ¬RES ∧ f(A,B) could fail. That would be a correctness or soundness failure, but it is not an instance of the paper's derivation reducing to its own inputs, so it does not raise the circularity score.

Assumptions & free parameters 7 free parameters · 5 assumptions · 0 invented entities

The central claim rests on the assumed correctness of the α-cell behavior from ref [9], on RSFQ simulation conventions, and on a large set of cell-specific component values that are tuned by optimization rather than derived. The memory and inverter cells depend even more heavily on undocumented margin behavior.

free parameters (7)

AND gate L and J values = see Fig. 1
Tuned manually and by qCS optimization to satisfy reset timing and margin [-26,22]% for J9.
OR gate L and J values = see Fig. 3
Tuned manually and optimized; margin [-29,50]% dominated by L6 and RB2.
XOR gate L and J values = see Fig. 5
Tuned and optimized; margins [-26,35]% for J5 and [-28,31]% for J6.
Inverter (MDRO) L and J values = inherited from Fig. 16 (multi-flux DRO)
Used as inverter with alpha cell providing negative flux; no separate margin reported.
DFF L and J values = see Fig. 10
The text says margin values are provided in Fig. 10, but the caption lists only configuration; functionality with α reset shown in Fig. 11.
TFF L and J values = see Fig. 13
Tuned to support toggle and α reset behavior; no margin values reported.
Multi-flux DRO L and J values = see Fig. 16
Adjusted so IcL > 4Φ0 for 4-bit storage and α reset or negative storage; no margin analysis reported.

assumptions (5)

standard math RSFQ pulse representation and clocked cell behavior are standard and captured by the simulation tool.
The paper assumes the usual RSFQ conventions (pulse equals logic 1, clock needed except for reset) throughout.
domain assumption The α-cell, characterized in ref [9] by the same group, behaves as a bidirectional JTL/CBU under the new loading and timing conditions.
Every reset operation depends on a reverse pulse propagating through the α-cell without corrupting the stored state; this is not re-derived here.
domain assumption The reverse path of the AND, OR, and XOR gates contains no inductive elements, so the reset pulse does not retain state in the reverse direction.
Stated in §II.B.1; if false, the clean reset to idle state fails. The multi-flux DRO section shows reverse pulses can decrement stored flux, so the assumption is context-dependent.
domain assumption The qCS optimization from ref [17] produces valid parameter margins for each cell.
The paper relies on the in-house optimizer without releasing code or certificates; no independent check is provided.
standard math IcL > 4Φ0 realizes four flux quanta of storage in the multi-flux DRO.
Uses flux quantization in a superconducting loop; a standard RSFQ design rule.

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Cite this review

Pith. "Pith review of AR-SFQ: Asynchronous Reset Library Using {\alpha}-Cell Design." pith.science (2026). https://pith.science/paper/TSCJHXA6

@misc{pith2026250109449,
  author       = {Pith},
  title        = {Pith review of: AR-SFQ: Asynchronous Reset Library Using \alpha-Cell Design},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/TSCJHXA6}},
  note         = {Machine review of arXiv:2501.09449}
}

read the original abstract

Rapid Single Flux Quantum (RSFQ) circuits are the most evolved superconductor logic family. However, the need to clock each cell and the deep pipeline causes a complex clock network with a large skew. This results in lower throughput and high latency in RSFQ. This work introduces an asynchronous RSFQ cell library that incorporates the {\alpha}-cell, enabling bidirectional signal paths in RSFQ circuits. The {\alpha}-cell mitigates the need for a large clock network by allowing reverse signal flow, minimizing routing, and enabling compact circuit designs. We demonstrate the library's reliability and efficiency by analog simulations and using in-house optimization tools. The asynchronous reset RSFQ (AR-SFQ) will enable efficient implementation of scalable, high-performance computing frameworks, such as state machines, neuromorphic computing, and higher fan-in circuits.

Figures

Figures reproduced from arXiv: 2501.09449 by the authors.

**Figure 3.** Schematic of the or gate. Configuration: L1=1.58 pH, L2=1.36 pH, L3=1.94 pH, L4=2.19 pH, L5=5.22 pH, L6=9.27 pH, L7=1.45 pH, L8=9.09 pH, L9=1.38 pH, J1=163.46 µA, J2=178.41 µA, J3=109.23 µA, J4=113.13 µA, J5=94.038 µA, J6=106.62 µA, J7=118.01 µA, J8=91.04 µA, J9=123.86 µA [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Simulation of the or gate. 28,31] % for J5 and J6, respectively. While J5 is the mentioned escape junction for the logic(1,1) damping mechanism, J6 is the clock escape junction. The XOR gate also requires the reset signal to be applied within a defined timing window. The reset must be issued no earlier than 15.14 ps before the arrival of the first input signal and no later than 10 ps before the clock pulse (setup ti… view at source ↗

**Figure 5.** The critical margin for this gate is [-26,35] % and [- [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗

Figures from the paper (9 more)

**Figure 7.** Figure 7: Schematic of the inverter gate [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

**Figure 6.** Figure 6: Simulation of the xor cell. increased compactness compared to a standard RSFQ inverter and a higher error margin. The inverter schematic is shown in Fig.7, with simulation results in Fig.8, highlighting the circuit’s behavior under different input conditions. The MDRO…

**Figure 10.** Figure 10: B. Toggle Flip Flop (TFF) Toggle Flip-Flop is an essential component in RSFQ circuits, primarily serving as a frequency divider. The TFF operates by toggling its output state with each incoming pulse on its input. Specifically, when two input pulses are applied to th…

**Figure 12.** Figure 12: State machine of the TFF gate [PITH_FULL_IMAGE:figures/full_fig_p005_12.png]

**Figure 10.** Figure 10: Schematic of the dff gate. Configuration: L1=2.10 pH, L2=6.67 pH, L3=4.45 pH, L4=1.55 pH, J1=208.52 µA, J2=201.78 µA, J3=180.00 µA, J4=239.29 µA [PITH_FULL_IMAGE:figures/full_fig_p005_10.png]

**Figure 11.** Figure 11: Simulation of the dff cell. state. If another set signal arrives during the T state, an SFQ pulse is generated at the output. Conversely, if a reset signal is received while in the T state, the TFF reverts to the idle state, and the schematic representation of the Res…

**Figure 15.** Figure 15: State machine of the multiflux dro [PITH_FULL_IMAGE:figures/full_fig_p006_15.png]

**Figure 17.** Figure 17: Simulation of the multiflux dro cell. Negative pulse storage: The multi-flux DRO cell, as depicted in [PITH_FULL_IMAGE:figures/full_fig_p006_17.png]

**Figure 19.** Figure 19: The design of XOR operation with intermediate [PITH_FULL_IMAGE:figures/full_fig_p007_19.png]

Discussion (0). Continue with ORCID to comment.

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Reference graph

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.

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Placement and routing methods based on mixed wiring of jtls and ptls for rsfq circuits,

T. Dejima, K. Takagi, and N. Takagi, “Placement and routing methods based on mixed wiring of jtls and ptls for rsfq circuits,” in 2019 IEEE International Superconductive Electronics Conference (ISEC), 2019, pp. 1–3

work page 2019