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On two 127-qubit superconducting processors, a connectivity-optimized Toffoli gate achieves only 56–64% state fidelity on real hardware, versus 98–99% in noiseless simulation, with the drop varying by input state class.

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Benchmarking a decomposed Toffoli gate on IBM quantum hardware yields 56-64% state fidelities, but the claimed state-dependent error pattern is confounded by using different devices.

T0 review reviewed 2026-08-05 challenge →

load-bearing objection Useful raw numbers, unsupported headline claim: the state-dependent comparison is confounded by using different IBM processors for different states. the 4 major comments →

arxiv 2509.05395 v1 pith:VBUV7VRA submitted 2025-09-05 quant-ph

Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors

M. AbuGhanem This is my paper
classification quant-ph PACS 03.67.Lx03.67.-a03.67.Ac
keywords Toffoli gatesuperconducting quantum processorsstate-dependent error patternsquantum state tomographyquantum process tomographyNISQ devicesfidelity benchmarkingechoed cross-resonance gate
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports a hardware-aware fidelity benchmark of the three-qubit Toffoli (CCNOT) gate on two 127-qubit superconducting processors. Using a decomposition built from echoed cross-resonance gates and single-qubit rotations, the author measures output state fidelity for three input classes—GHZ, W, and uniform superposition—under noiseless simulation, noise-aware emulation, and real hardware. The central claim is that real hardware executes the gate at only 56–64% state fidelity, far below the 98–99% predicted in simulation, and that the size of the degradation depends on which input state is fed to the gate. The paper also reports process fidelity of about 99% in noiseless simulation and 80% under noise-aware emulation. If true, this quantifies the practical gap between decomposed multi-qubit gates and their ideal behavior, and it suggests that algorithm designers must treat input-state class as a performance variable on near-term quantum hardware.

Core claim

On the author's terms, the discovery is a measured map of Toffoli-gate fidelity as a function of environment and input state. For the GHZ input, state fidelity falls from 98.442% in noise-free simulation to 81.470% in noise-aware emulation to 56.368% on hardware; for W states the corresponding numbers are 98.739%, 79.900%, and 63.689%; for the uniform superposition over all three-qubit basis states, 99.490%, 85.469%, and 61.161%. Quantum process tomography on the same decomposition yields 98.976% process fidelity in noiseless simulation and 80.160% under noise-aware emulation; full process tomography on hardware was not run because the 1,728 required circuits were impractical. The author int

What carries the argument

The central object is the three-qubit Toffoli (CCNOT) gate, decomposed into a native-gate sequence of echoed cross-resonance (ECR) gates plus single-qubit rotations (X, Rz, and sqrt-X) that respects the heavy-hexagonal connectivity of the 127-qubit processors. The measurement machinery is quantum state tomography (QST), which reconstructs the output density matrix from Pauli-basis measurements, and quantum process tomography (QPT), which reconstructs the process matrix via 12^3 circuits; the fidelity metric is the standard state fidelity between density operators and the average gate fidelity derived from it. This machinery carries the argument because the paper's central numbers are these r

Load-bearing premise

The fidelity differences attributed to input-state class assume the two processors are comparable in noise; because each state class was run on a different device, device quality could fully explain the pattern.

What would settle it

Run all three input-state classes on the same 127-qubit device, or swap which device handles which state class; if the fidelity ordering tracks each device's median two-qubit error rate instead of the state class, the state-dependence claim is refuted.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • A circuit designer who composes Toffoli gates on current 127-qubit superconducting hardware should expect roughly 56–64% state fidelity per gate for entanglement-heavy or superposition inputs, not the 98–99% predicted by noiseless simulation.
  • Input-state class becomes a first-order performance parameter: GHZ, W, and uniform-superposition inputs do not degrade identically, so benchmarks and error-mitigation strategies should be state-aware.
  • Noise-aware emulation predicts 80–85% fidelity and therefore overestimates real hardware by roughly 20–25 percentage points, so hardware-in-the-loop testing remains necessary for three-qubit gates.
  • Because full QPT on three qubits requires 1,728 circuits and was not performed on hardware, certification of process-level performance for multi-qubit gates will need lighter-weight protocols.
  • Algorithms that rely on Toffoli gates—quantum arithmetic, Grover search, and error-correction circuits—must budget for a per-gate fidelity cost far above what single- and two-qubit gate error rates would suggest.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The paper's hardware runs place the GHZ and W measurements on one processor and the uniform-superposition measurement on a second processor with a different median two-qubit error rate; because the state class and device are not crossed, the reported 'state-dependent' ordering is not uniquely attributable to state class. Re-running all three states on both devices would separate the effects.
  • The gap between noise-aware emulation (80–85%) and hardware (56–64%) suggests the emulator's noise model omits correlated errors, crosstalk, and drift; an emulator calibrated with day-of-run device error rates and pulse schedules could test whether hardware numbers are reproducible.
  • The paper notes but did not execute full QPT on hardware because 1,728 circuits were impractical; a randomized-benchmarking-style protocol would give a hardware process fidelity at a fraction of that cost.
  • A citation placeholder appears where the ECR-based decomposition is introduced, so the origin of the executed decomposition needs to be pinned down before reproducing the work.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper reports an experimental characterization of a connectivity-compliant Toffoli-gate decomposition on IBM 127-qubit superconducting processors. Quantum state tomography is used to estimate output state fidelities for three input classes—GHZ, W, and uniform superposition—under noise-free simulation, noise-aware emulation, and real hardware execution; quantum process tomography is performed only in simulation and emulation. The headline numbers are state fidelities of 98.4–99.5% (noise-free), 79.9–85.5% (emulation), and 56.4–63.7% (hardware), and the abstract claims these 'empirically characterize state-dependent error patterns in multi-qubit circuits.'

Significance. If the central claim were supported, the paper would be a useful benchmark of a practical Toffoli decomposition on current superconducting hardware, and the distinction between simulation, emulation, and hardware fidelities would be informative for circuit designers. The raw hardware numbers are plausible single-run measurements and the tables of device calibration data are a useful record. However, the state-dependence claim is the main contribution, and as presented it is not supported: the hardware measurements for different input states were taken on different devices with different calibrations, and no uncertainty estimates are given. The paper therefore does not currently deliver its advertised empirical conclusion, although the underlying measurement campaign could in principle be revised to do so.

major comments (4)
  1. [Section III / Table I] The hardware runs for GHZ and W states were performed on ibm_sherbrooke, while the uniform-superposition run was performed on ibm_brisbane (Table I and Section V). These devices differ in median ECR error (7.56e-3 vs 8.32e-3), coherence times (T1 272.21 vs 242.99 µs), and readout length (1,244 vs 4,000 ns). Input-state class and device are therefore perfectly confounded: the ordering 56.368% (GHZ), 63.689% (W), 61.161% (uniform) cannot be attributed to state dependence. A same-device, same-calibration comparison, or an explicit statistical adjustment for device effects, is required before the headline 'state-dependent error patterns' claim can be made.
  2. [Section III C / Table I] The text states that 'uncertainty estimates were derived' (Section III C), but no error bars, confidence intervals, or repeated runs are reported anywhere in Table I or the figures. The 'noise-free' fidelities are already only 98–99.5% because of finite-shot sampling, so the hardware differences (e.g., 61.161% vs 63.689%) are not tested against sampling noise. Without uncertainties, the reported fidelity ordering is not statistically meaningful.
  3. [Section IV / Conclusion] The conclusion that 'entangled states' degrade more than 'simpler superpositions' is internally inconsistent with Table I: the W state is entangled yet outperforms the uniform superposition on hardware (63.689% vs 61.161%). Even before the device confound is considered, the data do not show a consistent state-dependence pattern, so the narrative overstates and misstates the results.
  4. [Section III A / Figure 9] The 'noise-aware quantum emulation' results appear to be based on FakePerth() (Figure 9), a 27-qubit fake backend, rather than on a noise model calibrated to the 127-qubit ibm_sherbrooke/ibm_brisbane devices used for the hardware runs. If so, the emulation-to-hardware comparison is not apples-to-apples. The emulator backend and its noise model must be specified; otherwise the quantitative gap between emulation and hardware (Section IV) is not interpretable.
minor comments (4)
  1. [General] The manuscript has numerous duplicated passages, misnumbered figures (several Figures 3–5, a 'Figure 14' that appears as Figure 11), and unresolved citation placeholders such as '[?]' in Sections II C and in the captions of Figures 4–5. The text needs careful editorial cleanup.
  2. [Table I footnote] The footnote correctly states that 'noise-free' fidelities below 100% are due to finite-shot sampling. This should be reflected in the main text terminology: calling 98–99.5% values 'fidelities' without this caveat is misleading.
  3. [Section V] Readout errors are documented in Tables II–IV but are not corrected or mitigated in the reported state fidelities. Since the GHZ/W/uniform runs used very different readout lengths (1,244 ns vs 4,000 ns), the readout contribution to the reported fidelities should be explicitly acknowledged in the error analysis.
  4. [Section IV] The sentence 'The missing hardware process fidelity measurements would likely show even more severe degradation' is speculative and should be removed or clearly labeled as a conjecture.

Circularity Check

0 steps flagged

No circularity: fidelity numbers are direct measurements; only a minor self-citation to the underlying Toffoli decomposition is present.

full rationale

This is a benchmarking paper. The Toffoli decomposition is taken from the author's earlier ECR-based work (ref. [108]) and then independently measured by QST/QPT on a noise-free simulator, a noise-aware emulator, and two IBM 127-qubit devices. The reported 98.4%/81.5%/56.4% etc. are experimental outputs, not quantities derived from the input decomposition; no parameter is fitted to those outputs and then renamed a prediction. The footnote in Table I explicitly attributes sub-100% 'noise-free' fidelity to finite-shot sampling, so the simulator column is not an independent theoretical prediction. The emulator uses an external Qiskit noise model, so the emulation column is not the paper's own fit. The only load-bearing self-citation is the gate decomposition itself, and citing the construction of the object under test is normal. There is no equation in which a claimed result is defined in terms of the data it purports to explain. The more serious issues — the device/state confound (GHZ and W on ibm_sherbrooke, uniform on ibm_brisbane, Tables I–IV) and the missing [?] reference for the decomposition validation — are threats to validity and completeness, not circular reductions. Accordingly no circular step is identified; score 1 reflects the presence of a minor self-citation, not load-bearing circularity.

Axiom & Free-Parameter Ledger

0 free parameters · 5 axioms · 0 invented entities

The central measurement rests on the validity of the noise emulator, the interchangeability of the two IBM devices, and the assumption that raw QST fidelities isolate the gate. None of these are established in the paper.

axioms (5)
  • domain assumption The two IBM processors (ibm_sherbrooke and ibm_brisbane) have effectively equivalent noise characteristics, so cross-device fidelity differences can be attributed to input state class.
    This is assumed when comparing GHZ (98.4/81.5/56.4), W (98.7/79.9/63.7), and uniform (99.5/85.5/61.2) across different devices in Table I. No attempt is made to control for device identity.
  • domain assumption The noisy emulator (FakePerth or similar) accurately reproduces the real hardware noise channel, so QPT results in emulation are valid proxies for hardware process fidelity.
    The paper reports QPT process fidelity only in noise-free and noise-aware emulation (Section IV, Figure 9), and the missing hardware QPT is inferred to have 'even more severe degradation'.
  • domain assumption QST with finite shots yields unbiased fidelity estimates, and quoted fidelities are exact despite sampling noise.
    The paper says 'uncertainty estimates were derived' but reports no error bars, treating tens of thousands of shots as sufficient for point estimates.
  • standard math The decomposition in Figure 5 exactly implements the Toffoli gate when composed with the specified single-qubit gates.
    The decomposition is taken from prior work [108] and is not verified in this paper (e.g., no process matrix on hardware to confirm the unitary).
  • domain assumption Reported hardware state fidelities can be interpreted as Toffoli gate fidelity, despite including state preparation and readout errors in the QST pipeline.
    The circuit prepares a state, applies the Toffoli, and measures; no SPAM calibration or error mitigation is applied, yet the text calls these 'gate' fidelities.

reviewed 2026-08-05 · how reviews work

0 comments
Cite this review

Pith. "Pith review of Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors." pith.science (2026). https://pith.science/paper/VBUV7VRA

@misc{pith2026250905395,
  author       = {Pith},
  title        = {Pith review of: Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/VBUV7VRA}},
  note         = {Machine review of arXiv:2509.05395}
}
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read the original abstract

High-fidelity multi-qubit gates are a critical resource for near-term quantum computing, as they underpin the execution of both quantum algorithms and fault-tolerant protocols. The Toffoli gate (CCNOT), in particular, plays a central role in quantum error correction and quantum arithmetic, yet its efficient implementation on current quantum hardware remains limited by noise and connectivity constraints. In this work, we present a hardware-aware characterization of the Toffoli gate using optimized, connectivity-compliant decompositions executed on IBM's 127-qubit superconducting quantum processors. Our study integrates state preparation, gate synthesis, and quantum state/process tomography (QST/QPT) to evaluate fidelity across three distinct classes of input states: Greenberger-Horne-Zeilinger (GHZ), W, and the uniform superposition of all three-qubit computational basis states -- under noise-free simulation, noise-aware emulation, and real hardware execution. For GHZ states, we report state fidelities of 98.442% (noise-free simulation), 81.470% (noise-aware quantum emulation), and 56.368% (real quantum hardware). For W states, state fidelities are 98.739%, 79.900%, and 63.689%, respectively, and for the uniform superposition state, we observe state fidelities of 99.490%, 85.469%, and 61.161%. Comparative QPT experiments yield process fidelities of 98.976% (noise-free) and 80.160% (noise-aware emulation). Our results empirically characterize state-dependent error patterns in multi-qubit circuits and quantify trade-offs between gate decomposition strategies and native hardware performance, offering practical insights for scalable, hardware-efficient quantum circuit design.

Figures

Figures reproduced from arXiv: 2509.05395 by M. AbuGhanem.

Figure 1
Figure 1. Figure 1: FIG. 1. A standard decomposition of a three-qubit CCX (Toffoli) gate requires six CNOT gates along with multiple single-qubit [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. A decomposition of a three-qubit CCX (Toffoli) gate requires 8 CNOT gates along with multiple single-qubit gates [ ff [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Hardware-aware quantum circuit implementation of the Toffoli (CCNOT) gate for linearly connected qubit archi compiled for quantum processors with nearest-neighbor connectivity. Our implementation utilizes only the following single bit tthhttitR() fZittid th √X tfititiTht [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Hardwareaware quantum circuit synthesis of a Tooli gate (CCNOT) using echoed crossresonance (ECR) gates and optimized single-qubit gates [41]The circuit demonstrates native gate decomposition for superconducting quantum processors FIG. 4. Hardware-aware quantum circuit synthesis of a Toffoli gate (CCNOT) using echoed cross-resonance (ECR) gates and [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. QST of the Tooli gate with input state prepared as the maximally entangled GHZ state ( ff FIG. 6. QST of the Toffoli gate with input state prepared as the maximally entangled GHZ state ( [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. QST of the Toffoli gate with input state prepared as W states ( √1 3 ( ff FIG. 7. QST of the Toffoli gate with input state prepared as W states ( [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. QST of the Toffoli gate with input state prepared as a uniform superposition of all three-qubit computational basis FIG. 8. QST of the Toffoli gate with input state prepared as a uniform superposition of all three-qubit computational basis [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. QPT experiments of the To FIG. 9. QPT experiments of the Toff [PITH_FULL_IMAGE:figures/full_fig_p011_12.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. Qubit connectivity and readout error map of the [PITH_FULL_IMAGE:figures/full_fig_p012_10.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14. Comparative distributions of qubit performance metrics across three quantum processors. Boxplots show measured FIG. 11. Comparative distributions of qubit performance metrics across the quantum processors. Boxplots show measured l(flflh) fh()f(f) d h( [PITH_FULL_IMAGE:figures/full_fig_p014_14.png] view at source ↗

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Forward citations

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This paper was first reviewed by deepseek-v4-flash on August 5, 2026.