Monolithic GaN Systems Combining Non-Volatile Memory and Analog Computing via Area-Ratio-Engineered Ferroelectric AlScN Gate Stacks

Brendan Hanrahan; Geonwook Yoo; Hyeong Jun Joo; Jong Min Park; Kieran Barrett-Snyder

REVIEW 3 major objections 5 minor 5 references

Monolithic GaN Systems Combining Non-Volatile Memory and Analog Computing via Area-Ratio-Engineered Ferroelectric AlScN Gate Stacks

T0 review · 3 major / 5 minor · reviewed 2026-07-10 · grok-4.5

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Area-ratio engineering of AlScN gate stacks lets one GaN transistor family serve as both multi-bit memory and analog frequency converter.

desk verdict Solid experimental device paper that turns intermediate-electrode length into a practical dual-use knob for AlScN FeHEMTs; records and first FVC are real, high-ratio retention is the soft spot. read the letter →

arxiv 2607.07577 v2 pith:YYEBEM6O submitted 2026-07-08 cond-mat.mtrl-sci

Hyeong Jun Joo , Jong Min Park , Kieran Barrett-Snyder , Brendan Hanrahan , Geonwook Yoo This is my paper · ORCID

classification cond-mat.mtrl-sci

keywords FerroelectricHEMTsAlScNarea-rationon-volatilememoryanalogsignalprocessingMFMISgatestackfrequency-to-voltageconverterGa

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

GaN transistors dominate high-power and radio-frequency electronics, yet still rely on separate silicon chips for non-volatile memory and control. This paper shows that a single design knob—the area ratio of the metal-ferroelectric-metal-insulator-semiconductor gate stack—turns ferroelectric AlScN GaN HEMTs into devices that can be tuned for either dense multi-bit memory or continuous analog signal processing. By lengthening the intermediate electrode, more of the gate voltage drops across the ferroelectric, producing a 27 V memory window, sub-60 mV/dec switching even on the forward sweep, and 4-bit multi-level cells that remain uniform across a 4 imes4 array. Larger ratios instead yield continuously tunable conductance that the authors use for multi-state inverters and the first GaN ferroelectric frequency-to-voltage converter, linear from 0.5 to 500 Hz. The result is a concrete path toward monolithic GaN systems that store configuration data and process analog signals on the same wide-bandgap platform already preferred for power and RF.

What carries the argument

Area-ratio (SMIS/SMFM) capacitive voltage division: lengthening the intermediate Pt electrode increases the fraction of VGS that appears across the AlScN, amplifying polarization switching and, together with 2DEG-pinned downward polarization, simultaneously enlarges the memory window and enables partial, analog-like polarization states.

What would settle it

Fabricate devices spanning the same area ratios but deliberately introduce a known interface trap density or floating-electrode leakage path and measure whether the claimed 27 V window, forward 27 mV/dec swing, and linear 0.5–500 Hz FVC response still appear as predicted by the pure capacitive-division model.

Watch

Extended reading notes

Core claim

Systematic scaling of the area ratio SMIS/SMFM in an AlScN-based MFMIS gate stack redistributes gate voltage so that low ratios (1–2) produce large, stable multi-bit memory windows while high ratios (4–8) produce continuously programmable conductance states usable for multi-state inverters and a linear frequency-to-voltage converter, all on the same GaN HEMT platform.

Load-bearing premise

That the simple series-capacitor voltage-division formula, using only the measured dielectric constants of HfO2 and AlScN, fully explains the observed polarization pinning and dual memory/analog behavior without unmodeled traps, leakage or series resistance taking over at high ratios.

Editorial extensions

If this is right

Low-ratio FeHEMTs can serve as high-density multi-bit non-volatile cells co-integrated with GaN power or RF stages, removing the need for separate silicon memory chips.
High-ratio devices enable single-transistor multi-state inverters and frequency-to-voltage converters on the same GaN wafer used for power switching.
The same area-ratio knob can be used to trade retention stability against continuous analog tunability within one process flow.
Monolithic GaN systems that store their own configuration data and perform local analog signal processing become architecturally feasible.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the voltage-division model holds at higher frequencies, the same stack could be adapted for RF reconfigurable matching networks that store their own bias state.
The retention degradation seen only at high ratios suggests a materials path—thinner barriers or charge-blocking interlayers—that could push the analog regime into true non-volatile multi-state storage.
Because the intermediate electrode length is a lithographic parameter, foundry-compatible multi-project-wafer runs could offer designers a menu of memory versus analog FeHEMTs without process changes.

Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

This is a clean experimental device paper. The new piece is not AlScN FeHEMTs or MFMIS stacks—those already exist—but the systematic use of intermediate Pt length (area-ratio SMIS/SMFM = 1–8) as one process knob that deliberately splits the same gate stack into robust 4-bit MLC memory (low ratios) versus continuously tunable analog conductance (high ratios). They back it with transfer curves, pulse maps, 4×4 array statistics, multi-state VTCs, and the first GaN ferroelectric frequency-to-voltage converter (0.5–500 Hz, 1.1 mV/Hz, R²=0.97).

What they do well: fabrication and electrical data are thorough. TEM/EDS confirm the stack; PUND loops show saturation; low-ratio devices give 12 V MW, 4-bit states, endurance to 1k cycles, retention >1k s, and good array uniformity even at VDS=0.5 mV. High-ratio devices deliver the analog demos. Voltage-division equations are standard electrostatics applied to measured εr values, not fitted to invent the MW. Citations cover prior GaN FeHEMTs and Si/IGZO FeNAND fairly; self-cites are process context. The dual-function claim is supported by the data they show.

Soft spots are real but proportional. High-ratio devices (the ones that enable the FVC) show clear erase-state retention collapse after ~100 s, which the paper itself attributes to 2DEG depolarization field plus floating-Pt leakage. The simple capacitor network does not fully isolate pure ferroelectric amplification from series resistance, incomplete depletion, or interface effects at ratios 4 and 8; the forward SS=27 mV/dec and 27 V MW therefore rest partly on unmodeled terms. That weakens the clean “design-knob” narrative for the analog regime, but does not erase the measured dual behavior or the low-ratio memory results. No circular math, no invented entities.

This is for GaN device and power/RF integration people who care about on-chip NVM and analog blocks without silicon peripherals. It deserves a serious referee; the data are there, the caveats are visible, and the systems angle is concrete. I would engage.

Referee Report

3 major / 5 minor

Summary. The manuscript reports AlScN-based MFMIS ferroelectric GaN HEMTs in which the geometric area ratio SMIS/SMFM is varied (1, 2, 4, 8) by changing intermediate Pt electrode length. Capacitive voltage division is used to argue that higher ratios increase the fraction of VGS dropped across AlScN, producing a large memory window (up to 27 V), forward subthreshold swing of 27 mV/dec attributed to 2DEG-pinned polarization reversal, 4-bit multi-level cell operation with 4 imes4 array uniformity at low ratios, and continuously tunable conductance at high ratios that enables multi-state inverters and a GaN ferroelectric frequency-to-voltage converter (0.5–500 Hz, 1.1 mV/Hz, R² = 0.97). TEM/EDS, bidirectional transfer curves, pulse maps, endurance/retention, array statistics, VTCs and FVC waveforms are presented to support dual memory/analog functionality on a single GaN platform.

Significance. If the dual-function claim holds, the work supplies a practical structural design knob (area ratio) that lets a single AlScN FeHEMT platform serve both high-density non-volatile storage and analog signal processing on a wide-bandgap technology already used for power and RF. The 4-bit MLC array data, low-VDS operation (0.5 mV), and first GaN ferroelectric FVC are concrete advances relative to prior GaN FeHEMTs and to Si/IGZO FeNAND benchmarks. The experimental breadth (four ratios, array maps, circuit demos) is a clear strength even if the electrostatic model remains incomplete.

major comments (3)

Energy-band discussion and the two equations after Fig. 1: the central claim that area-ratio engineering alone produces the record MW (27 V) and forward SS (27 mV/dec) rests on VMFM = VGS/(1 + CMFM/CMIS) with εr(HfO2)=19.3, εr(AlScN)=24. At ratios 4 and 8 the paper itself reports incomplete 2DEG depletion, series resistance from extended LPt, and floating-Pt leakage that degrades erase retention after ~100 s (Figs. 3f, S3f). Without quantitative separation of pure ferroelectric voltage amplification from interface traps, leakage or series-resistance effects, the attribution of the high-ratio metrics and the FVC-enabling analog states remains under-supported.
Fig. 2d and abstract: the “record” MW of 27 V and forward SS of 27 mV/dec are extracted from high-ratio devices whose retention is already shown to be unstable (Figs. 3f, S3f). The manuscript should either (i) restrict the record claims to the low-ratio regime that actually retains data, or (ii) supply additional measurements (e.g., PUND under the same bias conditions, floating-electrode potential monitoring, or trap spectroscopy) that isolate ferroelectric switching from the unmodeled terms.
Figs. 5g–i and S6–S7: the FVC demonstration is novel, yet the bipolar Reset/Set scheme (1 V / –16 V) and the need for periodic re-initialization are presented without a quantitative model linking pulse frequency to fractional polarization. A short circuit-level analysis or SPICE-equivalent that predicts the observed 1.1 mV/Hz gain and R² = 0.97 would strengthen the claim that the converter is a direct consequence of area-ratio-engineered conductance states rather than an empirical pulse-train result.

minor comments (5)

Fig. 2a and S2a: on-current and Ion/Ioff degrade with area ratio because of series resistance from LPt; this trade-off should be stated quantitatively in the main text rather than only in the SI.
Table S1: the comparison with Si/IGZO FeNAND is useful, but the VDS column for this work lists 0.005 V while the main text emphasizes 0.5 mV; align the numbers and note the corresponding current levels.
Notation: SMIS/SMFM is introduced without defining the geometric areas on the first occurrence; a brief parenthetical (SMIS = LPt × W, SMFM = LG × W) would help readers.
Fig. 1c TEM/EDS: the scale bar and layer thicknesses are hard to read; a higher-resolution inset or labeled thickness values would improve clarity.
References: several recent AlScN FeFET and GaN FeHEMT works (2024–2025) are cited; ensure the “first GaN-based ferroelectric FVC” claim is checked against any concurrent preprints.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: experimental device demonstration whose measured MW, SS, MLC and FVC results stand independently of the standard capacitive-division formulas used only for post-hoc explanation.

full rationale

The paper is an experimental materials/device study. Area-ratio (SMIS/SMFM) is a geometric design parameter realized by lithographically varying intermediate-electrode length LPt; the resulting FeHEMTs are fabricated and characterized by bidirectional transfer sweeps, pulse programming, array mapping and circuit-level FVC measurements. The voltage-division relations VMFM = VGS/(1+CMFM/CMIS) and CMIS/CMFM = (SMIS/SMFM)·(dMFM/dMIS)·(εMIS/εMFM) together with C-V-extracted permittivities are textbook electrostatics applied after the fact to rationalize why higher ratios enlarge the effective field on AlScN; they are not fitted to the reported 27 V MW, 27 mV/dec forward SS or 1.1 mV/Hz FVC gain, nor are those quantities predicted from the formulas. Self-citations to the authors’ earlier AlScN FeHEMT process papers supply fabrication context but are not load-bearing uniqueness theorems or ansätze that force the new claims. No step reduces a claimed prediction or first-principles result to its own inputs by construction. The work is therefore self-contained against external benchmarks and free of the enumerated circularity patterns.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

Experimental device paper; load-bearing content is measured electrical behavior under the standard electrostatic model of series MFMIS capacitors plus the known large remnant polarization of AlScN. Free parameters are the four discrete area-ratios chosen by design and the extracted dielectric constants; axioms are textbook capacitive division and the domain assumption that 2DEG charge pins AlScN polarization downward. No new physical entities are postulated.

free parameters (2)

area-ratio SMIS/SMFM = 1, 2, 4, 8
Discrete design values 1, 2, 4, 8 set by intermediate Pt electrode length; chosen to span memory-to-analog regimes rather than derived from first principles.
relative permittivity of HfO2 and AlScN = εr,HfO2=19.3, εr,AlScN=24
Extracted from C–V measurements and inserted into the voltage-division formula; numerical values directly set the predicted VMFM fraction.

assumptions (3)

standard math Applied gate voltage divides between MFM and MIS capacitors according to VMFM = VGS × 1/(1 + CMFM/CMIS) with C proportional to area/thickness × ε.
Standard series-capacitor electrostatics invoked in the energy-band and voltage-partition paragraphs.
domain assumption High-density 2DEG at the AlGaN/GaN interface generates a built-in field that pre-aligns and pins AlScN polarization downward.
Used to explain both the large negative bias needed for high-ratio devices and the forward-sweep negative-capacitance effect; treated as established for this heterostructure.
domain assumption Al0.7Sc0.3N sputtered on Pt retains large remnant polarization (>100 µC cm⁻²) and coercive field ~5 MV cm⁻¹ under the process conditions used.
Material property taken from prior AlScN literature and confirmed by the paper’s own P–V loops.

how reviews work

0 comments

Cite this review

Pith. "Pith review of Monolithic GaN Systems Combining Non-Volatile Memory and Analog Computing via Area-Ratio-Engineered Ferroelectric AlScN Gate Stacks." pith.science (2026). https://pith.science/paper/YYEBEM6O

@misc{pith2026260707577,
  author       = {Pith},
  title        = {Pith review of: Monolithic GaN Systems Combining Non-Volatile Memory and Analog Computing via Area-Ratio-Engineered Ferroelectric AlScN Gate Stacks},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YYEBEM6O}},
  note         = {Machine review of arXiv:2607.07577}
}

read the original abstract

Gallium nitride (GaN) transistors have become the platform of choice for power electronics and radio-frequency power amplifiers. To unlock capabilities beyond those of conventional GaN, integrating ferroelectric heterostructure has been considered toward memory, logic and reconfigurable systems. Here, we demonstrate ferroelectric GaN transistors employing an AlScN-based gate stack in which systematic engineering of the area-ratio (SMIS/SMFM) provides unified control over both memory and analog functionality. Precise modulation of the intermediate electrode length yields a record memory window of 27 V and a forward subthreshold swing of 27 mV/dec, driven by ferroelectric polarization reversal of a robust downward-polarization state pre-induced by two-dimensional electron gas. Low area-ratio devices (SMIS/SMFM = 1, 2) achieve 4-bit multi-level cell operation and excellent spatial uniformity across a fabricated 4 x 4 array, benchmarking favorably against established silicon and oxide ferroelectric architectures. High area-ratio devices (SMIS/SMFM = 4, 8) harness continuously tunable conductance states to demonstrate multi-state inverters and the first GaN-based ferroelectric frequency-to-voltage converter, delivering a linear frequency-voltage response across 0.5 - 500 Hz range with a conversion gain of 1.1 mV/Hz. This work establishes routes towards monolithically integrated GaN systems that combine non-volatile memory and analog signal processing on a platform inherently suited to high-power and radio-frequency applications.

Review history (2 revisions) →

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

5 extracted references · 5 canonical work pages

[1]

P.; Mishra, U

(1) Zhang, N.-Q.; Keller, S.; Parish, G.; Heikman, S.; DenBaars, S. P.; Mishra, U. K. High Breakdown GaN HEMT with Overlapping Gate Structure. IEEE Electron Device Letters 2000, 21 (9), 421–423. (2) Chu, R.; Corrion, A.; Chen, M.; Li, R.; Wong, D.; Zehnder, D.; Hughes, B.; Boutros, K. 1200-V Normally off GaN-on-Si Field-Effect Transistors with Low Dynamic...

work page 2000
[2]

Y.; Yeom, M

(9) Yang, J. Y.; Yeom, M. J.; Lee, J.; Lee, K.; Park, C.; Heo, J.; Yoo, G. Reconfigurable Radio‐Frequency High‐Electron Mobility Transistors via Ferroelectric‐Based Gallium Nitride Heterostructure. Adv. Electron. Mater. 2022, 8 (9), 2101406. (10) Wu, C.; Smith, J.; Datta, S.; Cao, Y.; Xie, J.; Beam, E.; Fay, P. Microwave Performance of Ferroelectric- Gate...

work page 2022
[3]

Y.; Yeom, M

(15) Park, M.; Yang, J. Y.; Yeom, M. J.; Bae, B.; Baek, Y.; Yoo, G.; Lee, K. An Artificial Neuromuscular Junction for Enhanced Reflexes and Oculomotor Dynamics Based on a Ferroelectric CuInP2S6/GaN HEMT. Sci. Adv. 2023, 9 (38), eadh9889. (16) Pradhan, D. K.; Moore, D. C.; Kim, G.; He, Y.; Musavigharavi, P.; Kim, K.-H.; Sharma, N.; Han, Z.; Du, X.; Puli, V...

work page 2023
[4]

C.; Trolier-McKinstry, S

(18) Wang, D.; Zheng, J.; Musavigharavi, P.; Zhu, W.; Foucher, A. C.; Trolier-McKinstry, S. E.; Stach, E. A.; Olsson, R. H. Ferroelectric Switching in Sub-20 nm Aluminum Scandium Nitride Thin Films. IEEE Electron Device Letters 2020, 41 (12), 1774–1777. (19) Chen, L.; Liu, C.; Li, M.; Song, W.; Wang, W.; Wang, Z.; Wang, N.; Zhu, Y. Scandium-Doped Aluminum...

work page 2020
[5]

MIFIS” to

46 (10), 1697-1700. (23) Fichtner, S.; Wolff, N.; Krishnamurthy, G.; Petraru, A.; Bohse, S.; Lofink, F.; Chemnitz, S.; Kohlstedt, H.; Kienle, L.; Wagner, B. Identifying and Overcoming the Interface Originating C-Axis Instability in Highly Sc Enhanced AlN for Piezoelectric Micro-Electromechanical Systems. J. Appl. Phys. 2017, 122 (3). (24) Fichtner, S.; Wo...

work page 2017

Pith tools

Reviewed July 10, 2026 · model on record in the stance chip above.

[1] [1]

P.; Mishra, U

(1) Zhang, N.-Q.; Keller, S.; Parish, G.; Heikman, S.; DenBaars, S. P.; Mishra, U. K. High Breakdown GaN HEMT with Overlapping Gate Structure. IEEE Electron Device Letters 2000, 21 (9), 421–423. (2) Chu, R.; Corrion, A.; Chen, M.; Li, R.; Wong, D.; Zehnder, D.; Hughes, B.; Boutros, K. 1200-V Normally off GaN-on-Si Field-Effect Transistors with Low Dynamic...

work page 2000

[2] [2]

Y.; Yeom, M

(9) Yang, J. Y.; Yeom, M. J.; Lee, J.; Lee, K.; Park, C.; Heo, J.; Yoo, G. Reconfigurable Radio‐Frequency High‐Electron Mobility Transistors via Ferroelectric‐Based Gallium Nitride Heterostructure. Adv. Electron. Mater. 2022, 8 (9), 2101406. (10) Wu, C.; Smith, J.; Datta, S.; Cao, Y.; Xie, J.; Beam, E.; Fay, P. Microwave Performance of Ferroelectric- Gate...

work page 2022

[3] [3]

Y.; Yeom, M

(15) Park, M.; Yang, J. Y.; Yeom, M. J.; Bae, B.; Baek, Y.; Yoo, G.; Lee, K. An Artificial Neuromuscular Junction for Enhanced Reflexes and Oculomotor Dynamics Based on a Ferroelectric CuInP2S6/GaN HEMT. Sci. Adv. 2023, 9 (38), eadh9889. (16) Pradhan, D. K.; Moore, D. C.; Kim, G.; He, Y.; Musavigharavi, P.; Kim, K.-H.; Sharma, N.; Han, Z.; Du, X.; Puli, V...

work page 2023

[4] [4]

C.; Trolier-McKinstry, S

(18) Wang, D.; Zheng, J.; Musavigharavi, P.; Zhu, W.; Foucher, A. C.; Trolier-McKinstry, S. E.; Stach, E. A.; Olsson, R. H. Ferroelectric Switching in Sub-20 nm Aluminum Scandium Nitride Thin Films. IEEE Electron Device Letters 2020, 41 (12), 1774–1777. (19) Chen, L.; Liu, C.; Li, M.; Song, W.; Wang, W.; Wang, Z.; Wang, N.; Zhu, Y. Scandium-Doped Aluminum...

work page 2020

[5] [5]

MIFIS” to

46 (10), 1697-1700. (23) Fichtner, S.; Wolff, N.; Krishnamurthy, G.; Petraru, A.; Bohse, S.; Lofink, F.; Chemnitz, S.; Kohlstedt, H.; Kienle, L.; Wagner, B. Identifying and Overcoming the Interface Originating C-Axis Instability in Highly Sc Enhanced AlN for Piezoelectric Micro-Electromechanical Systems. J. Appl. Phys. 2017, 122 (3). (24) Fichtner, S.; Wo...

work page 2017