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AnalogCoder: Analog Circuit Design via Training-Free Code Generation
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Analog circuit design is a significant task in modern chip technology, focusing on the selection of component types, connectivity, and parameters to ensure proper circuit functionality. Despite advances made by Large Language Models (LLMs) in digital circuit design, the complexity and scarcity of data in analog circuitry pose significant challenges. To mitigate these issues, we introduce AnalogCoder, the first training-free LLM agent for designing analog circuits through Python code generation. Firstly, AnalogCoder incorporates a feedback-enhanced flow with tailored domain-specific prompts, enabling the automated and self-correcting design of analog circuits with a high success rate. Secondly, it proposes a circuit tool library to archive successful designs as reusable modular sub-circuits, simplifying composite circuit creation. Thirdly, extensive experiments on a benchmark designed to cover a wide range of analog circuit tasks show that AnalogCoder outperforms other LLM-based methods. It has successfully designed 20 circuits, 5 more than standard GPT-4o. We believe AnalogCoder can significantly improve the labor-intensive chip design process, enabling non-experts to design analog circuits efficiently.
Forward citations
Cited by 14 Pith papers
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LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
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An LLM grounded in gm/Id transistor lookup tables sizes a two-stage op-amp to spec in five iterations, claimed about an order of magnitude faster than a senior engineer.
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MenTeR is a multi-agent LLM system that claims to automate RF/analog circuit netlist design, achieving 84.2% Pass@1 on a 24-task benchmark, but its self-generated testbench validation is shown to sometimes certify inc...
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LATENT: LLM-Augmented Trojan Insertion and Evaluation Framework for Analog Netlist Topologies
LATENT uses an LLM agent with detection feedback to insert stealthy analog Trojans into SPICE netlists, reporting narrower activation ranges and higher evasion against the SPICED detector.
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LIFT fine-tunes an LLM with graph-neural-network supervision to predict HLS pragma values, reporting lower latencies than AutoDSE, HARP, and GPT-4o on average, but with caveats in how averages are computed.
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DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining
A self-supervised graph encoder for device-level circuits improves prediction of circuit similarity, delays, and op-amp performance across analog and digital designs.
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Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Masala-CHAI automatically converts schematic images into SPICE netlists using object detection, line detection, and LLMs, producing a 7,500-example open dataset that boosts analog netlist generation Pass@1 by up to 46...
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A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction
An LLM multi-agent framework extracts sizing relationships from analog circuit papers to prune the optimizer's search space, reporting 2.32 to 26.6 times faster sizing and higher pass rates on three circuits.
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LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation
LaMAGIC2's SFCI representation cuts output token length from quadratic to linear and improves precision-sensitive generation of analog power converter topologies.
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AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection
AMSnet 2.0 is a 2,686-circuit analog schematic dataset, and the paper's U-Net plus split-merge pipeline extracts netlists and reconstructs digital schematics with F1 scores between 80.39 and 90.19.
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DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model
A document-to-circuit pipeline that combines layout analysis, LLM-driven parameter extraction, topology recognition, and space-mapping optimization to automate analog circuit design from datasheets.
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A Survey of Research in Large Language Models for Electronic Design Automation
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