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Shuttling for Scalable Trapped-Ion Quantum Computers

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arxiv 2402.14065 v2 pith:ZA2U55IW submitted 2024-02-21 quant-ph

classification quant-ph
keywords quantumshuttlingapproachcomputersdeviceqccdtimearchitecture
verification ladder T0 review T1 audit T2 compute T3 formal

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Trapped-ion quantum computers exhibit promising potential to provide platforms for high-quality qubits and reliable quantum computation. The Quantum Charge Coupled Device (QCCD) architecture is a leading example that offers a modular solution to enable the realization of scalable quantum computers, paving the way for practical quantum algorithms with large qubit numbers. Within these devices, ions can be shuttled (moved) throughout the trap and through different dedicated zones, e.g., a memory zone for storage and a processing zone for the actual computation. However, due to decoherence of the ions' quantum states, the qubits lose their quantum information over time. Thus, the required time steps of shuttling operations should be minimized. In this work, we propose a heuristic approach to determining an efficient shuttling schedule, which orchestrates the movement operations within the device. Given a quantum algorithm and a device architecture, the proposed approach produces shuttling schedules with a close-to-minimal amount of time steps for small-size QCCD architectures. For large scale QCCD devices, empirical evaluations show promising results with respect to quality of the solution as well as performance. An implementation of the proposed approach is publicly available as part of the open-source Munich Quantum Toolkit (MQT) at https://github.com/cda-tum/mqt-ion-shuttler.

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. S-SYNC: Shuttle and Swap Co-Optimization in Quantum Charge-Coupled Devices

    quant-ph 2025-05 conditional novelty 6.0 of 10

    S-SYNC unifies shuttling and SWAP operations into a single 'generic swap' on a static graph, and a greedy heuristic co-optimizes them to cut shuttling by 3.69x and raise success rate by 1.73x on average in simulation.

  2. Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems

    quant-ph 2025-05 conditional novelty 4.0 of 10

    A cross-architectural survey that categorizes qubit mapping and routing compilers for superconducting, trapped-ion, and neutral atom quantum hardware.

  3. Compilation Techniques for Spin Qubits in a Shuttling Bus Architecture

    quant-ph 2025-02 conditional novelty 4.0 of 10

    A Swap Return mapping heuristic with lookahead to future qubit interactions offers the best balance of low phase error and low execution time for shuttling-bus spin qubit architectures.

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