RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
Revisiting verilogeval: Newer llms, in-context learning, and specification-to-rtl tasks
7 Pith papers cite this work. Polarity classification is still indexing.
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2026 7representative citing papers
PDAGENT-BENCH is a new benchmark suite with 353 curated problems and an agentic workflow framework for evaluating LLM/VLM agents across five capability dimensions in VLSI physical design.
A self-trained multi-agent RL framework pairs Verilog and Python agents for oracle-free mutual verification in RTL generation and reports 75.0% / 80.1% pass@1 on VerilogEval V2 using 4B / 9B models.
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
RTL-BenchMT is an agent-assisted framework for dynamically maintaining RTL generation benchmarks by fixing flaws and reducing overfitting in LLM-based EDA applications.
Self-generated replay from language models nearly eliminates catastrophic forgetting during finetuning except when models are pretrained close to saturation.
LEGO extracts 42 standardized circuit skills from 11 open-source projects into a plug-and-play platform that raises Pass@1 from 0 to 0.805 on 41 hard VerilogEval v2 problems.
citing papers explorer
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RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
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PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design
PDAGENT-BENCH is a new benchmark suite with 353 curated problems and an agentic workflow framework for evaluating LLM/VLM agents across five capability dimensions in VLSI physical design.
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ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
A self-trained multi-agent RL framework pairs Verilog and Python agents for oracle-free mutual verification in RTL generation and reports 75.0% / 80.1% pass@1 on VerilogEval V2 using 4B / 9B models.
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Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
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RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
RTL-BenchMT is an agent-assisted framework for dynamically maintaining RTL generation benchmarks by fixing flaws and reducing overfitting in LLM-based EDA applications.
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Forgetting in Language Models: Capacity, Optimization, and Self-Generated Replay
Self-generated replay from language models nearly eliminates catastrophic forgetting during finetuning except when models are pretrained close to saturation.
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LEGO: An LLM Skill-Based Front-End Design Generation Platform
LEGO extracts 42 standardized circuit skills from 11 open-source projects into a plug-and-play platform that raises Pass@1 from 0 to 0.805 on 41 hard VerilogEval v2 problems.