Space-group codes—CSS codes whose stabilizers use crystallographic point-group symmetries—can be topologically ordered and geometrically local, and some match or beat bivariate-bicycle benchmarks.
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Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
10 Pith papers cite this work. Polarity classification is still indexing.
10
Pith papers citing it
abstract
We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes. We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations. Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.
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quant-ph 10years
2026 10representative citing papers
Coset-based generalization of 2BGA codes produces new quantum LDPC codes with parameters such as [[48,8,6]] and competitive noise thresholds under BP-OSD decoding.
A high-rate non-LDPC CSS code family with parameters [[n, √n, Θ(n^β)]] (β≈0.2823) is constructed from a base [[n0,2,d0]] code and provably admits a constant-depth complete transversal logical Clifford ISA of targeted S̄, √X̄, and CZ̄ gates.
Experimental breakeven demonstration of a qLDPC code encoding 4 logical qubits in 18 physical qubits on trapped ions, with up to 9x lower logical error rate than prior superconducting implementations.
Hardware experiment on IBM devices shows reset-free LUCI achieves logical X and Z error suppression ratios of 1.75(10) and 1.93(12), competitive with surface code despite halved syndrome density.
Concatenating quantum Reed-Solomon codes over the gross code via Galois qudits reaches teraquop regime at uniform 10^{-3} noise with reduced overhead.
PIQC proposes a distributed FTQC architecture based on molecular quantum nodes with photonic integration, nuclear registers, loss-tolerant entanglement, and Floquetified qLDPC codes.
Experimental demonstration of a multiplexing trapped-ion QPU using sample-and-hold circuits achieves motional heating rates below 1 phonon/s and expected gate errors below 10^{-4} for sampling intervals under 50 ms.
Resource estimation for magic-state distillation on silicon spin qubits finds 42% overhead reduction via optimized pulses and ~3x physical footprint reduction with biased codes versus surface code.
Biased-noise ancillas (phase flips only) in bicycle bivariate and cyclic hypergraph product QLDPC codes increase effective fault distance, reduce short loops, and improve logical error rate by nearly 10x at 2e-3 circuit noise when bit flips are 50x rarer.
citing papers explorer
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Topological Codes from Space Groups: A Route beyond Translation Invariance
Space-group codes—CSS codes whose stabilizers use crystallographic point-group symmetries—can be topologically ordered and geometrically local, and some match or beat bivariate-bicycle benchmarks.
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Breaking the bicycle frame: Coset-based quantum LDPC codes
Coset-based generalization of 2BGA codes produces new quantum LDPC codes with parameters such as [[48,8,6]] and competitive noise thresholds under BP-OSD decoding.
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Quantum Logic Codes: Complete Transversal Logical Clifford Instruction Sets for High-Rate Stabilizer Quantum Error Correcting Codes
A high-rate non-LDPC CSS code family with parameters [[n, √n, Θ(n^β)]] (β≈0.2823) is constructed from a base [[n0,2,d0]] code and provably admits a constant-depth complete transversal logical Clifford ISA of targeted S̄, √X̄, and CZ̄ gates.
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Breakeven demonstration of quantum low-density parity-check codes
Experimental breakeven demonstration of a qLDPC code encoding 4 logical qubits in 18 physical qubits on trapped ions, with up to 9x lower logical error rate than prior superconducting implementations.
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LUCI on IBM Hardware: Error Suppression with Almost Half Syndrome Density
Hardware experiment on IBM devices shows reset-free LUCI achieves logical X and Z error suppression ratios of 1.75(10) and 1.93(12), competitive with surface code despite halved syndrome density.
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Concatenating Algebraic Codes over High-Rate Quantum LDPC Codes
Concatenating quantum Reed-Solomon codes over the gross code via Galois qudits reaches teraquop regime at uniform 10^{-3} noise with reduced overhead.
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PIQC: Scalable Distributed Quantum Computing via Photonic Integration of Designed Molecular Quantum Nodes
PIQC proposes a distributed FTQC architecture based on molecular quantum nodes with photonic integration, nuclear registers, loss-tolerant entanglement, and Floquetified qLDPC codes.
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Demonstration of a Multiplexing Trapped Ion Quantum Processing Unit
Experimental demonstration of a multiplexing trapped-ion QPU using sample-and-hold circuits achieves motional heating rates below 1 phonon/s and expected gate errors below 10^{-4} for sampling intervals under 50 ms.
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Hardware-Tailored Resource Estimation for Magic-State Distillation on Silicon Spin Qubits
Resource estimation for magic-state distillation on silicon spin qubits finds 42% overhead reduction via optimized pulses and ~3x physical footprint reduction with biased codes versus surface code.
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Untangling QLDPC Codes with Biased Noise Ancilla
Biased-noise ancillas (phase flips only) in bicycle bivariate and cyclic hypergraph product QLDPC codes increase effective fault distance, reduce short loops, and improve logical error rate by nearly 10x at 2e-3 circuit noise when bit flips are 50x rarer.