Genetic programming evolves heterogeneous layer-specific scalar functions to approximate layer normalization in pre-trained ViTs, capturing 91.6% variance versus 70.2% for uniform baselines and recovering 84.25% ImageNet Top-1 accuracy after 20 epochs of adaptation.
High- Performance ARM-on-ARM Virtualization for Mul- ticore SystemC-TLM-Based Virtual Platforms
11 Pith papers cite this work. Polarity classification is still indexing.
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STG generates deterministic testbenches 720x faster than iterative LLM flows with higher coverage and fewer false passes, while serving as an 11x faster data curation engine with 127x less energy.
LLM agents run closed-loop design of photonic components and a full modulator by proposing, simulating, and refining against acceptance criteria.
A co-design framework using approximate matrix decomposition and genetic algorithms delivers 33% average latency reduction in TinyML CNN FPGA accelerators with 1.3% average accuracy loss versus standard systolic arrays.
ROA brick topology supplies PVT-robust 2.31 GHz SHIL that preserves 93-97% accuracy in 324-node OIM max-cut while ROSC-SHIL loses locking.
OptoSynthesizer is an integrated physical-design automation system that takes EPIC netlists and produces fabrication-ready, yield-optimized GDS layouts using AI-augmented inverse design, GPU-accelerated placement, and hierarchical curvy waveguide routing.
Using LLMs to encode logic condition tables into HDL code and decode back to tables mitigates hallucinations in hardware design automation.
Log_b Quant is an adjustable-base logarithmic quantization technique that outperforms tensor-wise asymmetric linear quantization at 4-bit precision on language model benchmarks while providing memory savings.
Prototype automates creation of virtual ECU twins via agentic feedback-driven modeling in SystemC to enable early shift-left software testing in automotive development.
Emulation is positioned as a high-throughput pre-silicon method for exposing SoC security issues under realistic hardware/software workloads, with organized workflows, challenges, and future directions.
The paper reviews energy-aware computing literature and constructs a taxonomy organized by hardware/software aspects, measurement, optimizations, scheduling, scaling, consolidation, federated learning, and cooling.
citing papers explorer
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Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation
Genetic programming evolves heterogeneous layer-specific scalar functions to approximate layer normalization in pre-trained ViTs, capturing 91.6% variance versus 70.2% for uniform baselines and recovering 84.25% ImageNet Top-1 accuracy after 20 epochs of adaptation.
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Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
STG generates deterministic testbenches 720x faster than iterative LLM flows with higher coverage and fewer false passes, while serving as an 11x faster data curation engine with 127x less energy.
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Autonomous agentic design for photonics
LLM agents run closed-loop design of photonic components and a full modulator by proposing, simulating, and refining against acceptance criteria.
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Co-Design of CNN Accelerators for TinyML using Approximate Matrix Decomposition
A co-design framework using approximate matrix decomposition and genetic algorithms delivers 33% average latency reduction in TinyML CNN FPGA accelerators with 1.3% average accuracy loss versus standard systolic arrays.
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ROA-Based Subharmonic Injection Locking for Oscillator-Based Ising Machines
ROA brick topology supplies PVT-robust 2.31 GHz SHIL that preserves 93-97% accuracy in 324-node OIM max-cut while ROSC-SHIL loses locking.
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End-to-End Physical Design Automation Flow for Yield-Optimized Inverse-Designed Large-Scale Electronic-Photonic Integrated Circuits
OptoSynthesizer is an integrated physical-design automation system that takes EPIC netlists and produces fabrication-ready, yield-optimized GDS layouts using AI-augmented inverse design, GPU-accelerated placement, and hierarchical curvy waveguide routing.
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Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation
Using LLMs to encode logic condition tables into HDL code and decode back to tables mitigates hallucinations in hardware design automation.
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$\text{Log}_\text{b}$Quant: Quantizing Language Models in Logarithmic Space
Log_b Quant is an adjustable-base logarithmic quantization technique that outperforms tensor-wise asymmetric linear quantization at 4-bit precision on language model benchmarks while providing memory savings.
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Toward Automated Virtual Electronic Control Unit (ECU) Twins for Shift-Left Automotive Software Testing
Prototype automates creation of virtual ECU twins via agentic feedback-driven modeling in SystemC to enable early shift-left software testing in automotive development.
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Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
Emulation is positioned as a high-throughput pre-silicon method for exposing SoC security issues under realistic hardware/software workloads, with organized workflows, challenges, and future directions.
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Energy-Aware Computing in the Year 2026
The paper reviews energy-aware computing literature and constructs a taxonomy organized by hardware/software aspects, measurement, optimizations, scheduling, scaling, consolidation, federated learning, and cooling.