Pith. sign in

REVIEW 3 major objections 5 minor 77 references

Advanced Clustering Framework for Semiconductor Image Analytics Integrating Deep TDA with Self-Supervised and Transfer Learning Techniques

T0 review · 3 major / 5 minor · reviewed 2026-08-16 · deepseek-v4-flash

Pith's one-line read A label-free pipeline that fuses topological shape features with self-supervised learning can cluster semiconductor wafer maps into groups matching known defect patterns.

desk verdict A plausible engineering integration of SSL+TDA+TL for wafer map clustering, but the undefined 'lowest score' used to pick the displayed TDA maps leaves the label-free discovery claim unproven. read the letter →

arxiv 2505.03848 v1 pith:DURDSPGB submitted 2025-05-05 cs.CV cs.AIcs.ETcs.LG

classification cs.CVcs.AIcs.ETcs.LG
keywords topologicaldataanalysisself-supervisedlearningtransfersemiconductorwafermapsunsupervisedclusteringdefectpatternrecognitionpersistenthomologyimage
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a single unsupervised pipeline can recover the defect structure of semiconductor wafer maps by combining three ingredients: topological descriptors computed from each image, contrastive self-supervised learning on augmented views, and a pretrained visual backbone transferred to new data. Tested on the real-world WM811K and Mixed WM38 benchmarks and on two synthetic datasets, the resulting clusters line up with known defect types such as edge-ring, scratch, and mixed-type failures even though no labels are used during training. If this holds, the approach offers a label-free route to defect discovery and process monitoring in manufacturing, where labeled wafer images are scarce and expensive. The paper also claims that transfer learning lets the same model cluster new datasets without retraining, and that a distilled version can run in resource-constrained environments.

What carries the argument

The load-bearing mechanism is a two-part embedding: each image is passed through a convolutional backbone while persistent homology, the multiscale counting of connected components and loops, is computed from the image and vectorized into a topological signature; the visual and topological feature vectors are concatenated and projected into a low-dimensional space trained with a contrastive loss that pulls augmented views of the same image together and pushes different images apart. After the self-supervised phase, a TDA-enhanced density-based clustering algorithm groups the embeddings. A pretrained version of the same backbone, trained at scale on diverse images, is used for zero-shot feature extraction on new datasets, and a distilled student model is offered for CPU deployment.

What would settle it

Take the WM811K set, run the full pipeline across every grid-search setting of the TDA parameters, and evaluate each resulting cluster map against held-out defect labels; if the lowest-score map is no more aligned with labels than the average map, or if a different unsupervised criterion selects maps with much worse alignment, the claim that the framework reliably finds label-aligned defect clusters would be falsified.

Watch

Extended reading notes

Core claim

On its own terms, the central discovery is that combining deep topological data analysis with self-supervised contrastive learning produces an embedding space in which unsupervised clustering of wafer map images recovers meaningful defect categories. The authors report that on the WM811K dataset the largest clusters are dominated by Edge-Loc and Center patterns, with Edge-Ring split across several clusters and rare Near-Full patterns pushed to the periphery of the topological map; on Mixed WM38 the method yields 31 clusters that separate single, mixed, and normal wafers; and on synthetic datasets a pretrained model separates good from faulty wafers and even splits faulty wafers by background process variation. In all cases the cluster assignments were computed without label information, and labels were used only to interpret the resulting clusters.

Load-bearing premise

The load-bearing assumption is that the unsupervised score used to choose the single TDA map for each dataset is a valid measure of clustering quality, so that the reported alignment with defect labels is a genuine prediction rather than a selected outcome.

Editorial extensions

If this is right

  • New or previously unseen wafer defect modes can be surfaced without any manual labeling, which would let fabs detect novel process excursions earlier.
  • A pretrained model can be applied zero-shot to a new fab's wafer map data, giving useful clusters before any task-specific retraining or label collection.
  • Mixed-type defect patterns, such as Donut+Edge-Loc+Loc, can be separated into distinct clusters, potentially pointing to different root causes even when the constituent defects overlap.
  • Rare but important patterns like Near-Full and Random are not averaged away: the topological maps isolate them in tail regions, which is the sensitivity a monitoring system needs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • I would expect the same architecture to transfer to other high-volume imaging domains, such as PCB or display inspection, because neither the contrastive objective nor the persistent-homology features are wafer-specific; that extension is not tested in the paper.
  • The paper does not ablate the TDA branch against a pure self-supervised baseline, so a reader cannot yet tell how much of the cluster alignment comes from topology versus the contrastive representation; a controlled comparison on the same datasets would settle that.
  • Because the reported maps are selected by an unsupervised lowest-score criterion after a grid search, the method's practical reliability would be strengthened by showing that nearby grid-search settings produce similar clusters; otherwise the displayed alignments may overstate typical performance.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents an unsupervised clustering framework, implemented in the proprietary DataRefiner platform, that combines deep Topological Data Analysis (TDA), self-supervised learning (SSL), and transfer learning (TL) for semiconductor wafer-map image analytics. The framework is evaluated on two open-source datasets (WM811K and Mixed WM38) and two synthetically generated datasets (SPVD and SWED). The authors report that the framework 'successfully identifies clusters aligned with defect patterns and process variations' without using labels during training, and they illustrate this with TDA network maps, per-cluster histograms, and segment-level visualizations. The claims are supported only by visual inspection of selected TDA maps; no quantitative clustering metrics, baselines, error bars, or statistical controls are provided.

Significance. If the central claim were quantitatively established, a label-free clustering method that integrates topological features with self-supervised and transfer-learned representations would be a practically valuable contribution to semiconductor manufacturing analytics, where labeled defect data are scarce and process variations are numerous. The paper has some strengths: the synthetic dataset generation procedures are described in unusual detail, the use of labels only after clustering is stated explicitly, and the Discussion candidly acknowledges that quantitative comparison with state-of-the-art methods is future work. However, as submitted, the empirical contribution is not established because the evidence consists of selected visualizations from a proprietary pipeline, with no quantitative cluster-quality measures and no reproducible algorithm description.

major comments (3)
  1. [Results, WM811K (Table 2, Fig. 7); also Mixed WM38 (Table 3, Fig. 14), SPVD (Table 4, Fig. 18), SWED (Table 5, Fig. 20)] No quantitative clustering metrics are reported. The paper does not provide NMI, ARI, purity, or any other measure of agreement between the discovered clusters and the known classes, nor does it report error bars, multiple runs, or statistical significance. The Discussion concedes that 'Quantitative comparison with other state-of-the-art unsupervised clustering techniques... would further benchmark performance.' Without such metrics, the assertion in the Abstract that the framework 'successfully identifies clusters aligned with defect patterns' is unsupported; the visual alignment shown in Figures 7, 14, 18, and 20 is anecdotal, and the histograms in Figures 8, 15, and 22 report class composition but not clustering accuracy.
  2. [Methods, Downstream Clustering; Datasets and Results] The clustering algorithm is a proprietary 'DataRefiner TDA-enhanced density-based clustering algorithm' that is not described in the paper. The Methods state that 'the core approach, conceived and implemented entirely by DataRefiner' relies on 'DataRefiner's proprietary algorithms and code bases,' and the downstream clustering step is described only as applying an in-house algorithm to the learned embeddings. The number of clusters, the stopping criterion, the density thresholds, and the meaning of the 'lowest score' are all unspecified. This makes the results impossible to reproduce or to assess independently, and it is a major obstacle to evaluating whether the reported clusters are meaningful or are artifacts of undocumented algorithmic choices.
  3. [Results, Figures 7, 14, 18, 20] Labels are used after clustering to name and color the clusters, and the captions state that labels were not part of the learning framework. Using labels for post hoc evaluation is legitimate, but naming each cluster by its most represented labeled class after seeing the class distribution can exaggerate apparent alignment when clusters are impure. The paper does not quantify how much of each cluster belongs to the dominant class, nor does it report the confusion between classes. For instance, the WM811K largest cluster is said to contain Edge-Loc and Center as major categories, while the caption of Figure 7 claims a cluster is composed 100% of Edge-Ring images; the relationship between these statements and the underlying cluster quality is not quantified. Quantitative agreement measures are needed to substantiate the claimed alignment.
minor comments (5)
  1. [Results, Mixed WM38] The text near Figure 16 refers to defect categories as 'a. C7:Near-Full and b. C9:Random', while the caption of Figure 14 labels C7 as Random and C9 as Near-Full; the class numbering is inconsistent and should be corrected.
  2. [Results, Mixed WM38] The sentence 'The resulting distribution of the failure categories per cluster is shown in Figure 8 Figure 15' contains a typo and should refer only to Figure 15.
  3. [Results, SPVD] The opening sentence says the evaluation tests 'Transfer Learning (TL) and semi-supervised learning (SSL) capabilities,' but SSL stands for self-supervised learning in the rest of the paper; the terminology should be made consistent.
  4. [Datasets, Mixed-WM38 and Table 3] The description of Mixed-WM38 says '8 categories of single defect types, 1 normal type and 3 kinds of mixed defect types,' which should read 29 mixed types; Table 3 also uses '37 failure categories' where '38 classes' would be clearer.
  5. [Throughout] The names 'Mixed 38WM' and 'Mixed WM38' are used interchangeably, and 'No of clusters' and 'networks' are used informally; the manuscript should standardize these terms.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: the SSL+Deep TDA+TL pipeline is trained without labels, and the reported cluster-label alignment is presented as an unsupervised result rather than a fitted quantity.

full rationale

The paper's central claim is that an unsupervised pipeline integrating SSL, Deep TDA, and TL produces clusters aligned with known wafer defect classes and process variations. The learning objective is a contrastive loss (NT-Xent) on augmented views plus precomputed TDA features; no loss term or training step uses the class labels. Labels appear only after clustering, to name and color clusters in the TDA maps, and the paper explicitly states that 'Labels of these images were not part of the learning framework.' The only self-citation (ref. 19, Giri & Lengyel 2023) is background on TDA in manufacturing and is not load-bearing. The main validity concern is that each dataset's single displayed TDA map is chosen by an undefined 'lowest score' after a grid search over Beta and metric (e.g., 'The TDA map with the lowest score is chosen for analysis'), and the paper concedes that quantitative comparison with other unsupervised methods is future work. That is a selection-bias and reproducibility limitation, not a demonstrated circular reduction: the paper does not state or exhibit a score that uses the labels, and no equation equates the reported alignment to the selection criterion. Under the requirement to exhibit a specific reduction before claiming circularity, no circular step is established.

Assumptions & free parameters 6 free parameters · 5 assumptions · 3 invented entities

The central claim rests on assumptions that TDA features concatenated with CNN features improve clustering, that the in-house algorithm's 'lowest score' selects a representative map, and that synthetic datasets validate transfer learning. None of these assumptions is ablated or defined. The proprietary components function as black boxes, and the free parameters are selected by hand or by an unspecified score. No new physical entity is proposed.

free parameters (6)
  • TDA grid-search Beta (persistence/homology scale) = 3.5 (WM811K), 10.0 (Mixed WM38), 3.5 (SPVD/SWED)
    Grid searched over 1.5, 3.5, 10.0, and 20.0; the final map is chosen by the unspecified 'lowest score.'
  • TDA grid-search distance metric = Euclidean (reported maps); Cosine also searched
    Categorical choice in the TDA grid search; no independent justification is given for the selected metric.
  • Number of clusters (networks) = 4 (WM811K), 31 (Mixed WM38), 20 (SPVD), 8 (SWED)
    Produced by the proprietary density-based clustering algorithm with unspecified thresholds, so cluster granularity is effectively a tool-selected output.
  • SSL training epochs = 600 (WM811K), 1000 (Mixed WM38), 100 (SPVD/SWED)
    Hand-set in hyperparameter tables; no convergence criterion or sensitivity analysis is reported.
  • SSL batch size = 512 (WM811K), 256 (others)
    Hand-set in hyperparameter tables; no ablation is reported.
  • SSL learning rate = 0.12
    Hand-set and constant across experiments; no schedule or sensitivity analysis is reported.
assumptions (5)
  • domain assumption Persistent homology vectors computed from wafer images capture defect-relevant shape and connectivity information
    Invoked in Methods 'Topological Computation'; no ablation shows that these features improve clustering or that the vectorization is stable.
  • domain assumption Stochastic augmentations such as flips, rotations, and crops preserve the defect label and produce useful positive pairs for contrastive learning
    Used in Methods Step 2; this is a standard SSL assumption for wafer maps but is not verified on these datasets.
  • ad hoc to paper The in-house TDA-enhanced density-based clustering algorithm produces meaningful clusters and its 'lowest score' is a valid model-selection criterion
    The algorithm and the score are not specified; every reported cluster map is chosen by this score.
  • domain assumption A pre-trained foundational model trained with SSL and Deep TDA transfers zero-shot to new wafer map datasets
    Invoked for the SPVD and SWED zero-shot experiments; no details of the pretraining data or model are provided.
  • domain assumption Synthetic datasets SPVD and SWED emulate real wafer map distributions closely enough to validate transfer learning
    The authors state that synthetic data 'may not fully represent' real-world complexity, so results on these datasets are limited as validation evidence.
invented entities (3)
  • DataRefiner Deep TDA feature extraction module
    purpose: Computes persistence-based topology vectors that are concatenated with CNN features
    No equations, public implementation, or output examples are provided, so the module cannot be independently tested.
  • DataRefiner TDA-enhanced density-based clustering algorithm
    purpose: Groups learned embeddings into clusters called networks
    Described only as 'developed in-house'; thresholds and the score function are unspecified.
  • Pre-trained foundational model with SSL and Deep TDA, plus a distilled MobileNetV3 variant
    purpose: Enables zero-shot feature extraction and efficient deployment
    No model weights, training data details, or evaluation checkpoints are released.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Advanced Clustering Framework for Semiconductor Image Analytics Integrating Deep TDA with Self-Supervised and Transfer Learning Techniques." pith.science (2026). https://pith.science/paper/DURDSPGB

@misc{pith2026250503848,
  author       = {Pith},
  title        = {Pith review of: Advanced Clustering Framework for Semiconductor Image Analytics Integrating Deep TDA with Self-Supervised and Transfer Learning Techniques},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DURDSPGB}},
  note         = {Machine review of arXiv:2505.03848}
}
read the original abstract

Semiconductor manufacturing generates vast amounts of image data, crucial for defect identification and yield optimization, yet often exceeds manual inspection capabilities. Traditional clustering techniques struggle with high-dimensional, unlabeled data, limiting their effectiveness in capturing nuanced patterns. This paper introduces an advanced clustering framework that integrates deep Topological Data Analysis (TDA) with self-supervised and transfer learning techniques, offering a novel approach to unsupervised image clustering. TDA captures intrinsic topological features, while self-supervised learning extracts meaningful representations from unlabeled data, reducing reliance on labeled datasets. Transfer learning enhances the framework's adaptability and scalability, allowing fine-tuning to new datasets without retraining from scratch. Validated on synthetic and open-source semiconductor image datasets, the framework successfully identifies clusters aligned with defect patterns and process variations. This study highlights the transformative potential of combining TDA, self-supervised learning, and transfer learning, providing a scalable solution for proactive process monitoring and quality control in semiconductor manufacturing and other domains with large-scale image datasets.

Figures

Figures reproduced from arXiv: 2505.03848 by the authors.

Figure 10
Figure 10. f [PITH_FULL_IMAGE:figures/full_fig_p018_10.png] view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

77 extracted references · 73 canonical work pages

  1. [1]

    WSTS Semiconductor Market Forecast Fall 2024 (2025)

    World Semiconductor Trade Statistics. WSTS Semiconductor Market Forecast Fall 2024 (2025). https://www.wsts.org/esraCMS/extension/media/f/WST/6765/WSTS_FC-Release- 2024_11.pdf

  2. [2]

    The Role of Semiconductors in Emerging Technologies like AI and 5G (2025) https://www.einfochips.com/blog/the-role-of-semiconductors-in-emerging- technologies-like-ai-and-5g/

    EInfoChips. The Role of Semiconductors in Emerging Technologies like AI and 5G (2025) https://www.einfochips.com/blog/the-role-of-semiconductors-in-emerging- technologies-like-ai-and-5g/

  3. [3]

    Hribhu Chowdhury Semiconductor manufacturing process improvement using data-driven methodologies (2023) https://doi.org/10.20944/preprints202310.0056.v1

  4. [4]

    Integration of AI and Machine Learning in Semiconductor Manufacturing for Defect Detection and Yield Improvement

    Katari, Monish et al. Integration of AI and Machine Learning in Semiconductor Manufacturing for Defect Detection and Yield Improvement. Journal of Artificial Intelligence General science (JAIGS) ISSN:3006-4023 3(1), 418–431. https://doi.org/10.60087/jaigs.v3i1.191 (2024)

  5. [5]

    and Balakrishnan R

    Munirathinam S. and Balakrishnan R. Predictive models for equipment fault detection in the semiconductor manufacturing process. International Journal of Engineering and Technology (2016);8(4):273-285. https://doi.org/10.7763/ijet.2016.v6.898

  6. [6]

    , Shin M

    Kim E. , Shin M. , Ahn H. , Park S. , Lee D. , Park H. et al.. Deep learning-based automatic defect classification for semiconductor manufacturing. Metrology, Inspection, and Process Control XXXVII (2023). https://doi.org/10.1117/12.2658638

  7. [7]

    & Lee, CO

    Yu, J., Han, S. & Lee, CO. Defect inspection in semiconductor images using FAST- MCD method and neural network. Int J Adv Manuf Technol 129, 1547–1565 (2023). https://doi.org/10.1007/s00170-023-12287-z

  8. [8]

    , Sánchez-Reolid R

    Rosa F . , Sánchez-Reolid R. , Gómez-Sirvent J. , Morales R. , & Fernández‐Caballero A. A review on machine and deep learning for semiconductor defect classification in scanning electron microscope images. Applied Sciences (2021);11(20):9508. https://doi.org/10.3390/app11209508

Show all 77 references
  1. [9]

    Iterative Cluster Harvesting for Wafer Map Defect Patterns (2024)

    Pleli A, Baeuerle S, Janus M, Barth J, Mikut R, Lensch H. Iterative Cluster Harvesting for Wafer Map Defect Patterns (2024). arXiv preprint arXiv:2404.15436. 2024 Apr 23

  2. [10]

    A novel DBSCAN-based defect pattern detection and classification framework for wafer bin map (2019)

    Jin CH, Na HJ, Piao M, Pok G, Ryu KH. A novel DBSCAN-based defect pattern detection and classification framework for wafer bin map (2019). IEEE Transactions on Semiconductor Manufacturing. (2019) May 14;32(3):286-92

  3. [11]

    Detection and clustering of mixed-type defect patterns in wafer bin maps

    Kim J, Lee Y , Kim H. Detection and clustering of mixed-type defect patterns in wafer bin maps. IISE Transactions. (2018) Feb 1;50(2):99-111

  4. [12]

    A self-adaptive DBSCAN-based method for wafer bin map defect pattern classification

    Chen S, Yi M, Zhang Y , Hou X, Shang Y , Yang P . A self-adaptive DBSCAN-based method for wafer bin map defect pattern classification. Microelectronics Reliability. (2021) Aug 1;123:114183

  5. [13]

    Clustering high-dimensional data: A survey on subspace clustering, pattern-based clustering, and correlation clustering

    Kriegel HP , Kröger P , Zimek A. Clustering high-dimensional data: A survey on subspace clustering, pattern-based clustering, and correlation clustering. Acm transactions on knowledge discovery from data (tkdd). (2009) Mar 23;3(1):1-58

  6. [14]

    Enabling DBSCAN for Very Large-Scale High-Dimensional Spaces

    Wang Y . Enabling DBSCAN for Very Large-Scale High-Dimensional Spaces. arXiv preprint arXiv:2411.11421. (2024) Nov 18

  7. [15]

    Anomaly detection and improvement of clusters using enhanced k- means algorithm

    Shorewala V . Anomaly detection and improvement of clusters using enhanced k- means algorithm. In2021 5th International Conference on Computer, Communication and Signal Processing (ICCCSP) (2021) May 24 (pp. 115-121). IEEE

  8. [16]

    An improved and heuristic-based iterative DBSCAN clustering algorithm

    Ma L. An improved and heuristic-based iterative DBSCAN clustering algorithm. In2021 IEEE 5th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC) (2021) Mar 12 (Vol. 5, pp. 2709-2714). IEEE

  9. [17]

    A novel approach for wafer defect pattern classification based on topological data analysis

    Ko S, Koo D. A novel approach for wafer defect pattern classification based on topological data analysis. Expert Systems with Applications. (2023) Nov 30;231:120765

  10. [18]

    A novel quality clustering methodology on fab-wide wafer map images in semiconductor manufacturing

    Hsu YM, Jia X, Li W, Lee J. A novel quality clustering methodology on fab-wide wafer map images in semiconductor manufacturing. International Manufacturing Science and Engineering Conference (2022) Jun 27 (Vol. 85819, p. V002T06A022). American Society of Mechanical Engineers

  11. [19]

    Explainable machine learning approach to yield and quality improvements using deep topological data analytics

    Giri J, Lengyel A. Explainable machine learning approach to yield and quality improvements using deep topological data analytics. International Electronic Packaging Technical Conference and Exhibition (2023) Oct 24 (Vol. 87516, p. V001T08A001). American Society of Mechanical Engineers

  12. [20]

    Self-supervised representation learning for wafer bin map defect pattern classification

    Kahng H, Kim SB. Self-supervised representation learning for wafer bin map defect pattern classification. IEEE Transactions on Semiconductor Manufacturing. (2020) Nov 16;34(1):74-86

  13. [21]

    When wafer failure pattern classification meets few- shot learning and self-supervised learning

    Geng H, Yang F , Zeng X, Yu B. When wafer failure pattern classification meets few- shot learning and self-supervised learning. IEEE/ACM International Conference On Computer Aided Design (ICCAD) (2021) Nov 1 (pp. 1-8). IEEE

  14. [22]

    A momentum contrastive learning framework for low-data wafer defect classification in semiconductor manufacturing

    Wang Y , Ni D, Huang Z. A momentum contrastive learning framework for low-data wafer defect classification in semiconductor manufacturing. Applied Sciences. (2023) May 10;13(10):5894

  15. [23]

    Variational deep clustering of wafer map patterns

    Hwang J, Kim H. Variational deep clustering of wafer map patterns. IEEE Transactions on Semiconductor Manufacturing. (2020) Jun 23;33(3):466-75

  16. [24]

    Dynamic clustering for wafer map patterns using self-supervised learning on convolutional autoencoders

    Kim D, Kang P . Dynamic clustering for wafer map patterns using self-supervised learning on convolutional autoencoders. IEEE Transactions on Semiconductor Manufacturing. (2021) Aug 25;34(4):444-54

  17. [25]

    Anomaly detection and segmentation for wafer defect patterns using deep convolutional encoder–decoder neural network architectures in semiconductor manufacturing

    Nakazawa T, Kulkarni DV . Anomaly detection and segmentation for wafer defect patterns using deep convolutional encoder–decoder neural network architectures in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing. (2019) Feb 5;32(2):250-6

  18. [26]

    A CNN-based transfer learning method for defect classification in semiconductor manufacturing

    Imoto K., Nakai T., Ike T., Haruki K., & Satō Y . A CNN-based transfer learning method for defect classification in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing (2019);32(4):455-459. https://doi.org/10.1109/tsm.2019.2941752

  19. [27]

    Anomaly detection in batch manufacturing processes using localized reconstruction errors from 1-d convolutional autoencoders

    Gorman M., Ding X., Maguire L., & Coyle D.. Anomaly detection in batch manufacturing processes using localized reconstruction errors from 1-d convolutional autoencoders. IEEE Transactions on Semiconductor Manufacturing (2023);36(1):147-150. https://doi.org/10.1109/tsm.2022.3216032

  20. [28]

    Convolutional autoencoders for anomaly detection in semiconductor manufacturing

    Gorman M., Ding X., Maguire L., & Coyle D.. Convolutional autoencoders for anomaly detection in semiconductor manufacturing. (2023). https://doi.org/10.1109/aics60730.2023.10470831

  21. [29]

    Physics-prior Bayesian neural networks in semiconductor processing

    Chen C., Parashar P ., Akbar C., Fu S., Syu M., & Lin A. Physics-prior Bayesian neural networks in semiconductor processing. IEEE Access (2019);7:130168-130179. https://doi.org/10.1109/access.2019.2940130

  22. [30]

    A patch-interactive enhancement network for semiconductor wafer map mixed defect recognition with a two-stage training strategy

    Shu-Long G., Lei Z., Zhao D., Wen G., Yang C., Feng K.et al.. A patch-interactive enhancement network for semiconductor wafer map mixed defect recognition with a two-stage training strategy. Measurement Science and Technology (2025);36(4):045403. https://doi.org/10.1088/1361-6...

  23. [31]

    Transfer Learning-Based Defect Detection System on Wafer Surfaces

    Chu SL, Su E, Ho CC. Transfer Learning-Based Defect Detection System on Wafer Surfaces. IEEE Transactions on Semiconductor Manufacturing. (2025) Jan 22

  24. [32]

    A CNN-based transfer learning method for defect classification in semiconductor manufacturing

    Imoto K, Nakai T, Ike T, Haruki K, Sato Y . A CNN-based transfer learning method for defect classification in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing. (2019) Sep 16;32(4):455-9

  25. [33]

    Few-shot classification of wafer bin maps using transfer learning and ensemble learning

    Kim H, Yoon H, Kim H. Few-shot classification of wafer bin maps using transfer learning and ensemble learning. Journal of Manufacturing Science and Engineering. (2024) Jul 1;146(7)

  26. [34]

    An EfficientNet-Based Transfer Learning System for Defect Classification in Manufacturing

    Rasheed MR, Coleman S, Gardiner B, Vance P , McAteer C, Nguyen K. An EfficientNet-Based Transfer Learning System for Defect Classification in Manufacturing. (2024) IEEE 22nd International Conference on Industrial Informatics (INDIN) 2024 Aug 18 (pp. 1-7). IEEE

  27. [35]

    Zhao, W., Gu, A., Liu, Y ., Yan, R., & Gao, Y . (2024). Dual-Channel Wafer Defect Segmentation and Classification Algorithm Based on Adaptive Data Augmentation. SSRN Electronic Journal. Available at SSRN: https://ssrn.com/abstract=5084918

  28. [36]

    AI Deep-Learning Approach for Manufacturing Optimization During Chiplets and Heterogeneous Package Inspection,

    S. Chitchian, S. Kim, T. Jung, T. Lee and B. Joo, "AI Deep-Learning Approach for Manufacturing Optimization During Chiplets and Heterogeneous Package Inspection, " 2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC), Berlin, Germany, 2024, pp. 1-4, doi: ...

  29. [37]

    Advanced Techniques in Semiconductor Defect Detection and Classification: Overview of Current Technologies and Future Trends in AI/ML Integration,

    Y . Zheng and K. . -W. A. Chee, "Advanced Techniques in Semiconductor Defect Detection and Classification: Overview of Current Technologies and Future Trends in AI/ML Integration, " 2024 World Rehabilitation Robot Convention (WRRC), Shanghai, China, 2024, pp. 1-5, doi: 10.1109...

  30. [38]

    Integration of AI and Machine Learning in Semiconductor Manufacturing for Defect Detection and Yield Improvement

    Katari M, Shanmugam L, Malaiyappan JN. Integration of AI and Machine Learning in Semiconductor Manufacturing for Defect Detection and Yield Improvement. Journal of Artificial Intelligence General science (JAIGS) ISSN: 3006-4023. (2024) Mar 30;3(1):418-31

  31. [39]

    A Machine Learning-Based Method for Assisted Analysis and Decision Making of Wafer Yield

    Qin J. A Machine Learning-Based Method for Assisted Analysis and Decision Making of Wafer Yield. 4th International Conference on Machine Learning and Intelligent Systems Engineering (MLISE) (2024) Jun 28 (pp. 183-186). IEEE

  32. [40]

    A momentum contrastive learning framework for low-data wafer defect classification in semiconductor manufacturing

    Wang Y , Ni D, Huang Z. A momentum contrastive learning framework for low-data wafer defect classification in semiconductor manufacturing. Applied Sciences. 2023 May 10;13(10):5894

  33. [41]

    Self-supervised representation learning for wafer bin map defect pattern classification

    Kahng H, Kim SB. Self-supervised representation learning for wafer bin map defect pattern classification. IEEE Transactions on Semiconductor Manufacturing. 2020 Nov 16;34(1):74-86

  34. [42]

    Application of Self-Supervised Contrastive Learning for Mixed- Type Wafer Map Defect Recognition and Classification

    Kim T, Behdinan K. Application of Self-Supervised Contrastive Learning for Mixed- Type Wafer Map Defect Recognition and Classification. Available at SSRN 4605931

  35. [43]

    Unsupervised representation learning for large-scale wafer maps in micro-electronic manufacturing

    Xu Q, Yu N, Yu H. Unsupervised representation learning for large-scale wafer maps in micro-electronic manufacturing. IEEE Transactions on Consumer Electronics. 2023 Mar 27

  36. [44]

    Dynamic clustering for wafer map patterns using self-supervised learning on convolutional autoencoders

    Kim D, Kang P . Dynamic clustering for wafer map patterns using self-supervised learning on convolutional autoencoders. IEEE Transactions on Semiconductor Manufacturing. 2021 Aug 25;34(4):444-54

  37. [45]

    Wafer Map Defect Classification Using Autoencoder- Based Data Augmentation and Convolutional Neural Network

    Bao YY , Li EC, Yang HQ, Jia BB. Wafer Map Defect Classification Using Autoencoder- Based Data Augmentation and Convolutional Neural Network. arXiv preprint arXiv:2411.11029. 2024 Nov 17

  38. [46]

    A systematic review of deep learning for silicon wafer defect recognition

    Batool U, Shapiai MI, Tahir M, Ismail ZH, Zakaria NJ, Elfakharany A. A systematic review of deep learning for silicon wafer defect recognition. IEEE Access. 2021 Aug 18;9:116572-93

  39. [47]

    AI in semiconductor industry

    De Luca C, Lippmann B, Schober W, Al-Baddai S, Pelz G, Rojko A, Pétrot F , Coppola M, John R. AI in semiconductor industry. InArtificial Intelligence for Digitising Industry–Applications 2022 Sep 1 (pp. 105-112). River Publishers

  40. [48]

    Wafer bin map recognition with autoencoder-based data augmentation in semiconductor assembly process

    Shen PC, Lee CY . Wafer bin map recognition with autoencoder-based data augmentation in semiconductor assembly process. IEEE Transactions on Semiconductor Manufacturing. 2022 Jan 25;35(2):198-209

  41. [49]

    Multiple granularities generative adversarial network for recognition of wafer map defects

    Yu J, Liu J. Multiple granularities generative adversarial network for recognition of wafer map defects. IEEE Transactions on Industrial Informatics. 2021 Jun 25;18(3):1674-83

  42. [50]

    An analog wafer map clustering model with deep-learning based data augmentation and feature extraction

    Liu Z, Shi Z. An analog wafer map clustering model with deep-learning based data augmentation and feature extraction. In2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) 2022 Oct 25 (pp. 1-3). IEEE

  43. [52]

    Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks

    Schlosser T, Friedrich M, Beuth F , Kowerko D. Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks. Journal of Intelligent Manufacturing. 2022 Apr;33(4):1099- 123

  44. [53]

    Hybrid Deep Learning Pipeline for Advanced Electrical Wafer Defect Maps Assessment

    Rundo F , Coffa S, Calabretta M, Sarpietro RE, Messina A, Pino C, Palazzo S, Spampinato C. Hybrid Deep Learning Pipeline for Advanced Electrical Wafer Defect Maps Assessment. In2022 AEIT International Annual Conference (AEIT) 2022 Oct 3 (pp. 1-6). IEEE

  45. [54]

    Explainable deep learning system for advanced silicon and silicon carbide electrical wafer defect map assessment

    Sarpietro RE, Pino C, Coffa S, Messina A, Palazzo S, Battiato S, Spampinato C, Rundo F . Explainable deep learning system for advanced silicon and silicon carbide electrical wafer defect map assessment. IEEE Access. 2022 Sep 5;10:99102-28

  46. [55]

    Automated Anomaly Detection Through Assembly and Packaging Process

    Al-Baddai S, Juhrisch M, Papadoudis J, Renner A, Bernhard L, De Luca C, Haas F , Schober W. Automated Anomaly Detection Through Assembly and Packaging Process. InArtificial Intelligence for Digitising Industry–Applications 2022 Sep 1 (pp. 161-176). River Publishers

  47. [56]

    Defective wafer detection using a denoising autoencoder for semiconductor manufacturing processes

    Fan SK, Hsu CY , Jen CH, Chen KL, Juan LT. Defective wafer detection using a denoising autoencoder for semiconductor manufacturing processes. Advanced Engineering Informatics. 2020 Oct 1;46:101166

  48. [57]

    A self-training-based system for die defect classification

    Ping-Hung W, Lin SZ, Yuan-Teng C, Yu-Wei L, Ssu-Han C. A self-training-based system for die defect classification. Mathematics. 2024;12(15):2415

  49. [58]

    AI-Based Localization and Classification of Visual Anomalies on Semiconductor Devices

    Le MK, Chia JZ, Peskes D. AI-Based Localization and Classification of Visual Anomalies on Semiconductor Devices. In AmEC 2024–Automotive meets Electronics & Control; 14. GMM Symposium 2024 Mar 14 (pp. 36-40). VDE

  50. [59]

    Deep convolutional generative adversarial networks-based data augmentation method for classifying class-imbalanced defect patterns in wafer bin map

    Park S, You C. Deep convolutional generative adversarial networks-based data augmentation method for classifying class-imbalanced defect patterns in wafer bin map. Applied Sciences. 2023 Apr 28;13(9):5507

  51. [60]

    Building manufacturing deep learning models with minimal and imbalanced training data using domain adaptation and data augmentation

    Li AS, Bertino E, Wu RT, Wu TY . Building manufacturing deep learning models with minimal and imbalanced training data using domain adaptation and data augmentation. In2023 IEEE International Conference on Industrial Technology (ICIT) 2023 Apr 4 (pp. 1-8). IEEE

  52. [61]

    Wafer defect pattern labeling and recognition using semi-supervised learning

    Li KS, Jiang XH, Chen LL, Wang SJ, Huang AY , Chen JE, Liang HC, Hsu CL. Wafer defect pattern labeling and recognition using semi-supervised learning. IEEE Transactions on Semiconductor Manufacturing. 2022 Mar 14;35(2):291-9

  53. [62]

    A Masked Autoencoder-Based Approach for Defect Classification in Semiconductor Manufacturing

    Lu H, Shen J, Zhao B, Lou P , Zhou W, Zhou K, Zhao X, Lyu S, Lu Y . A Masked Autoencoder-Based Approach for Defect Classification in Semiconductor Manufacturing. In2023 International Workshop on Advanced Patterning Solutions (IWAPS) 2023 Oct 26 (pp. 1-4). IEEE

  54. [63]

    Enhancing defect diagnosis and localization in wafer map testing through weakly supervised learning

    Nie M, Jiang W, Yang W, Wang S, Wen X, Ni T. Enhancing defect diagnosis and localization in wafer map testing through weakly supervised learning. In2023 IEEE 32nd Asian Test Symposium (ATS) 2023 Oct 14 (pp. 1-6). IEEE

  55. [64]

    Anomalous Wafer Map Detection and Localization using Unsupervised Learning

    Zhao L, Yeo CK. Anomalous Wafer Map Detection and Localization using Unsupervised Learning. In2023 International Conference on IC Design and Technology (ICICDT) 2023 Sep 25 (pp. 80-83). IEEE

  56. [65]

    Unsupervised Defect Detection Based on Fast Retrieval of Deep Feature

    Wu L, Qiu F , Zhang B, Guo J. Unsupervised Defect Detection Based on Fast Retrieval of Deep Feature. In2023 4th International Conference on Computer, Big Data and Artificial Intelligence (ICCBD+ AI) 2023 Dec 15 (pp. 733-737). IEEE

  57. [66]

    Unsupervised Wafer Defect Classification Model Based On Joint Reconstruction And Clustering

    Jie L, Guo Y , Yao Y , Liu Y . Unsupervised Wafer Defect Classification Model Based On Joint Reconstruction And Clustering. Advances in Engineering Technology Research. 2024;9(1):182-

  58. [67]

    Adaptive modelling for anomaly detection and defect diagnosis in semiconductor smart manufacturing: A domain-specific automl

    Zhai W, Shi X, Zeng Z. Adaptive modelling for anomaly detection and defect diagnosis in semiconductor smart manufacturing: A domain-specific automl. In2023 IEEE International Conference on Cybernetics and Intelligent Systems (CIS) and IEEE Conference on Robotics, Automation an...

  59. [68]

    Wafer map defect patterns semi-supervised classification using latent vector representation

    Wei Q, Zhao W, Zheng X, Zeng Z. Wafer map defect patterns semi-supervised classification using latent vector representation. In 2023 IEEE International Conference on Cybernetics and Intelligent Systems (CIS) and IEEE Conference on Robotics, Automation and Mechatronics (RAM) 20...

  60. [69]

    Joint feature and label adversarial network for wafer map defect recognition

    Yu J, Shen Z, Zheng X. Joint feature and label adversarial network for wafer map defect recognition. IEEE Transactions on Automation Science and Engineering. 2020 Jun 30;18(3):1341-53

  61. [70]

    Unsupervised pre-training of imbalanced data for identification of wafer map defect patterns

    Shon HS, Batbaatar E, Cho WS, Choi SG. Unsupervised pre-training of imbalanced data for identification of wafer map defect patterns. IEEE Access. 2021 Mar 24;9:52352-63

  62. [71]

    Identification of key features using topological data analysis for accurate prediction of manufacturing system outputs

    Guo W, Banerjee AG. Identification of key features using topological data analysis for accurate prediction of manufacturing system outputs. Journal of Manufacturing Systems. 2017 Apr 1;43:225-34

  63. [72]

    Topological Data Analysis in smart manufacturing: State of the art and future directions

    Uray M, Giunti B, Kerber M, Huber S. Topological Data Analysis in smart manufacturing: State of the art and future directions. Journal of Manufacturing Systems. 2024 Oct 1;76:75-91

  64. [73]

    Recent Applications Using Explainable Artificial Intelligence for Data Analytics

    Mansour Y , Jan M, Brik B, Ahmed N. Recent Applications Using Explainable Artificial Intelligence for Data Analytics. In2024 IEEE International Conference on Control & Automation, Electronics, Robotics, Internet of Things, and Artificial Intelligence (CERIA) 2024 Oct 17 (pp. 1...

  65. [74]

    The Applications of Simulation and Artificial Intelligence in Advanced Packaging

    Li Y , Kim W. The Applications of Simulation and Artificial Intelligence in Advanced Packaging. In2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2024 Jul 15 (pp. 1-5). IEEE

  66. [75]

    Wafer map failure pattern recognition and similarity ranking for large-scale data sets

    Wu MJ, Jang JS, Chen JL. Wafer map failure pattern recognition and similarity ranking for large-scale data sets. IEEE Transactions on Semiconductor Manufacturing. 2014 Oct 21;28(1):1-12

  67. [76]

    Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition

    Wang J, Xu C, Yang Z, Zhang J, Li X. Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition. IEEE Transactions on Semiconductor Manufacturing. 2020 Sep 2;33(4):587-96

  68. [77]

    https://github.com/Junliangwangdhu/WaferMap

  69. [78]

    Topological methods for data modelling

    Carlsson G. Topological methods for data modelling. Nature Reviews Physics. 2020 Dec;2(12):697-708

Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.