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REVIEW 4 major objections 5 minor 8 cited by

Louvre: Relaxing Hardware Requirements of Quantum LDPC Codes by Routing with Expanded Quantum Instruction Set

T0 review · 4 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read Louvre routing lowers quantum LDPC qubit degree to 4.5 or 4

desk verdict Louvre cuts GB/BB code connectivity to degree 4.5–4 via iSWAP routing; the analytic claims hold up, and the LER-parity claim is plausible but under-verified by underspecified simulations. read the letter →

arxiv 2508.20858 v1 pith:3TCZENSQ submitted 2025-08-28 quant-ph

Runshi Zhou , Fang Zhang , Hui-Hai Zhao , Feng Wu , Linghang Kong , Jianxin Chen This is my paper
classification quant-ph MSC 81P70 PACS 03.67.Pp03.67.Lx
keywords quantumLDPCcodesgeneralizedbicyclebivariatesyndromeextractionqubitroutingiSWAPgateconnectivityreductionlogicalerrorrate
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper proposes Louvre, a family of syndrome extraction circuits for generalized bicycle (GB) quantum LDPC codes that cuts the physical connectivity needed on superconducting hardware. The key trick is that a CXSWAP gate—CNOT followed by a SWAP—costs the same as a CNOT when iSWAP is a native gate, so ancilla qubits can be routed for free while stabilizer measurements happen. Louvre-7 keeps the standard circuit depth and lowers the average qubit degree of bivariate bicycle codes from 6 to 4.5; Louvre-8 accepts one extra layer to reach average degree 4. Both schemes also remove some long-range couplers, and numerical simulations over six rounds show Louvre-7's logical error rate matches the standard circuit while Louvre-8 pays a modest penalty. The paper further shows that reordering gates shortens couplers and that the scheme adapts to open boundaries and defect-containing grids.

What carries the argument

The mechanism is the CXSWAP/iSWAP gate used as a free routing primitive, together with the symmetry of GB stabilizer shapes. A CXSWAP is a CNOT followed by a SWAP; on hardware with native iSWAP it costs one two-qubit gate, so moving qubits during syndrome extraction adds no extra depth or two-qubit noise. Because the vector from a Z-ancilla to its A_i data qubit is the negative of the vector from an X-ancilla to its A_i data qubit, the same coupler can serve both sides of the interaction once the ancilla and data sublattices have been moved past each other. Louvre-7 uses one CXSWAP routing layer in Phase 2 and a reversed round to restore the layout; Louvre-8 inserts an extra SWAP layer, halv

What would settle it

Measure the logical error rate of the [[18,4,4]] BB code under the SI(1000) model with a native iSWAP whose fidelity equals that of CNOT, and again with iSWAP degraded by the 1.5x error factor the paper quotes: if the two Louvre-7 curves separate from the standard syndrome-extraction curve beyond simulation statistics, the free-routing premise fails. Alternatively, draw the explicit wiring diagram of a Louvre-7 cell and count distinct couplers per ancilla: if any ancilla needs a sixth distinct coupler, the degree formula n_a+n_b−(1/2)max(n_a,n_b) is wrong.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central claim is that a GB code's syndrome extraction need not assign one dedicated coupler per stabilizer term. Because the vector from a Z-ancilla to its A_i data qubit is the negative of the vector from an X-ancilla to its A_i data qubit, a single bidirectional coupler can serve both halves of the interaction if the ancilla and data sublattices are moved between the two uses. Replacing some CNOTs with CXSWAPs moves the sublattices in opposite directions, reusing couplers, and a reversed round returns qubits to their starting layout. For a code with n_a and n_b terms in its two generating polynomials, Louvre-7 achieves average degree n_a+n_b−(1/2)max(n_a,n_b),

Load-bearing premise

The construction assumes iSWAP (equivalently CXSWAP) is a native two-qubit gate with the same cost and fidelity as CNOT, so routing ancilla qubits through data qubits is free; if that parity does not hold on real hardware, Louvre-7 loses its same-depth, same-logical-error-rate property.

Editorial extensions

If this is right

  • If the construction is correct, bivariate bicycle codes become implementable on hardware with average qubit degree 4 to 4.5, much closer to planar-code connectivity while retaining high code rates.
  • Louvre-7 achieves the degree reduction without adding circuit depth, so the improvement does not come from trading away noise or speed.
  • Louvre-8's inserted SWAP layer adds a roughly threefold logical error rate penalty in the paper's simulations, making it the scheme of choice when connectivity, not noise, is the binding constraint.
  • For La-Cross codes, Louvre-7R circuits can run on grid topology with nearest-neighbor interactions, which current surface-code hardware already supports.
  • Placement and routing estimates in the paper show that Louvre circuits generally reduce the number of hardware tiers needed for multi-layer superconducting implementations of BB and GB codes.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If iSWAP is natively available at parity with CNOT, the same free-routing trick should transfer to other stabilizer-code families whose stabilizer shapes come in opposite vector pairs; Louvre is a template rather than a GB-specific patch.
  • The claimed noise equivalence of Louvre-7 depends on iSWAP and CNOT having equal fidelity; for architectures where iSWAP error is even modestly higher, the logical-error-rate curves will separate, and the crossover error ratio is directly measurable.
  • The degree formulas are averages; a concrete next step is to compile Louvre-7 and Louvre-8 for specific chip coupler maps and check whether the removed long-range couplers actually sit on the bottleneck layers, since average degree alone may not equal fabrication difficulty.
  • Because the routing relies on periodic, all-sublattice motion, codes whose stabilizer shapes are not closed under vector negation would not benefit; identifying such families would map the boundary of the method.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes Louvre, a syndrome-extraction routing framework for generalized bicycle (GB) codes that reduces the physical qubit connectivity degree by exploiting an expanded native gate set containing iSWAP/CXSWAP and SWAP. Louvre-7 is claimed to reduce the average degree of bivariate bicycle codes from 6 to 4.5 while preserving the depth-7 circuit, and Louvre-8 further reduces it to 4 at the cost of one extra layer. The authors also introduce distance-reducing variants Louvre-7R/8R, report logical-error-rate simulations claiming Louvre-7 is indistinguishable from the static circuit while Louvre-8 has a modest penalty, and present placement/routing experiments suggesting reduced hardware cost in multi-layer superconducting architectures. The paper includes a note crediting the earlier routing idea in a related work by the same authors and an independent concurrent work.

Significance. If the central claims hold, the paper provides a practical and elegant route to lowering connectivity requirements for high-rate quantum LDPC codes, which is a recognized bottleneck for superconducting implementations. The analytical degree-reduction formulas (Eqs. 1-2) are simple and transparent, and the circuit constructions are illustrated with concrete examples. The paper also includes genuine numerical predictions under a fixed noise model, placement/routing analyses, and an explicit extension to open boundaries, and it properly credits prior and concurrent related work. The main risks are reproducibility of the logical-error-rate simulations, lack of a general correctness proof for the Louvre circuits, and the strong dependence of the 'free routing' claim on the assumed equivalence of iSWAP and CNOT error rates.

major comments (4)
  1. [Section 5.1 (Figs. 11-15)] The central claim that Louvre-7 has an 'indistinguishable' logical error rate from the standard SEC rests entirely on numerical simulations that are not reproducible from the manuscript. The paper cites the SI(1000) model to [26] but does not specify the circuit-level noise model (depolarizing vs. amplitude/dephasing channels), gate error values, idling error, measurement/reset error, decoding algorithm or matching graph, number of shots, or error bars. Without these details, the asserted LER equivalence cannot be checked, and it is load-bearing for the main advantage of Louvre-7. Please provide a complete simulation specification (ideally code or data) or at least all parameters needed for independent reproduction.
  2. [Section 3 (Eqs. 1-2) and Appendix A] The degree reduction formulas (1)-(2) are stated as general results for GB codes, but the circuit construction is only demonstrated through examples (J18,4,4K and La-Cross code). No theorem or general algorithm is given proving that the Louvre-7/Louvre-8 circuits measure all stabilizers for arbitrary GB codes with arbitrary A and B, nor that the formulas hold exactly. The relative-position arguments are persuasive but do not constitute a proof. Given that the central claim is a general degree reduction, a formal proof or a systematic automated verification over the code families considered would be needed.
  3. [Section 2.3 and Fig. 12] The 'free routing' premise for Louvre-7 is that a CXSWAP (iSWAP) gate has the same cost and fidelity as a CNOT. The sensitivity of this assumption is not analyzed: Fig. 12 varies only the SWAP noise factor for Louvre-8, not the relative iSWAP/CNOT error for Louvre-7. Since even a small extra error on the routing gates would break the claimed LER parity, the paper should include a simulation or analytic bound showing how the Louvre-7 LER changes as the iSWAP/CNOT error ratio varies from 1 to, say, 2. Without this, the headline 'indistinguishable' claim is conditional on an unquantified hardware assumption.
  4. [Table 6, J72,8,9K row] The average degree reported for Louvre-8 on J72,8,9K is 4.5, but Eq. (2) with n_a=2 and n_b=6 gives 5. If this is not a typo, the formula needs qualification for imbalanced polynomials; if it is a typo, it should be corrected. As written, the table undermines confidence in the numerical degree reductions and should be reconciled with the formulas in Section 3.
minor comments (5)
  1. [Table 6] The table layout is easy to misread: each scheme is represented by a pair (degree, total interaction distance), which should be stated explicitly in the header or caption to avoid confusion such as reading '6 10' as two separate values under different schemes.
  2. [Fig. 15(d)] The caption reads 'J126, 16, 8K' but the text and Table 10 refer to 'J128, 16, 8K'. Please correct the code label.
  3. [Appendix A] There is a typo: 'Lourvre' should be 'Louvre'. Also in the same appendix, 'senario' appears twice.
  4. [Fig. 12] The label 'gate nosie factor' should read 'gate noise factor'.
  5. [Section 5.1] The logical-error-rate plots would benefit from error bars or at least a statement of the number of Monte Carlo samples used, since the 'indistinguishable' claim is visual.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: degree reductions are coupler-counting from explicit circuits, and LER parity is a genuine simulation result under an external noise model; self-citations are transparent and non-load-bearing.

full rationale

The central derivations are self-contained. Eq. (1) and Eq. (2) are obtained by counting how many distinct couplers are needed after the explicit routing sequences in Tables 2 and 4; for BB codes na=nb=3 they give 4.5 and 4 by direct arithmetic, with no fitted parameter. The headline LER comparisons are genuine simulation outputs under the SI(1000) model of [26] over 6 rounds; no parameter is adjusted to force Louvre-7 to match Regular. The only externally imported premise is the native gate set and relative SWAP error, stated explicitly in Sec. 2.3 as an assumption and supported by independent experimental work [18,19]; the CXSWAP-as-iSWAP relation is a standard quantum-circuit identity, not an assumption tailored to the conclusion. The self-citation [20] merely credits the prior Halma routing idea and is not used to justify any theorem here, and the AshN citation [18] is to a published, experimentally tested scheme; neither raises the circularity score. The paper itself flags human-ansatz suboptimality (Sec. 4 and 5.2) and the local failure of Louvre when padding qubits are absent (Appendix A); these are honest limitations, not circular reductions. Concerns about the under-specified numerical setup (no circuit-level noise model or decoding details) and the 6-round/world-LER scope are reproducibility and scope risks, not circularity; similarly, the Table 6 entry '10' under J18,4,4K is the averaged interaction-distance column, not a degree, so it is not an internal contradiction. Hence no step in the derivation is equivalent to its inputs by construction.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central construction introduces no new physical entities and no fitted parameters. It relies on two external assumptions: the availability and fidelity of the expanded native gate set (iSWAP, CNOT, SWAP) and the global, periodic topology assumptions of the standard GB code setting. The numerical LER claims additionally rely on an unspecified noise model inherited from [26].

assumptions (4)
  • domain assumption The hardware provides native iSWAP (equivalently CXSWAP), CNOT, and SWAP gates with the stated relative fidelities.
    Section 2.3: the entire Louvre construction treats CXSWAP as cost-free routing and borrows the AshN gate scheme from [18,19].
  • domain assumption Syndrome extraction is executed as global instructions where all ancillas of the same type act in parallel, and all qubit sublattices move together.
    Section 2.2 and used throughout Section 3; breaks if absent sites exist, which the appendix addresses with padding or extra couplers.
  • domain assumption The main construction assumes periodic boundary conditions (torus topology) and a complete grid; degree formulas (1)-(2) rely on this.
    Section 3: the sublattice-motion argument that reuses couplers depends on translational symmetry; open-boundary adaptations are deferred to Appendix A.
  • domain assumption The SI(1000) noise model cited from [26] is a faithful proxy for superconducting hardware behavior.
    Section 5.1: the logical error rate conclusions rest on this model, but its gate-level parameters are not defined in the paper and are only referenced.

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Cite this review

Pith. "Pith review of Louvre: Relaxing Hardware Requirements of Quantum LDPC Codes by Routing with Expanded Quantum Instruction Set." pith.science (2026). https://pith.science/paper/3TCZENSQ

@misc{pith2026250820858,
  author       = {Pith},
  title        = {Pith review of: Louvre: Relaxing Hardware Requirements of Quantum LDPC Codes by Routing with Expanded Quantum Instruction Set},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3TCZENSQ}},
  note         = {Machine review of arXiv:2508.20858}
}
read the original abstract

Generalized bicycle codes (GB codes) represent a promising family of quantum low-density parity-check codes, characterized by high code rates and relatively local qubit connectivity. A subclass of the GB code called bivariate bicycle codes (BB codes) has garnered significant interest due to their compatibility with two-layer connectivity architectures on superconducting quantum processors. However, one key limitation of BB codes is their high qubit connectivity degree requirements (degree 6), which exacerbates the noise susceptibility of the system. Building on the recent progress in implementing multiple two-qubit gates on a single chip, this work introduces Louvre -- a routing-based framework designed to reduce qubit connectivity requirements in GB codes. Specifically, Louvre-7 achieves degree reduction while preserving the depth of the syndrome extraction circuit, whereas Louvre-8 further minimizes the connectivity by slightly increasing the circuit depth. When applied to BB codes, these two schemes could reduce the average degree to 4.5 and 4, respectively. Crucially, Louvre eliminates some of the long-range, error-prone connections, which is a distinct advantage over prior approaches. Numerical simulations demonstrate that Louvre-7 has an indistinguishable logical error rate as the standard syndrome extraction circuits of GB codes, while Louvre-8 only incurs a slight error rate penalty. Furthermore, by reordering some of the gates in the circuit, we can reduce the coupler length without degrading the performance. Though most of our analysis focuses on GB codes defined on periodic boundary conditions, we further discuss the adaptability of Louvre to open-boundary lattices and defect-containing grids, underscoring its broader applicability in practical quantum error correction architectures.

Figures

Figures reproduced from arXiv: 2508.20858 by the authors.

Figure 1
Figure 1. The bulk region of a generalized bicycle code with a basic unit in the boxed area. [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. (a) The shape of a Z-stabilizer for the toric code in the language of generalized bicycle code. [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. vBi,Z (red arrow) and vBi,X (blue arrow). L X R Z (a) L X R Z (b) L R X Z (c) X × R R • × • X Z × L L × Z (d) [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figures from the paper (15 more)
Figure 4
Figure 4. Figure 4: (a-c) The 2D diagram and (d) the quantum circuit of an example reusing the same coupler [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: The qubit configuration in a basic unit before and after routing. [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 6
Figure 6. Figure 6: The Louvre-7 syndrome extraction circuit of the [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: The Louvre-8 syndrome extraction circuit of the [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]
Figure 8
Figure 8. Figure 8: An example of reducing interaction distances via [PITH_FULL_IMAGE:figures/full_fig_p013_8.png]
Figure 9
Figure 9. Figure 9: The shape of the stabilizers in the κ = 2 La-Cross code, indicated by the filled data qubit in the shaded region. We apply the technique discussed in Section 4.1 to data qubits corresponding to terms in A of Z-ancilla, by arranging the two-qubit interactions in a certa…
Figure 10
Figure 10. Figure 10: (a-h) The Louvre-7R syndrome extraction circuit for the La-Cross code with interaction [PITH_FULL_IMAGE:figures/full_fig_p016_10.png]
Figure 11
Figure 11. Figure 11: The logical error rate with different syndrome extraction circuit. The logical error rate is [PITH_FULL_IMAGE:figures/full_fig_p019_11.png]
Figure 12
Figure 12. Figure 12: The logical error rate of the J72, 12, 6K BB code with different gate nosie factor of the SWAP gate. result is shown in [PITH_FULL_IMAGE:figures/full_fig_p019_12.png]
Figure 13
Figure 13. Figure 13: The logical error rate of the κ = 2 La-Cross code on the periodic boundaries with different syndrome extraction circuit. 10 3 10 2 Phyical Error Rate 10 2 10 1 10 0 Logical Error Rate LER over 6 rounds for the =2 Open Boundary La-Cross Code Regular l=6 On grid l=6 Reg…
Figure 14
Figure 14. Figure 14: The logical error rate of the (a) κ = 2 and (b) κ = 3 La-Cross code on open boundaries with different syndrome extraction circuit. 5.2 Coupler Length Although a multi-layer structure employing bump-bonding, TSVs and long-range couplers can enable the connectivity requ…
Figure 15
Figure 15. Figure 15: The logical error rate of the generalized bicycle code with different syndrome extraction [PITH_FULL_IMAGE:figures/full_fig_p022_15.png]
Figure 16
Figure 16. Figure 16: The scenario when we use padding qubits. The left data qubit in the boxed basic unit is [PITH_FULL_IMAGE:figures/full_fig_p025_16.png]
Figure 17
Figure 17. Figure 17: The scenario when we install additional couplers. The left data qubit in the boxed basic unit [PITH_FULL_IMAGE:figures/full_fig_p026_17.png]
Figure 18
Figure 18. Figure 18: The logical error rate of the J88, 6, 6K BB on open boundary conditions with different syndrome extraction circuit. S1 is the first senario while S2 is the second senario discuss in this section. [6] Matt McEwen, Dave Bacon, and Craig Gidney. “Relaxing Hardware Requir…

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Forward citations

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Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.