pith. sign in

arxiv: 2604.03290 · v1 · submitted 2026-03-26 · 💻 cs.AR

A Review of Multiscale Thermal Modeling in Heterogeneous 3D ICs

Baibhari Priya Barua , Md Rahatul Islam Udoy , Ahmedullah Aziz This is my paper

Pith reviewed 2026-05-15 00:09 UTC · model grok-4.3

classification 💻 cs.AR
keywords 3D integrated circuitsthermal modelingmultiscale analysisthermal boundary resistancefinite element methodcompact modelsphysics-informed machine learningheterogeneous packages
0
0 comments X

The pith

A review unifies device-to-system thermal models for 3D ICs by analyzing trade-offs in methods and stressing interface resistance.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Thermal management in stacked 3D integrated circuits has become critical as power densities increase and heat paths narrow. This review pulls together physical mechanisms and modeling techniques from the smallest device features up to full system packages. It compares compact models, numerical simulations, analytical methods, and machine learning approaches, while underscoring how thermal boundary resistance at interfaces dominates heat flow. The goal is to provide design guidelines and a research path that combines physics and data-driven tools for better predictions and co-optimization.

Core claim

The paper synthesizes multiscale thermal transport in heterogeneous 3D ICs into a unified framework that evaluates compact thermal models, finite element and finite difference methods, Green's function techniques, reduced-order and multi-fidelity methods, and physics-informed machine learning, placing central importance on thermal boundary resistance, material anisotropy, electrothermal coupling, and the requirement for experimental validation.

What carries the argument

The coherent framework that unifies thermal modeling across device, package, and system scales while incorporating the effects of thermal boundary resistance and variability in thermal interface materials.

If this is right

  • Designers can choose modeling techniques based on accuracy-speed trade-offs for specific 3D IC configurations.
  • Including thermal boundary resistance in models improves accuracy of temperature predictions in stacked dies.
  • Decoupled electrical and thermal analyses lead to errors that the framework helps avoid.
  • Hybrid approaches combining physics-based models with machine learning enable faster thermally aware design optimization.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The framework may support integration with real-time sensing for adaptive thermal management in operating chips.
  • Extending this to emerging materials like 2D layers could address anisotropy more explicitly.
  • Validation protocols suggested here could standardize testing for new 3D packaging technologies.

Load-bearing premise

The review presumes that its selection of literature covers all major methods and challenges comprehensively without significant bias.

What would settle it

Demonstrating that a key thermal modeling method or a measured thermal behavior in a 3D IC is not adequately captured by the proposed unified framework would challenge its coherence.

read the original abstract

Thermal behavior has become a first-order constraint in advanced 2.5D/3D integrated circuits (ICs) and heterogeneous packages. As power densities rise and multiple active dies are vertically integrated, heat removal paths become constricted, elevating junction temperatures, magnifying temperature gradients, and exacerbating reliability risks. This review synthesizes the physical mechanisms, modeling assumptions, and analysis methods that govern multiscale thermal transport in 3D ICs, with emphasis on interface-dominated conduction, material anisotropy, and strong electrothermal coupling. We unify device-to-system scales into a coherent framework, analyzing trade-offs among compact thermal models (CTMs), finite element/finite difference methods (FEM/FDM), Green's function and semi-analytical techniques, reduced-order and multi-fidelity methods, and physics-informed machine learning (PIML), while highlighting the central role of thermal boundary resistance (TBR) and variability in thermal interface materials (TIMs), the pitfalls of decoupled electrical/thermal analyses, and the need for rigorous validation against measurements. Finally, we outline practical design guidelines and a forward-looking research agenda that integrates physics-based modeling, data-driven surrogates, and in situ sensing to enable thermally aware co-optimization across the IC-package-system hierarchy.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 2 minor

Summary. The manuscript is a review synthesizing physical mechanisms, modeling assumptions, and analysis methods for multiscale thermal transport in heterogeneous 3D ICs. It unifies device-to-system scales into a coherent framework by analyzing trade-offs among compact thermal models (CTMs), finite element/finite difference methods (FEM/FDM), Green's function and semi-analytical techniques, reduced-order and multi-fidelity methods, and physics-informed machine learning (PIML), while emphasizing the central role of thermal boundary resistance (TBR), variability in thermal interface materials (TIMs), pitfalls of decoupled electrothermal analyses, and the need for rigorous validation against measurements. It concludes with practical design guidelines and a forward-looking research agenda.

Significance. If the synthesis accurately captures the literature without significant gaps, the review would be significant for the field of computer architecture and electronics thermal management. It offers a structured comparison of modeling approaches at a time when thermal constraints are first-order in 3D IC design, provides actionable guidelines for practitioners, and highlights timely directions such as integrating physics-based models with data-driven surrogates and in situ sensing.

minor comments (2)
  1. [Abstract] Abstract: The acronym PIML is introduced without prior expansion on first use (though expanded later in the text); ensure all acronyms such as TIMs and TBR are defined at their first appearance for clarity.
  2. The manuscript would benefit from an explicit summary table or diagram in the main text that maps the unified framework across scales and methods, as the trade-off analysis is described but not visually consolidated.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the positive evaluation of our review on multiscale thermal modeling in heterogeneous 3D ICs and for recommending minor revision. The assessment accurately captures the manuscript's scope, its unification of modeling approaches across scales, and the emphasis on thermal boundary resistance, validation, and future directions. We appreciate the recognition of its potential utility for the field.

Circularity Check

0 steps flagged

No significant circularity: pure literature synthesis

full rationale

This is a review paper that synthesizes external literature on multiscale thermal modeling in 3D ICs. It analyzes trade-offs among CTMs, FEM/FDM, Green's functions, reduced-order methods, and PIML, highlights TBR/TIM issues, and offers design guidelines without presenting original derivations, equations, fitted parameters, or predictions. No self-definitional steps, no fitted inputs renamed as predictions, and no load-bearing self-citations that reduce the central claims to the paper's own inputs. The unification is an organizational framework drawn from cited works, not a closed loop. All content is externally grounded.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

As a review paper, the central claim rests entirely on cited prior literature with no new free parameters, axioms, or invented entities introduced by the authors.

pith-pipeline@v0.9.0 · 5525 in / 1067 out tokens · 30643 ms · 2026-05-15T00:09:21.643705+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

What do these tags mean?
matches
The paper's claim is directly supported by a theorem in the formal canon.
supports
The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends
The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses
The paper appears to rely on the theorem as machinery.
contradicts
The paper's claim conflicts with a theorem or certificate in the canon.
unclear
Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

77 extracted references · 77 canonical work pages

  1. [1]

    3 -D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration and systems-on-chlp integration,

    K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3 -D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration and systems-on-chlp integration,” Proceedings of the IEEE, vol. 89, no. 5, pp. 602–632, 2001, doi: 10.1109/5.929647

    work page doi:10.1109/5.929647 2001

  2. [2]

    In: ACM/IEEE Design Automation Con- ference

    J. Kim, L. Zhu, H. M. Torun, M. Swaminathan, and S. K. Lim, “Micro - bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options,” Proc. Des. Autom. Conf., vol. 2021-December, pp. 1189– 1194, Dec. 2021, doi: 10.1109/DAC18074.2021.9586229

    work page doi:10.1109/dac18074.2021.9586229 2021

  3. [3]

    AMD Instinct MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems,

    A. Smith, “AMD Instinct MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems,” Nov. 2025. [Online]. Available: https://www.aihardware.mit.edu/amd-instinct

    work page 2025

  4. [4]

    State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding,

    J. H. Lau, “State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding,” Journal of Microelectronics and Electronic Packaging, vol. 18, no. 4, p. 410, 2021, doi: 10.4071/imaps.1542066

    work page doi:10.4071/imaps.1542066 2021

  5. [5]

    Silicon Reliability Characterization of Intel’s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking,

    C. Prasad et al., “Silicon Reliability Characterization of Intel’s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking,” IEEE International Reliability Physics Symposium Proceedings, vol. 2020-April, Apr. 2020, doi: 10.1109/IRPS45951.2020.9129277

    work page doi:10.1109/irps45951.2020.9129277 2020

  6. [6]

    A review of thermal performance of 3D stacked chips,

    Z. Wang, R. Dong, R. Ye, S. S. K. Singh, S. Wu, and C. Chen, “A review of thermal performance of 3D stacked chips,” Int. J. Heat Mass Transf., vol. 235, p. 126212, Dec. 2024, doi: 10.1016/j.ijheatmasstransfer.2024.126212

    work page doi:10.1016/j.ijheatmasstransfer.2024.126212 2024

  7. [7]

    Thermal management materials for 3D-stacked integrated circuits,

    W.-Y. Woon et al., “Thermal management materials for 3D-stacked integrated circuits,” Nature Reviews Electrical Engineering 2025 2:9, vol. 2, no. 9, pp. 598–613, Aug. 2025, doi: 10.1038/S44287-025-00196-0

    work page doi:10.1038/s44287-025-00196-0 2025

  8. [8]

    Interfacial thermal resistance: Past, present, and future,

    J. Chen, X. Xu, J. Zhou, and B. Li, “Interfacial thermal resistance: Past, present, and future,” Rev. Mod. Phys., vol. 94, no. 2, p. 025002, Apr. 2022, doi: 10.1103/RevModPhys.94.025002

    work page doi:10.1103/revmodphys.94.025002 2022

  9. [9]

    Thermal runaway in integrated circuits,

    A. Vassighi and M. Sachdev, “Thermal runaway in integrated circuits,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 2, pp. 300–305, Jun. 2006, doi: 10.1109/TDMR.2006.876577

    work page doi:10.1109/tdmr.2006.876577 2006

  10. [10]

    Thermal management of 3-D heterogeneously integrated microelectronics: challenges and future research directions,

    M. K. Sharma and B. Ramos-Alvarado, “Thermal management of 3-D heterogeneously integrated microelectronics: challenges and future research directions,” Communications Engineering 2026 5:1, vol. 5, no. 1, pp. 28-, Feb. 2026, doi: 10.1038/s44172-026-00590-y

    work page doi:10.1038/s44172-026-00590-y 2026

  11. [11]

    Ultra-fast Thermoreflectance Imaging for Electronic Optoelectronic and Thermal Devices,

    J.-H. Bahk and A. Shakouri, “Ultra-fast Thermoreflectance Imaging for Electronic Optoelectronic and Thermal Devices,” in Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2019, pp. 1–8. doi: 10.1109/ITHERM.2019.8757200

    work page doi:10.1109/itherm.2019.8757200 2019

  12. [12]

    HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design,

    W. Huang and others, “HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design,” IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 14, no. 5, pp. 501–513, May 2006, doi: 10.1109/TVLSI.2006.876103

    work page doi:10.1109/tvlsi.2006.876103 2006

  13. [13]

    Perspective on multi-scale simulation of thermal transport in solids and interfaces,

    M. Hu and Z. Yang, “Perspective on multi-scale simulation of thermal transport in solids and interfaces,” Physical Chemistry Chemical Physics, vol. 23, no. 3, pp. 1785–1801, Jan. 2021, doi: 10.1039/d0cp03372c

    work page doi:10.1039/d0cp03372c 2021

  14. [14]

    Ultra-fast Thermoreflectance Imaging for Electronic, Optoelectronic, and Thermal Devices,

    J. H. Bahk and A. Shakouri, “Ultra-fast Thermoreflectance Imaging for Electronic, Optoelectronic, and Thermal Devices,” 2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2019, Nov. 2019, doi: 10.1109/BCICTS45179.2019.8972732

    work page doi:10.1109/bcicts45179.2019.8972732 2019

  15. [15]

    Thermal analysis and interpolation techniques for a logic + WideIO stacked DRAM test chip,

    F. Beneventi, A. Bartolini, P. Vivet, and L. Benini, “Thermal analysis and interpolation techniques for a logic + WideIO stacked DRAM test chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 35, no. 4, pp. 623–636, Apr. 2016, doi: 10.1109/TCAD.2015.2474382

    work page doi:10.1109/tcad.2015.2474382 2016

  16. [16]

    Thermal Modeling and Analysis of High Bandwidth Memory in 2.5D Si-interposer Systems,

    T. Kim et al., “Thermal Modeling and Analysis of High Bandwidth Memory in 2.5D Si-interposer Systems,” InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM , vol. 2022- May, 2022, doi: 10.1109/iTherm54085.2022.9899586

    work page doi:10.1109/itherm54085.2022.9899586 2022

  17. [17]

    A Novel through Mold Plate (TMP) for Signal and Thermal Integrity Improvement of High Bandwidth Memory (HBM),

    K. Son et al., “A Novel through Mold Plate (TMP) for Signal and Thermal Integrity Improvement of High Bandwidth Memory (HBM),” 2020 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization, NEMO 2020, p. 9343473, Dec. 2020, doi: 10.1109/NEMO49486.2020.9343473

    work page doi:10.1109/nemo49486.2020.9343473 2020

  18. [18]

    Thermal analysis of a 3D die -stacked high- performance microprocessor,

    K. Puttaswamy and G. H. Loh, “Thermal analysis of a 3D die -stacked high- performance microprocessor,” Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, vol. 2006, pp. 19–24, 2006, doi: 10.1145/1127908.1127915

    work page doi:10.1145/1127908.1127915 2006

  19. [19]

    Designandsimulationofsymmetricwafer-to-waferbondingcompensating agravityeffect

    R. Mathur et al., “Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology,” Proceedings - Electronic Components and Technology Conference, vol. 2020- June, pp. 541–547, Jun. 2020, doi: 10.1109/ECTC32862.2020.00091

    work page doi:10.1109/ectc32862.2020.00091 2020

  20. [20]

    High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits; High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits,

    Ç. ˘ Gıl, K. ˘ Glu, and E. Pop, “High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits; High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits,” IEEE Electron Device Letters, vol. 44, no. 3, 2023, doi: 10.1109/LED.2023.3240676

    work page doi:10.1109/led.2023.3240676 2023

  21. [21]

    Thermal Modeling of a Chiplet - Based Packaging with a 2.5-D Through-Silicon Via Interposer,

    M. Zhou, L. Li, F. Hou, G. He, and J. Fan, “Thermal Modeling of a Chiplet - Based Packaging with a 2.5-D Through-Silicon Via Interposer,” IEEE Trans. Compon. Packaging Manuf. Technol., vol. 12, no. 6, pp. 956–963, Jun. 2022, doi: 10.1109/TCPMT.2022.3174608

    work page doi:10.1109/tcpmt.2022.3174608 2022

  22. [22]

    An efficient thermal model of chiplet heterogeneous integration system for steady-state temperature prediction,

    C. Wang, Q. Xu, C. Nie, H. Cao, J. Liu, and Z. Li, “An efficient thermal model of chiplet heterogeneous integration system for steady-state temperature prediction,” Microelectronics Reliability, vol. 146, no. 1, p. 115006, Jul. 2023, doi: 10.1016/j.microrel.2023.115006

    work page doi:10.1016/j.microrel.2023.115006 2023

  23. [23]

    Circuit models for the co-simulation of superconducting quantum computing systems,

    Y. Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan, and A. Joshi, “TAP - 2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems,” Proceedings -Design, Automation and Test in Europe, DATE, vol. 2021- February, pp. 1246–1251, Feb. 2021, doi: 10.23919/DATE51398.2021.9474011

    work page doi:10.23919/date51398.2021.9474011 2021

  24. [25]

    Thermomechanical stress -aware management for 3D IC designs,

    Q. Zou, T. Zhang, E. Kursun, and Y. Xie, “Thermomechanical stress -aware management for 3D IC designs,” Proceedings -Design, Automation and Test in Europe, DATE, pp. 1255–1258, 2013, doi: 10.7873/date.2013.260

    work page doi:10.7873/date.2013.260 2013

  25. [26]

    Nanoscale Thermal Transport,

    D. G. Cahill and others, “Nanoscale Thermal Transport,” J. Appl. Phys., vol. 93, no. 2, pp. 793–818, 2003, doi: 10.1063/1.1524305

    work page doi:10.1063/1.1524305 2003

  26. [27]

    Broadband phonon mean free path contributions to thermal conductivity measured using frequency domain thermoreflectance,

    K. T. Regner, D. P. Sellan, Z. Su, C. H. Amon, A. J. H. McGaughey, and J. A. Malen, “Broadband phonon mean free path contributions to thermal conductivity measured using frequency domain thermoreflectance,” Nature Communications 2013 4:1, vol. 4, no. 1, pp. 1640-, Mar. 2013, doi: 10.1038/ncomms2630

    work page doi:10.1038/ncomms2630 2013

  27. [28]

    Thermal boundary resistance,

    E. T. Swartz and R. O. Pohl, “Thermal boundary resistance,” Rev. Mod. Phys., vol. 61, no. 3, p. 605, Jul. 1989, doi: 10.1103/RevModPhys.61.605

    work page doi:10.1103/revmodphys.61.605 1989

  28. [29]

    Thermal boundary resistance predictions from molecular dynamics simulations and theoretical calculations,

    E. S. Landry and A. J. H. McGaughey, “Thermal boundary resistance predictions from molecular dynamics simulations and theoretical calculations,” Phys. Rev. B, vol. 80, no. 16, p. 165304, Oct. 2009, doi: 10.1103/PhysRevB.80.165304

    work page doi:10.1103/physrevb.80.165304 2009

  29. [30]

    A new channel percolation model for V/sub T/ shift in discrete-trap memories,

    F. Chen and others, “Measurements of Effective Thermal Conductivity for Advanced Interconnect Structures with Various Composite Low -K Dielectrics,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), Apr. 2004, pp. 526–532. doi: 10.1109/RELPHY.2004.1315380

    work page doi:10.1109/relphy.2004.1315380 2004

  30. [31]

    Wire bond challenges in low‐k devices,

    S. Narasimalu, “Wire bond challenges in low‐k devices,” Microelectronics International, vol. 25, no. 1, pp. 34–40, Dec. 2007, doi: 10.1108/13565360810846635

    work page doi:10.1108/13565360810846635 2007

  31. [32]

    A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System,

    C. Wang et al., “A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System,” IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 32, no. 1, pp. 178–189, Jan. 2024, doi: 10.1109/TVLSI.2023.3321933

    work page doi:10.1109/tvlsi.2023.3321933 2024

  32. [33]

    High Thermal Conductivity Insulators for Thermal Management in 3D ICs,

    M. J. Koroglu and K. E. Goodson, “High Thermal Conductivity Insulators for Thermal Management in 3D ICs,” IEEE Electron Device Letters, vol. 44, no. 6, pp. 923–926, Jun. 2023, doi: 10.1109/LED.2023.3264139

    work page doi:10.1109/led.2023.3264139 2023

  33. [34]

    On the Universality of Inversion Layer Mobility in Si MOSFETs: Part I—Effects of Substrate Impurity Concentration,

    S. Takagi and others, “On the Universality of Inversion Layer Mobility in Si MOSFETs: Part I—Effects of Substrate Impurity Concentration,” IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357–2362, Dec. 1994, doi: 10.1109/16.337449

    work page doi:10.1109/16.337449 1994

  34. [35]

    TSV Stress -Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC,

    M. Jung, J. Mitra, D. Z. Pan, and S. K. Lim, “TSV Stress -Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC,” | communIcaTIonS of The acm, vol. 57, no. 1, 2014, doi: 10.1145/2494536

    work page doi:10.1145/2494536 2014

  35. [36]

    Impact of mechanical stress on the full chip timing for through-silicon-via-based 3-D ICs,

    K. Athikulwongse, J. S. Yang, D. Z. Pan, and S. K. Lim, “Impact of mechanical stress on the full chip timing for through-silicon-via-based 3-D ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 6, pp. 905–917, 2013, doi: 10.1109/TCAD.2013.2237770

    work page doi:10.1109/tcad.2013.2237770 2013

  36. [37]

    Chip/package mechanical stress impact on 3-D IC reliability and mobility variations,

    M. Jung, D. Z. Pan, and S. K. Lim, “Chip/package mechanical stress impact on 3-D IC reliability and mobility variations,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , vol. 32, no. 11, pp. 1694– 1707, 2013, doi: 10.1109/TCAD.2013.2265372

    work page doi:10.1109/tcad.2013.2265372 2013

  37. [38]

    Manoj, H

    S. Manoj, H. Yu, Y. Shang, S. Tan, and S. K. Lim, “IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1 Reliable 3D Clock-tree Synthesis Considering Nonlinear Capacitive TSV Model with Electrical-thermal-mechanical Coupling,” 2013

    work page 2013

  38. [39]

    Survey of ab initio phonon thermal transport,

    L. Lindsay, C. Hua, X. L. Ruan, and S. Lee, “Survey of ab initio phonon thermal transport,” Materials Today Physics, vol. 7, no. 33, pp. 106–120, Dec. 2018, doi: 10.1016/j.mtphys.2018.11.008

    work page doi:10.1016/j.mtphys.2018.11.008 2018

  39. [41]

    JAX-BTE: A GPU-Accelerated Differentiable Solver for Phonon Boltzmann Transport Equation,

    H. Zhu and others, “JAX-BTE: A GPU-Accelerated Differentiable Solver for Phonon Boltzmann Transport Equation,” NPJ Comput. Mater., vol. 11, p. 90, May 2025, doi: 10.1038/s41524-025-01635-0

    work page doi:10.1038/s41524-025-01635-0 2025

  40. [42]

    Molecular dynamics simulation of thermal boundary conductance between carbon nanotubes and SiO2,

    Z. Y. Ong and E. Pop, “Molecular dynamics simulation of thermal boundary conductance between carbon nanotubes and SiO2,” Phys. Rev. B Condens. Matter Mater. Phys., vol. 81, no. 15, Apr. 2010, doi: 10.1103/PhysRevB.81.155408

    work page doi:10.1103/physrevb.81.155408 2010

  41. [43]

    Nonequilibrium Green’s functions (NEGF) in vibrational energy transport: a topical review,

    C. A. Polanco, “Nonequilibrium Green’s functions (NEGF) in vibrational energy transport: a topical review,” Nanoscale and Microscale Thermophysical Engineering, vol. 25, no. 1, pp. 1–24, Jan. 2021, doi: 10.1080/15567265.2021.1881193

    work page doi:10.1080/15567265.2021.1881193 2021

  42. [44]

    Nonequilibrium Green’s Function Approach to Phonon Transport in Defective Carbon Nanotubes,

    T. Yamamoto and K. Watanabe, “Nonequilibrium Green’s Function Approach to Phonon Transport in Defective Carbon Nanotubes,” Phys. Rev. Lett., vol. 96, no. 25, p. 255503, Jun. 2006, doi: 10.1103/PhysRevLett.96.255503

    work page doi:10.1103/physrevlett.96.255503 2006

  43. [45]

    High-efficiency green function-based thermal simulation algorithms,

    Y. Zhan and S. S. Sapatnekar, “High-efficiency green function-based thermal simulation algorithms,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1661–1675, Sep. 2007, doi: 10.1109/TCAD.2007.895754

    work page doi:10.1109/tcad.2007.895754 2007

  44. [46]

    3D -ICE: A compact thermal model for early-stage design of liquid-cooled ICs,

    A. Sridhar, A. Vincenzi, D. Atienza, and T. Brunschwiler, “3D -ICE: A compact thermal model for early-stage design of liquid-cooled ICs,” IEEE Transactions on Computers, vol. 63, no. 10, pp. 2576–2589, Oct. 2014, doi: 10.1109/TC.2013.127

    work page doi:10.1109/tc.2013.127 2014

  45. [47]

    Reduced Order Modeling of Transient Heat Transfer in Microchip Interconnects,

    A. Nokhosteen, M. Soltani, and B. Barabadi, “Reduced Order Modeling of Transient Heat Transfer in Microchip Interconnects,” J. Electron. Packag., vol. 141, no. 1, Mar. 2019, doi: 10.1115/1.4041666

    work page doi:10.1115/1.4041666 2019

  46. [48]

    The MTA: An advanced and versatile thermal simulator for integrated systems,

    S. Ladenheim, Y. C. Chen, M. Mihajlovic, and V. F. Pavlidis, “The MTA: An advanced and versatile thermal simulator for integrated systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 37, no. 12, pp. 3123–3136, Dec. 2018, doi: 10.1109/TCAD.2018.2789729

    work page doi:10.1109/tcad.2018.2789729 2018

  47. [49]

    Physics-Informed Deep Learning for Solving Phonon Boltzmann Transport Equation with Large Temperature Non-Equilibrium,

    R. Li and others, “Physics-Informed Deep Learning for Solving Phonon Boltzmann Transport Equation with Large Temperature Non-Equilibrium,” NPJ Comput. Mater., vol. 8, p. 29, Feb. 2022, doi: 10.1038/s41524-022- 00712-y

    work page doi:10.1038/s41524-022- 2022

  48. [50]

    Physics-informed neural networks for solving time-dependent mode-resolved phonon Boltzmann transport equation,

    J. Zhou, R. Li, and T. Luo, “Physics-informed neural networks for solving time-dependent mode-resolved phonon Boltzmann transport equation,” npj Computational Materials 2023 9:1, vol. 9, no. 1, pp. 212-, Nov. 2023, doi: 10.1038/s41524-023-01165-7

    work page doi:10.1038/s41524-023-01165-7 2023

  49. [51]

    Primer: Fast private transformer inference on encrypted data

    Z. Liu et al., “DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design,” Proc. Des. Autom. Conf., vol. 2023-July, 2023, doi: 10.1109/DAC56929.2023.10247998

    work page doi:10.1109/dac56929.2023.10247998 2023

  50. [52]

    Efficient ML-Based Transient Thermal Prediction for 3D- ICs,

    Y. F. Yang et al., “Efficient ML-Based Transient Thermal Prediction for 3D- ICs,” Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 7, pp. 628–634, Mar. 2025, doi: 10.1145/3658617.3697754

    work page doi:10.1145/3658617.3697754 2025

  51. [53]

    Self-Attention to Operator Learning-based 3D-IC Thermal Simulation,

    Z. Huang et al., “Self-Attention to Operator Learning-based 3D-IC Thermal Simulation,” Oct. 2025, Accessed: Mar. 22, 2026. [Online]. Available: http://arxiv.org/abs/2510.15968

    work page arXiv 2025

  52. [54]

    A multiscale thermal modeling approach for ballistic and diffusive heat transport in two dimensional domains,

    N. Donmezer and S. Graham, “A multiscale thermal modeling approach for ballistic and diffusive heat transport in two dimensional domains,” International Journal of Thermal Sciences, vol. 76, no. 7, pp. 235–244, Feb. 2014, doi: 10.1016/j.ijthermalsci.2013.09.004

    work page doi:10.1016/j.ijthermalsci.2013.09.004 2014

  53. [55]

    A hybrid phonon Monte Carlo -diffusion method for ballistic-diffusive heat conduction in nano- and micro- structures,

    H. L. Li, Y. C. Hua, and B. Y. Cao, “A hybrid phonon Monte Carlo -diffusion method for ballistic-diffusive heat conduction in nano- and micro- structures,” Int. J. Heat Mass Transf., vol. 127, no. 1, pp. 1014–1022, Dec. 2018, doi: 10.1016/j.ijheatmasstransfer.2018.06.080

    work page doi:10.1016/j.ijheatmasstransfer.2018.06.080 2018

  54. [56]

    Inversion for Thermal Properties with Frequency Domain Thermoreflectance,

    B. Treweek et al., “Inversion for Thermal Properties with Frequency Domain Thermoreflectance,” ACS Appl. Mater. Interfaces, vol. 16, no. 3, pp. 4117– 4125, Jan. 2024, doi: 10.1021/acsami.3c13658

    work page doi:10.1021/acsami.3c13658 2024

  55. [58]

    3D -ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation with Pluggable Heat Sink Models,

    F. Terraneo, A. Leva, W. Fornaciari, M. Zapater, and D. Atienza, “3D -ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation with Pluggable Heat Sink Models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 4, pp. 1062–1075, Apr. 2022, doi: 10.1109/TCAD.2021.3074613

    work page doi:10.1109/tcad.2021.3074613 2022

  56. [59]

    A review of thermoreflectance techniques for characterizing wide bandgap semiconductors’ thermal properties and devices’ temperatures,

    C. Yuan, R. Hanus, and S. Graham, “A review of thermoreflectance techniques for characterizing wide bandgap semiconductors’ thermal properties and devices’ temperatures,” J. Appl. Phys., vol. 132, no. 22, p. 220701, Dec. 2022, doi: 10.1063/5.0122200

    work page doi:10.1063/5.0122200 2022

  57. [60]

    Quantifying uncertainty in multiscale heat conduction calculations,

    P. Marepalli, J. Y. Murthy, B. Qiu, and X. Ruan, “Quantifying uncertainty in multiscale heat conduction calculations,” J. Heat Transfer, vol. 136, no. 11, Nov. 2014, doi: 10.1115/1.4027348

    work page doi:10.1115/1.4027348 2014

  58. [61]

    Smart Temperature Sensors in Standard CMOS,

    K. A. A. Makinwa, “Smart Temperature Sensors in Standard CMOS,” Procedia Eng., vol. 5, pp. 930–939, 2010, doi: 10.1016/j.proeng.2010.09.262

    work page doi:10.1016/j.proeng.2010.09.262 2010

  59. [62]

    Thermal monitoring mechanisms for chip multiprocessors,

    J. Long, S. O. Memik, G. Memik, and R. Mukherjee, “Thermal monitoring mechanisms for chip multiprocessors,” Transactions on Architecture and Code Optimization, vol. 5, no. 2, Aug. 2008, doi: 10.1145/1400112.1400114

    work page doi:10.1145/1400112.1400114 2008

  60. [63]

    CMOS temperature sensor with ring oscillator for mobile DRAM self -refresh control,

    C. C. Chen, P. Chen, A. W. Liu, W. F. Lu, and Y. C. Chang, “CMOS temperature sensor with ring oscillator for mobile DRAM self -refresh control,” Microelectronics J., vol. 38, no. 10–11, pp. 1042–1049, Oct. 2007, doi: 10.1088/0957-0233/17/4/031

    work page doi:10.1088/0957-0233/17/4/031 2007

  61. [64]

    A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution,

    M. Kuball and J. W. Pomeroy, “A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution,” IEEE Transactions on Device and Materials Reliability, vol. 16, no. 4, pp. 667–684, Dec. 2016, doi: 10.1109/TDMR.2016.2617458

    work page doi:10.1109/tdmr.2016.2617458 2016

  62. [65]

    Time -domain thermoreflectance,

    R. Mohan, S. Khan, R. B. Wilson, and P. E. Hopkins, “Time -domain thermoreflectance,” Nature Reviews Methods Primers 2025 5:1, vol. 5, no. 1, pp. 55-, Aug. 2025, doi: 10.1038/s43586-025-00425-8

    work page doi:10.1038/s43586-025-00425-8 2025

  63. [66]

    Measurements of Thermal Resistance Across Buried Interfaces with Frequency-Domain Thermoreflectance,

    B. A. Cola and others, “Measurements of Thermal Resistance Across Buried Interfaces with Frequency-Domain Thermoreflectance,” ACS Appl. Mater. Interfaces, vol. 16, no. 30, pp. 39826–39836, Jul. 2024, doi: 10.1021/acsami.4c05258

    work page doi:10.1021/acsami.4c05258 2024

  64. [67]

    Uncertainty analysis of thermoreflectance measurements,

    J. Yang, E. Ziade, and A. J. Schmidt, “Uncertainty analysis of thermoreflectance measurements,” Review of Scientific Instruments, vol. 87, no. 1, p. 14901, Jan. 2016, doi: 10.1063/1.4939671

    work page doi:10.1063/1.4939671 2016

  65. [68]

    Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs,

    H. Oprins, V. Cherman, C. Torregiani, M. Stucchi, B. Vandevelde, and E. Beyne, “Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs,” Electronics System Integration Technology Conference, ESTC 2010 - Proceedings, 2010, doi: 10.1109/ESTC.2010.5642955

    work page doi:10.1109/estc.2010.5642955 2010

  66. [69]

    Javier Mesa-martinez, E

    F. Javier Mesa-martinez, E. K. Ardestani, J. Renau, and F. J. Mesa-Martínez Ehsan K Ardestani Jose Renau, “Characterizing processor thermal behavior Open Access Support provided by: Citation in BibTeX format ASPLOS ’10: Architectural Support for Programming Languages and Operating Systems Characterizing Processor Thermal Behavior,” Proceedings of the fift...

    work page doi:10.1145/1736020.1736043 2010

  67. [70]

    The impact of technology scaling on lifetime reliability,

    J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, “The impact of technology scaling on lifetime reliability,” Proceedings of the International Conference on Dependable Systems and Networks, pp. 177–186, 2004, doi: 10.1109/dsn.2004.1311888

    work page doi:10.1109/dsn.2004.1311888 2004

  68. [71]

    Electromigration in three-dimensional integrated circuits,

    Z. Shen, S. Jing, Y. Heng, Y. Yao, K. N. Tu, and Y. Liu, “Electromigration in three-dimensional integrated circuits,” Appl. Phys. Rev., vol. 10, no. 2, p. 21309, Jun. 2023, doi: 10.1063/5.0139658

    work page doi:10.1063/5.0139658 2023

  69. [72]

    Improving DRAM Performance in 3 -D ICs via Temperature Aware Refresh,

    M. Guan and L. Wang, “Improving DRAM Performance in 3 -D ICs via Temperature Aware Refresh,” IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 25, no. 3, pp. 833–843, Mar. 2017, doi: 10.1109/TVLSI.2016.2606085

    work page doi:10.1109/tvlsi.2016.2606085 2017

  70. [73]

    Thermal -Aware Fixed- Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach,

    W. Guan, X. Tang, H. Lu, Y. Zhang, and Y. Zhang, “Thermal -Aware Fixed- Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach,” IEEE Trans. Very Large Scale Integr. VLSI Syst. , vol. 31, no. 12, pp. 1882– 1895, Dec. 2023, doi: 10.1109/TVLSI.2023.3321532

    work page doi:10.1109/tvlsi.2023.3321532 2023

  71. [74]

    Thermal and mechanical reliability of thermal through-silicon vias in three-dimensional integrated circuits,

    C. Qu, R. Dai, J. Zheng, Y. Hu, and J. Zhang, “Thermal and mechanical reliability of thermal through-silicon vias in three-dimensional integrated circuits,” Microelectronics Reliability, vol. 143, no. SPL CONTENT, p. 114952, Apr. 2023, doi: 10.1016/j.microrel.2023.114952

    work page doi:10.1016/j.microrel.2023.114952 2023

  72. [75]

    Three -dimensional chip- multiprocessor run-time thermal management,

    C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Joseph, “Three -dimensional chip- multiprocessor run-time thermal management,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 27, no. 8, pp. 1479–1492, Aug. 2008, doi: 10.1109/TCAD.2008.925793

    work page doi:10.1109/tcad.2008.925793 2008

  73. [76]

    Cu - Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application,

    Y. C. Huang, Y. X. Lin, C. K. Hsiung, T. H. Hung, and K. N. Chen, “Cu - Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application,” Nanomaterials 2023, Vol. 13, vol. 13, no. 17, Sep. 2023, doi: 10.3390/nano13172490

    work page doi:10.3390/nano13172490 2023

  74. [77]

    3D Integrated Circuit Cooling with Microfluidics,

    S. Wang, Y. Yin, C. Hu, and P. Rezai, “3D Integrated Circuit Cooling with Microfluidics,” Micromachines 2018, Vol. 9, vol. 9, no. 6, Jun. 2018, doi: 10.3390/mi9060287

    work page doi:10.3390/mi9060287 2018

  75. [78]

    Cryo-CMOS Circuits and Systems for Quantum Computing Applications,

    B. Patra et al., “Cryo-CMOS Circuits and Systems for Quantum Computing Applications,” IEEE Journal of Solid State Circuits, vol. 53, no. 1, pp. 309– 321, Jan. 2018, doi: 10.1109/JSSC.2017.2737549

    work page doi:10.1109/jssc.2017.2737549 2018

  76. [79]

    Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions [Feature],

    S. Chakraborty and R. V. Joshi, “Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions [Feature],” IEEE Circuits and Systems Magazine, vol. 24, no. 2, pp. 34–46, 2024, doi: 10.1109/MCAS.2024.3383808

    work page doi:10.1109/mcas.2024.3383808 2024

  77. [80]

    Kapitza Resistance,

    G. L. Pollack, “Kapitza Resistance,” Rev. Mod. Phys., vol. 41, no. 1, p. 48, Jan. 1969, doi: 10.1103/RevModPhys.41.48

    work page doi:10.1103/revmodphys.41.48 1969