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Scalable error mitigation for noisy quantum circuits produces competitive expectation values

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arxiv 2108.09197 v1 pith:L2AT7ZFK submitted 2021-08-20 quant-ph cond-mat.mes-hall

Scalable error mitigation for noisy quantum circuits produces competitive expectation values

classification quant-ph cond-mat.mes-hall
keywords quantumerrorcircuitsmitigationapproximationscircuitcomputationdemonstrate
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Noise in existing quantum processors only enables an approximation to ideal quantum computation. However, these approximations can be vastly improved by error mitigation, for the computation of expectation values, as shown by small-scale experimental demonstrations. However, the practical scaling of these methods to larger system sizes remains unknown. Here, we demonstrate the utility of zero-noise extrapolation for relevant quantum circuits using up to 26 qubits, circuit depths of 60, and 1080 CNOT gates. We study the scaling of the method for canonical examples of product states and entangling Clifford circuits of increasing size, and extend it to the quench dynamics of 2-D Ising spin lattices with varying couplings. We show that the efficacy of the error mitigation is greatly enhanced by additional error suppression techniques and native gate decomposition that reduce the circuit time. By combining these methods, we demonstrate an accuracy in the approximate quantum simulation of the quench dynamics that surpasses the classical approximations obtained from a state-of-the-art 2-D tensor network method. These results reveal a path to a relevant quantum advantage with noisy, digital, quantum processors.

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Cited by 4 Pith papers

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    Presents unbiased uncertainty quantification for post-processing error mitigation and applies it to optimize hyperparameters in Zero Noise Extrapolation and Clifford Data Regression under finite-shot noise.

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    Dissipative protocols on quantum hardware prepare approximate thermal states for kagome AFIM up to 79 sites and AFHM via simulation, with circuit depth independent of size and linear in inverse temperature.