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A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

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arxiv 2304.13840 v2 pith:WQJHVWEX submitted 2023-04-26 cs.LG cs.SE

Enrique Dehaerne , Bappaditya Dey , Sandip Halder , Stefan De Gendt This is my paper
classification cs.LGcs.SE
keywords verilogdesignframeworkautocompletiondatasetautomationcodedata
verification ladder T0 review T1 audit T2 compute T3 formal
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Innovative Electronic Design Automation (EDA) solutions are important to meet the design requirements for increasingly complex electronic devices. Verilog, a hardware description language, is widely used for the design and verification of digital circuits and is synthesized using specific EDA tools. However, writing code is a repetitive and time-intensive task. This paper proposes, primarily, a novel deep learning framework for training a Verilog autocompletion model and, secondarily, a Verilog dataset of files and snippets obtained from open-source repositories. The framework involves integrating models pretrained on general programming language data and finetuning them on a dataset curated to be similar to a target downstream task. This is validated by comparing different pretrained models trained on different subsets of the proposed Verilog dataset using multiple evaluation metrics. These experiments demonstrate that the proposed framework achieves better BLEU, ROUGE-L, and chrF scores by 9.5%, 6.7%, and 6.9%, respectively, compared to a model trained from scratch. Code and data are made available at: https://github.com/99EnriqueD/verilog_autocompletion .

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code

    cs.AR 2025-09 conditional novelty 6.0 of 10

    AutoVeriFix improves LLM-generated Verilog functional correctness by generating a high-level Python reference model, deriving a high-coverage testbench, and iteratively fixing Verilog simulation mismatches.

  2. ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation

    cs.AR 2026-07 conditional novelty 5.0 of 10

    On 64 large OpenCores-derived Verilog tasks, top LLMs reach 23.6% functional pass@1, 37.5% pass@5, and 0% on designs with two or more submodules, showing hierarchical RTL generation remains unsolved.

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