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Scaffold-Assisted Window Junctions for Superconducting Qubit Fabrication

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arxiv 2503.11010 v1 pith:WPTTSYUL submitted 2025-03-14 physics.app-ph quant-ph

Scaffold-Assisted Window Junctions for Superconducting Qubit Fabrication

classification physics.app-ph quant-ph
keywords fabricationqubitjunctionprocessjosephsonqualityscaffoldvapor
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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The superconducting qubit is one of the promising directions in realizing fault-tolerant quantum computing (FTQC), which requires many high-quality qubits. To achieve this, it is desirable to leverage modern semiconductor industry technology to ensure quality, uniformity, and reproducibility. However, conventional Josephson junction fabrication relies mainly on resist-assistant double-angle evaporation, posing integration challenges. Here, we demonstrate a lift-off-free qubit fabrication that integrates seamlessly with existing industrial technologies. This method employs a silicon oxide (SiO$_2$) scaffold to define an etched window with a well-controlled size to form a Josephson junction. The SiO$_2$, which has a large dielectric loss, is etched away in the final step using vapor HF leaving little residue. This Window junction (WJ) process mitigates the degradation of qubit quality during fabrication and allows clean removal of the scaffold. The WJ process is validated by inspection and Josephson junction measurement. The scaffold removal process is verified by measuring the quality factor of the resonators. Furthermore, compared to scaffolds fabricated by plasma-enhanced chemical vapor deposition (PECVD), qubits made by WJ through physical vapor deposition (PVD) achieve relaxation time up to $57\,\mu\text{s}$. Our results pave the way for a lift-off-free qubit fabrication process, designed to be compatible with modern foundry tools and capable of minimizing damage to the substrate and material surfaces.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. On-chip stencil lithography for superconducting qubits

    quant-ph 2025-07 unverdicted novelty 6.0

    An on-chip SiO2/Si3N4 stencil lithography mask enables shadow evaporation of Al Josephson junctions, demonstrated with transmon qubits achieving average T1 of 75 μs.

  2. Review of Superconducting Qubit Devices and Their Large-Scale Integration

    quant-ph 2026-02 accept novelty 1.0

    A review summarizing superconducting qubit types, DiVincenzo criteria implementations, coherence limits from defects, and large-scale integration strategies for quantum computing.