Paper Citation Record · LEDGER

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:2504.03711.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2504.03711 v3

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 6 of 6 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 6 of 6 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T05:54:36.455488Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-10T10:49:56.153974Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 52356c5e-ff2b-49cc-bbfb-2b415e67ecdf · inbound

FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks cites this paper.

FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-07T05:54:36.455488Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8182becf-67f1-4e76-ae78-588228c276f4 · inbound

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs cites this paper.

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-06T15:51:34.486369Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f9fb87bf-ac4b-4600-9a36-daa0e4a5c954 · inbound

Discovering heuristics in a complex SAT solver with large language models cites this paper.

Discovering heuristics in a complex SAT solver with large language models A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-06T11:18:48.720836Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 70ba4d8f-5755-4329-82b8-e19d1abf3301 · inbound

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits cites this paper.

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-05T16:00:39.535353Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation edce3f66-c69c-4456-a15e-3b8ed186c6fb · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.380774Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 570281b2-95bb-4dbd-b284-138768fa4fd2 · inbound

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement cites this paper.

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Reference 14

Resolution: verified exact; arxiv_id, observed 2026-07-03T02:17:05.300504Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.