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Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides

T0 review · 4 major / 4 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read Top-down patterned monolayer transition-metal dichalcogenide nanoribbons retain high current density down to 25 nm channel widths, setting records for single-gated nanoribbons.

desk verdict Strong experimental paper; the central claim is credible, but the headline records rest on single devices and a 10-20% width uncertainty that isn't propagated. read the letter →

arxiv 2509.09964 v3 pith:25SM65WW submitted 2025-09-12 cond-mat.mtrl-sci cond-mat.mes-hall

Tara Peña , Anton E. O. Persson , Andrey Krayev , Áshildur Fri{ḥriksdóttir , Haotian Su , Yuan-Mau Lee , Young Suh Song , Kathryn Neilson
show 8 more authors
Zhepeng Zhang Anh Tuan Hoang Jerry A. Yang Lauren Hoang Shan X. Wang Andrew J. Mannix Paul C. McIntyre Eric Pop
This is my paper · ORCID
classification cond-mat.mtrl-scicond-mat.mes-hall
keywords two-dimensionalsemiconductorstransitionmetaldichalcogenidesnanoribbontransistorMoS2WS2WSe2tip-enhancedphotoluminescencegate-all-aroundnanosheet
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports that monolayer transition-metal dichalcogenide (TMD) nanoribbons can be scaled to channel widths of 25 nm and lengths of 50 nm without losing the high on-state currents seen in micrometer-wide devices. Using a top-down multi-patterning process with 'anchored' contacts that hold the fragile monolayer to the substrate, the authors fabricate n-type MoS2 and WS2 and p-type WSe2 nanoribbons and measure on-state currents of 560, 420, and 130 µA/µm at 1 V drain bias, respectively. The WS2 result is more than 100 times higher than prior single-gated WS2 nanoribbons and comes in a normally-off (enhancement-mode) device. Nanoscale imaging with tip-enhanced photoluminescence, Raman spectroscopy, and electron microscopy shows no obvious edge damage, which the authors take as evidence that edge effects are not limiting at these dimensions. If correct, this clears a major obstacle to using monolayer TMDs as channels in future gate-all-around nanosheet transistors.

What carries the argument

Two fabrication innovations carry the argument. The 'anchored' contact uses a dog-bone-shaped TMD pattern, in which the ribbon widens into micrometer-scale pads under the source and drain contacts; this prevents delamination and yields over 90% working devices at 75 nm width. A litho-etch-litho-etch (LELE) multi-patterning scheme defines ribbons down to ~25 nm while keeping electron-beam dose low and thus limiting lithographic damage. Supporting evidence comes from tip-enhanced photoluminescence and electron microscopy, which show minimal edge degradation, and from transfer-length-method measurements giving contact resistance comparable to the best reported MoS2/Au contacts. Current densitie

What would settle it

Fabricate a width series of monolayer MoS2 nanoribbons from ~20 to ~100 nm on one chip, extract physical widths by the paper's Gaussian FWHM method, and plot saturation current per micron at fixed gate overdrive. If the points do not scale linearly with width, or if the 25 nm device's current density is not reproducible across several nominally identical devices, the claim that width scaling preserves current density would be contradicted. A gated Hall measurement that independently determines the conducting width would cross-check the normalization directly.

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Extended reading notes

Core claim

The central claim is that top-down patterned monolayer TMD nanoribbons with channel widths down to 25 nm and lengths down to 50 nm achieve on-state currents of 560, 420, and 130 µA/µm at VDS = 1 V for MoS2, WS2, and WSe2, respectively, surpassing prior reports for single-gated nanoribbons, the WS2 by over 100 times, even in normally-off (enhancement-mode) transistors. The authors further claim that these narrow ribbons perform as well as co-fabricated micrometer-wide control devices, and that their edges remain smooth at the few-nanometer scale with mixed zigzag/armchair termination. Taken together, the paper argues that width scaling does not degrade transport in monolayer TMDs at these dim

Load-bearing premise

The load-bearing premise is that the electrically active channel width equals the physical width read from AFM/SEM contrast profiles; if the conducting path is narrower (edge depletion or reduced carrier density at mixed zigzag/armchair edges), the reported current densities are systematically overestimated by 10–20%.

Editorial extensions

If this is right

  • If correct, top-down monolayer TMD nanoribbons can serve as the channel building block for gate-all-around nanosheet transistors, since sub-50 nm widths do not cost current density.
  • Monolayer WS2 nanoribbons combine normally-off operation with current densities over 100 times larger than prior single-gated WS2 nanoribbons, making WS2 viable for low-power logic.
  • The p-type WSe2 nanoribbon result at 130 µA/µm with enhancement-mode behavior narrows the historical performance gap between n- and p-type 2D transistors.
  • The absence of measurable edge conduction in the off-state (on/off ratios above 10^8) implies that top-down edges do not create leakage paths at these widths.
  • Because the process works for three different TMDs and with thin HfO2 dielectrics, the anchored-contact and multi-patterning approach should transfer to other monolayer semiconductors.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • My inference: the same process should be pushed to ~10 nm widths; below some width the mixed zigzag/armchair edges that suppress leakage will likely start scattering carriers, setting a lower limit the paper does not sample.
  • My inference: the single-gate geometry used here is a test vehicle; moving to gate-all-around nanosheet transistors will change electrostatics and contact geometry, so the exact current-density numbers may not carry over.
  • My inference: the >100x benchmark improvement over prior WS2 nanoribbons may partly reflect different width definitions across laboratories; a standardized width metrology would make such comparisons trustworthy.
  • My inference: the low off-state leakage in nanoribbon arrays suggests dense packing is feasible; measuring threshold-voltage variation across many 25 nm devices would test manufacturability.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper reports top-down fabricated monolayer MoS2, WS2, and WSe2 nanoribbon transistors with channel widths down to 25 nm and lengths down to 50 nm, using 'anchored' contacts and a litho-etch-litho-etch (LELE) multi-patterning approach. The central claim is that these devices reach on-state current densities of 560, 420, and 130 µA/µm at VDS = 1 V for MoS2, WS2, and WSe2, respectively, when integrated with thin HfO2, and that the WS2 value surpasses previous single-gated monolayer TMD nanoribbons by over 100×, even in enhancement-mode operation. The paper also presents TLM contact-resistance extraction on ~30 devices, low-temperature transport, Raman/TEPL/TEM edge characterization, and off-state array measurements, and concludes that nanoribbon width scaling down to ~25 nm does not degrade transport, supporting the viability of TMD nanoribbons for future nanosheet transistors.

Significance. If the quantitative claims hold, the paper is significant: it would be one of the first demonstrations that top-down patterned monolayer TMD nanoribbons retain high current density at widths relevant to future gate-all-around nanosheet transistors, and it extends the material set to n-type MoS2, n-type WS2, and p-type WSe2. The fabrication advances (anchored contacts, LELE patterning) and the combination of electrical, optical, and structural characterization are genuine strengths. The TLM dataset with 30 devices and the low-temperature measurements add statistical and physical depth. However, the headline record claims depend on width-normalization assumptions and on single devices at the smallest widths, and the '>100×' benchmark is not independently verifiable from the provided text. These issues are load-bearing for the paper's central advertised conclusions, so the significance is conditional on their resolution.

major comments (4)
  1. [MoS2 nanoribbons (Fig. 2d) and Methods (width extraction)] The record current densities are normalized by channel widths extracted from Gaussian FWHM fits to AFM/SEM contrast line profiles. The paper acknowledges '3-5 nm uncertainty of our nanoribbon width estimates... which implies 10 to 20% uncertainty of current density,' but neither the abstract nor Fig. 2d propagates this uncertainty into the reported 560/420/130 µA/µm values or the 'over 100×' benchmark. At 25 nm width, a 3-5 nm error is 12-20%, comparable to or larger than the claimed record margins. The bias could also be signed: AFM tip convolution may overestimate width (making the quoted current density conservative), while edge depletion or reduced active width would make it an overestimate of active-channel current density. Please provide explicit error bars or ranges on all quoted current densities, state the direction of the likely bias, and discuss whether the electrically active
  2. [Figs. 2d and 4c; conclusions] The 43 nm and 25 nm MoS2 devices in Fig. 2d are described as 'two such devices' with no statistics, and the high-κ devices in Fig. 4c are presented as single representative curves without error bars or replicate counts. The robust 30-device TLM dataset is at 75 nm width, not at the 25-50 nm widths that support the 'record' and 'no degradation' claims. For load-bearing quantitative claims, either provide multiple devices at each width/dielectric condition with mean±spread, or explicitly state in the abstract and conclusions that the sub-50 nm and high-κ values are single-device demonstrations subject to width uncertainty. Without this, the 'highest current density reported to date' and 'no performance degradation' statements overreach the presented data.
  3. [High-κ dielectric integration and benchmarking (Fig. 4e/f)] The claim that the WS2 nanoribbon exceeds prior reports 'by over 100 times' is supported only by a reference to Supplementary Table S1, which is not present in the provided manuscript text. The main-text benchmarking plots (Fig. 4e/f) do not let the reader reproduce the comparison: prior values are shown as unlabeled/small markers with no numerical values, and the conditions (VDS, VGS range, width definition, enhancement vs. depletion mode) are not tabulated. Since this is the paper's most striking quantitative benchmark, the comparison must be made verifiable: add the supplementary table, list the prior WS2 device parameters and measured currents, and specify the normalization conventions used. Otherwise the '>100×' claim cannot be independently assessed.
  4. [Material characterization (Fig. 3) and conclusions] The edge-quality evidence (Raman down to ~45 nm, TEPL on ~75 nm ribbons, TEM on transferred arrays) is presented as supporting the absence of edge degradation at the record dimensions, but it is not obtained on the specific 25 nm or 50 nm high-κ devices that carry the headline claims. The TEM samples also underwent an additional transfer step that could alter edge structure. Please either provide edge characterization on ribbons at/near the record widths, or temper the conclusion that 'minimal edge degradation' is verified at the dimensions claimed in the abstract. This distinction matters because the width-dependence of edge conduction/depletion is one of the key physics questions motivating the study.
minor comments (4)
  1. [Abstract and Introduction] The abstract reports 560 µA/µm for MoS2 with HfO2, while the introduction states 'over 600 μA μm-1 with SiO2 gate dielectric (560 μA μm-1 with HfO2 dielectric)' and Fig. 2d shows ~620 µA/µm for the 43 nm SiO2 device. Please make the dielectric/width conditions consistent across abstract, introduction, and figure captions to avoid apparent mismatches.
  2. [Fig. 2d caption] The transfer curves for the 43 nm and 25 nm devices are individual curves with no markers indicating sample count. Even if replicate data are not shown, the caption should state explicitly how many devices were measured and whether the curves are representative or best-case.
  3. [Fig. 4e/f caption] The caption says 'Unlabeled symbols are MoS2' but several symbols in the plotted region are not individually distinguished; adding a legend or listing the numerical values of prior works in the text or a table would improve reproducibility of the benchmark.
  4. [Methods] The width extraction description states that AFM and/or SEM were used, but it is not stated how the two techniques were cross-calibrated or whether the Gaussian FWHM was measured on the channel region or on a wider pad. A sentence clarifying the extraction protocol and its validation would help the reader judge the 3-5 nm uncertainty estimate.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: all headline currents are direct I_D measurements normalized by an independently measured AFM/SEM width; self-citations are process benchmarks, not inputs.

full rationale

The paper's central claims—on-state currents of roughly 560, 420, and 130 µA/µm for MoS2, WS2, and WSe2, and the >100× WS2 benchmark—are direct electrical measurements (I_D) divided by a channel width extracted from AFM/SEM contrast line profiles. No model, fit, or theoretical derivation is used to produce these values. The width normalization (Gaussian FWHM of the line profile) is independent physical metrology, and the paper explicitly acknowledges its uncertainty: 'We note 3-5 nm uncertainty of our nanoribbon width estimates ... which implies 10 to 20% uncertainty of current density.' Thus the width is not a tuning parameter chosen to force a record current. The TLM contact-resistance extraction (Rc < 560 Ω·µm) is a standard linear fit to measured Rtot versus Lch and is not an input to the headline currents. Self-citations (refs 6, 17, 23, 42–45) appear as process benchmarks, synthesis recipes, contact engineering references, and TEPL instrument methodology; none defines the claimed current densities, and none is invoked as a uniqueness theorem or ansatz that makes the experimental results true by definition. The caveats that do exist are evidentiary rather than circular: the >100× WS2 comparison is deferred to Supplementary Table S1 (not present in the provided text), the microscopy edge-quality evidence was obtained on 75 nm or transferred ribbons rather than on the specific 25 nm record device, and the narrowest devices are single samples with acknowledged width error. These affect confidence in the quantitative record but do not make the measurement chain self-referential. No circular step is present.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new free parameters or invented entities. Its central claims rely on domain assumptions about monolayer TMD material quality, transport regime, and edge termination, all grounded in cited prior work, plus measurement conventions for width and VT.

assumptions (4)
  • domain assumption Monolayer TMDs grown by CVD used here have the same intrinsic transport properties (mobility, mean free path) as previous reports (refs 7, 8, 20).
    The paper compares its nanoribbon performance to micrometer-wide controls on the same chip, which partially grounds this, but the 'record' claims assume the material quality is comparable to the best prior reports.
  • domain assumption Electron mean free path of monolayer MoS2 is 3-5 nm (ref 20), so a 75 nm ribbon is in the diffusive, not edge-limited, regime.
    Used to explain why no mobility degradation is seen with width; depends on an external simulation result from the same group (ref 20), which is cited but not independently verified here.
  • domain assumption Mixed zigzag/armchair edge termination produced by top-down etching does not create conducting edge states (refs 15, 39).
    Used to explain the absence of off-state edge conduction; supported by two prior theory papers.
  • domain assumption XeF2 dry etching and the CSAR resist process do not introduce electrically active defects beyond what Raman/TEPL can detect.
    The conclusion of minimal edge degradation rests on the sensitivity of these spectroscopic probes; the paper acknowledges transferred TEM samples may differ from actual devices.

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Cite this review

Pith. "Pith review of Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides." pith.science (2026). https://pith.science/paper/25SM65WW

@misc{pith2026250909964,
  author       = {Pith},
  title        = {Pith review of: Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/25SM65WW}},
  note         = {Machine review of arXiv:2509.09964}
}
abstract

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved only in micrometer-wide channels. Here, we demonstrate both $\it{n}$- and $\it{p}$-type nanoribbon transistors based on monolayer 2DS, fabricated using a multi-patterning process, reaching channel widths and lengths down to 25-30 nm. 'Anchored' contacts improve device yield, while nanoscale imaging, including tip-enhanced photoluminescence, reveals minimal edge degradation. The devices reach on-state currents up to 560, 420, and 130 $\mu$A $\mu$m$^{-1}$ at 1 V drain-to-source voltage for $\it{n}$-type MoS$_{2}$, WS$_{2}$, and $\it{p}$-type WSe$_{2}$, respectively, integrated with thin high-$\kappa$ dielectrics. These results surpass prior reports for single-gated nanoribbons, the WS$_{2}$ by over 100 times, even in normally off (enhancement-mode) transistors. Taken together, these findings suggest that top down patterned 2DS nanoribbons are promising building blocks for future nanosheet transistors.

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Breaking the width-scaling limit in high-performance atomically thin 2D nanoribbon transistors

    cond-mat.mes-hall 2026-06 unverdicted novelty 6.0 of 10

    Monolayer and bilayer MoS2 nanoribbon transistors down to 15 nm width show up to 230% and 170% higher on-current density than wider devices, with high on/off ratios and improved mobility.

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Pith tools

Reviewed August 4, 2026 · model on record in the stance chip above.