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arxiv: 2512.08152 · v1 · submitted 2025-12-09 · ❄️ cond-mat.mes-hall · quant-ph

Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor

Pith reviewed 2026-05-17 00:08 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall quant-ph
keywords spin qubitsgate-all-around transistorqubit readoutsiliconTCADSPICECMOS
0
0 comments X

The pith

Silicon spin qubit readout works through state-dependent current in a gate-all-around transistor.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The authors simulate how a logical spin qubit made of two physical qubits affects the current in a surrounding gate-all-around transistor due to different charge distributions from spin states. They use 3D TCAD simulations to model the current-voltage characteristics for various qubit and transistor configurations. Circuit simulations with SPICE then show that a standard CMOS sense amplifier circuit can amplify these signals if voltages are controlled dynamically. This demonstrates a path to reading out spin qubits using conventional semiconductor technology. The approach relies on electrostatic effects rather than direct magnetic sensing.

Core claim

Different spin configurations in the logical qubit lead to distinct electrostatic effects on the GAA transistor, resulting in measurable differences in the current flowing through it. Simulations confirm that a properly designed CMOS circuit with dynamic voltage control allows a conventional sense amplifier to detect the qubit state effectively.

What carries the argument

The gate-all-around transistor, whose current is modulated by the electrostatic potential from the qubit's spin-dependent charge distribution.

If this is right

  • The readout process can be integrated into standard CMOS fabrication flows.
  • Existing TCAD and SPICE tools are sufficient to design and verify such hybrid quantum-classical circuits.
  • Dynamic control of voltages enables reliable detection despite weak signals from the qubits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If successful in hardware, this could allow spin qubits to be embedded directly in classical control electronics on the same chip.
  • Scaling to larger qubit arrays would require simulating interference between multiple GAA sensors.
  • Alternative readout methods might be compared for power efficiency in future designs.

Load-bearing premise

The electrostatic effects from different spin configurations must produce current differences large enough to be distinguished from noise and fabrication variations.

What would settle it

An experiment measuring the actual current difference in a fabricated GAA transistor with controlled spin states and comparing it to the simulated values and noise levels.

Figures

Figures reproduced from arXiv: 2512.08152 by Keiji Ono, Tetsufumi Tanamoto.

Figure 1
Figure 1. Figure 1: FIG. 1. A logical qubit is defined using two coupled quantum [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Current-voltage characteristics of the type-A con [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. (a) A unit of the qubit (two quantum dots) and [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. An example of stacking the qubit arrays of Fig. 2. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Current-voltage characteristics of the type-A config [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Electric potential profile of the [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Current density profile of the [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Qubit readout circuit based on the comparison of two [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Time-dependent circuit behaviors for two types of [PITH_FULL_IMAGE:figures/full_fig_p007_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. Time-dependent circuit behaviors for two types of [PITH_FULL_IMAGE:figures/full_fig_p007_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. We can arrange the qubits and GAA transistor [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. (a) [PITH_FULL_IMAGE:figures/full_fig_p009_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. The qubit operation is based on the Heisenberg coupling between quantum dots. (a) Qubit-qubit interaction between [PITH_FULL_IMAGE:figures/full_fig_p010_13.png] view at source ↗
read the original abstract

We theoretically investigated the readout process of a spin--qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configurations result in different charge distributions, which subsequently influence the electrostatic effects on the GAA transistor. Consequently, the current flowing through the GAA transistor depends on the qubit's state. We calculated the current-voltage characteristics of the three-dimensional configurations of the qubit and GAA structures, using technology computer-aided design (TCAD) simulations. Moreover, we performed circuit simulations using the Simulation Program with Integrated Circuit Emphasis (SPICE) to investigate whether a readout circuit made from complementary metal--oxide semiconductor (CMOS) transistors can amplify the weak signals generated by the qubits. Our findings indicate that, by dynamically controlling the applied voltage within a properly designed circuit, the readout can be detected effectively based on a conventional sense amplifier.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper claims that TCAD simulations of a gate-all-around (GAA) transistor integrated with a two-physical-qubit logical spin qubit demonstrate state-dependent drain currents arising from spin-configuration-dependent charge distributions, and that SPICE simulations of a conventional CMOS sense-amplifier circuit can amplify the resulting weak signals to enable effective readout when the applied voltage is dynamically controlled.

Significance. If the simulated current differences prove large enough to exceed realistic noise and variation floors, the work would supply a useful device-circuit co-simulation framework for silicon spin-qubit readout, highlighting a potential route to scalable CMOS-compatible detection that avoids custom cryogenic amplifiers.

major comments (2)
  1. [TCAD results] TCAD results section: the I-V curves for different spin states are presented without reported values of ΔI, without mesh-convergence checks, and without any comparison of ΔI to expected thermal, 1/f, or amplifier noise at ~1 K; this quantitative gap directly undermines the central claim that readout is 'detected effectively' with a standard sense amplifier.
  2. [SPICE circuit simulations] SPICE circuit section: the sense-amplifier simulations use standard CMOS models without cryogenic corrections (threshold-voltage shift, mobility freeze-out, or increased low-temperature noise), so the amplification of the weak qubit-induced signals cannot yet be considered realistic for the operating regime of silicon spin qubits.
minor comments (2)
  1. [Abstract] Abstract: no numerical values are given for current differences, bias points, or simulation parameters, reducing the reader's ability to judge practical relevance.
  2. [Methods] Device geometry and doping profiles are listed as free parameters but are not tabulated or described with sufficient precision for independent reproduction of the 3D TCAD structures.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful and constructive review of our manuscript. The comments highlight important aspects of quantitative validation and cryogenic applicability that we have addressed in the revision.

read point-by-point responses
  1. Referee: [TCAD results] TCAD results section: the I-V curves for different spin states are presented without reported values of ΔI, without mesh-convergence checks, and without any comparison of ΔI to expected thermal, 1/f, or amplifier noise at ~1 K; this quantitative gap directly undermines the central claim that readout is 'detected effectively' with a standard sense amplifier.

    Authors: We agree that explicit reporting of ΔI, mesh convergence verification, and noise benchmarking are necessary to substantiate the readout claim. In the revised manuscript we now tabulate the extracted current differences ΔI between the relevant spin configurations. We have added a dedicated subsection documenting mesh-convergence tests (current variation < 1 % upon successive refinement) and have included order-of-magnitude estimates comparing ΔI to thermal (kT/C), 1/f, and typical CMOS sense-amplifier noise floors at ~1 K. These additions show that the simulated signal margins remain detectable under the stated conditions. revision: yes

  2. Referee: [SPICE circuit simulations] SPICE circuit section: the sense-amplifier simulations use standard CMOS models without cryogenic corrections (threshold-voltage shift, mobility freeze-out, or increased low-temperature noise), so the amplification of the weak qubit-induced signals cannot yet be considered realistic for the operating regime of silicon spin qubits.

    Authors: We acknowledge that the SPICE simulations rely on standard room-temperature CMOS compact models and therefore omit cryogenic corrections. In the revised text we have added an explicit limitations paragraph stating this approximation and have supplied literature-based estimates of threshold-voltage shift and mobility reduction at 1 K to indicate the expected direction and magnitude of change. While a full cryogenic device-model library would be preferable, the present circuit-level study is intended to illustrate the dynamic-voltage-control concept; the added discussion clarifies the scope and points to future modeling needs. revision: partial

Circularity Check

0 steps flagged

No circularity: readout claims rest on independent TCAD/SPICE simulations

full rationale

The paper derives its readout-effectiveness claim from numerical device simulations in commercial TCAD (computing 3D electrostatics and I-V curves for different spin configurations) followed by SPICE circuit simulations of a CMOS sense-amplifier stage. These steps use external, standard physics models and commercial solvers whose outputs are not defined in terms of the target result; the current delta is an emergent consequence of the modeled charge distributions rather than a fitted or self-referential quantity. No equations reduce by construction to the claimed prediction, no self-citations are load-bearing, and no ansatz or uniqueness theorem is smuggled in. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that spin configurations produce distinct electrostatic effects and on standard semiconductor device physics; no new entities are postulated and simulation parameters are not enumerated in the abstract.

free parameters (1)
  • device geometry and doping profiles
    TCAD simulations require specific 3D dimensions, doping concentrations, and material parameters that are not listed in the abstract.
axioms (1)
  • domain assumption Different spin configurations result in different charge distributions that influence the electrostatics of the GAA transistor
    Invoked in the abstract as the mechanism linking qubit state to transistor current.

pith-pipeline@v0.9.0 · 5457 in / 1208 out tokens · 30511 ms · 2026-05-17T00:08:21.054414+00:00 · methodology

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Works this paper leans on

56 extracted references · 56 canonical work pages · 1 internal anchor

  1. [1]

    N. D. Stuyck, A. Saraiva, W. Gilbert, J. C. Pardo, R. Li, C. C. Escott, K. De Greve, S. Voinigescu, D. J. Reilly, and A. S. Dzurak, ``CMOS compatibility of semiconductor spin qubits,'' arXiv:2409.03993

  2. [2]

    Anders et al

    J. Anders et al. , ``CMOS Integrated Circuits for the Quantum Information Sciences,'' IEEE Trans. Quantum Eng. , vol. 4, pp. 1-30, 2023

  3. [3]

    Yeap et al

    G. Yeap et al. , ``2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,'' 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4

  4. [4]

    S. -G. Jung, D. Jang, S. -J. Min, E. Park and H. -Y. Yu, ` `Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics,'' IEEE Access , vol. 10, pp. 41112-41118, 2022

  5. [5]

    Loubet et al

    N. Loubet et al. , ``Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,'' 2017 Symposium on VLSI Technology , Kyoto, Japan, 2017, pp. T230-T231,

  6. [6]

    Bae et al

    G. Bae et al. , ``3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications,'' IEEE International Electron Devices Meeting (IEDM) , San Francisco, CA, USA, 2018, pp. 28.7.1-28.7.4

  7. [7]

    Agrawal et al

    A. Agrawal et al. , ``Silicon RibbonFET CMOS at 6nm Gate Length,'' IEEE International Electron Devices Meeting (IEDM) , San Francisco, CA, USA, 2024, pp. 1-4

  8. [8]

    V. B. Sreenivasulu, A. K. Neelam, S. R. Kola, J. Singh and Y. Li, ``Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison,'' IEEE Access , vol. 11, pp. 90421-90429, 2023

  9. [9]

    Y. C. Chen, L. A. Yu, K. W. Cheng and E. R. Hsieh, ``Ultra-Scale ( 0.014 m ^2 ) High-Efficient 10A 6T Cfet-Sram Cells Combined Backside Power Deliver Networks and Backside Bit-Lines,'' International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) , Hsinchu, Taiwan, 2025, pp. 01-02

  10. [10]

    Pal et al

    A. Pal et al. , ``Novel Logic & SRAM Interconnect Design for Advanced Complementary FET (CFET) Based Technology Nodes, " IEEE International Electron Devices Meeting (IEDM) , San Francisco, CA, USA, 2024, pp. 1-4

  11. [11]

    Abdi et al

    D. Abdi et al. , ``Area-Efficient CFET Dual-port SRAM with Backside Interconnect," IEEE European Solid-State Electronics Research Conference (ESSERC) , Bruges, Belgium, 2024, pp. 21-24

  12. [12]

    M. Lee, Z. -Y. Huang, S. -F. Fan, Y. -C. Lu and V. P. -H. Hu, ``Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors,'' International Electron Devices Meeting (IEDM) , San Francisco, CA, USA, 2022, pp. 15.2.1-15.2.4

  13. [13]

    Yoneda, K

    J. Yoneda, K. Takeda, A. Noiri, T. Nakajima, S. Li, J. Kamioka, T. Kodera, and S. Tarucha, ``Quantum non-demolition readout of an electron spin in silicon,'' Nat. Communications , vol 11, 1144, Mar. 2020

  14. [14]

    D. M. Zajac, A. J. Sigillito, M. Russ, F. Borjans, J. M. Taylor, G. Burkard, and J. R. Petta, ``Resonantly driven CNOT gate for electron spins,'' Science , vol 359, pp. 439-442, Dec. 2017

  15. [15]

    Noiri, K

    A. Noiri, K. Takeda, T. Nakajima, T. Kobayashi, A. Sammak, G. Scappucci, and S, Tarucha, ``Fast universal quantum gate above the fault-tolerance threshold in silicon,'' Nature , vol. 601, pp.338–342, Jan. 2022

  16. [16]

    C. M. Compagnoni, G. M. Paolucci, C. Miccoli, A. S. Spinelli, A. L. Lacaita, A. Visconti, and A. Goda, ``First Detection of Single-Electron Charging of the Floating Gate of NAND Flash Memory Cells,'' IEEE Electron Device Lett. , vol. 36, pp. 132-134, Feb. 2015

  17. [17]

    Loss, and D.P

    D. Loss, and D.P. DiVincenzo, ``Quantum computation with quantum dots,'' Phys.Rev. A , vol 57, pp.120-126 Jan. 1998

  18. [18]

    Burkard, T

    G. Burkard, T. D. Ladd, A. Pan, J. M. Nichol, J. R. Petta, ``Semiconductor spin qubits,'' Rev. Mod. Phys. , vol 95, 025003, Jun. 2023

  19. [19]

    J. M. Taylor, H.-A. Engel, C. M. Marcus, and M. D. Lukin ``Fault-tolerant architecture for quantum computation using electrically controlled semiconductor spins,'' Nature Phys , vol. 1, pp. 177–183, Dec. 2005

  20. [20]

    J. M. Taylor, J. R. Petta, A. C. Johnson, A. Yacoby, C. M. Marcus, and M. D. Lukin, ``Relaxation, dephasing, and quantum control of electron spins in double quantum dots,'' Phys. Rev. B , vol 76, 035315, Jul. 2007

  21. [21]

    J. R. Petta, A. C. Johnson, J. M. Taylor, E. A. Laird, A. Yacoby, M. D. Lukin, C. M. Marcus, M. P. Hanson, and A. C. Gossard, Science , vol 309, pp. 2180-2184, Sep. 2005

  22. [22]

    B. M. Maune, M. G. Borselli, B. Huang, T. D. Ladd, P. W. Deelman, K. S. Holabird, A. A. Kiselev, I. Alvarado-Rodriguez, R. S. Ross, A. E. Schmitz, M. Sokolich, C. A. Watson, M. F. Gyure, and A. T. Hunte, ``Coherent singlet-triplet oscillations in a silicon-based double quantum dot,'' Nature , vol. 481, pp. 344–347, Jan. 2012

  23. [23]

    Klinovaja, D

    J. Klinovaja, D. Stepanenko, B. I. Halperin, and D. Loss, ``Exchange-based CNOT gates for singlet-triplet qubits with spin-orbit interaction,'' Phys. Rev. B , vol 86, 085423, Aug. 2012

  24. [24]

    F. A. Calderon-Vargas and J. P. Kestner, ``Directly accessible entangling gates for capacitively coupled singlet-triplet qubits,'' Phys. Rev. B , vol 91, 035301, Jan. 2015

  25. [25]

    Takeda, A

    K. Takeda, A. Noiri, J. Yoneda, T. Nakajima, and S. Tarucha, ``Resonantly Driven Singlet-Triplet Spin Qubit in Silicon,'' Phys. Rev. Lett. , vol 124, 117701, Mar. 2020

  26. [26]

    Zhang, E

    X. Zhang, E. Morozova, M. Rimbach-Russ, D. Jirovec, T.-K. Hsiao, P. C. Fariña, C.-A. Wang, S. D. Oosterhout, A. Sammak, G. Scappucci, M. Veldhorst, and L. M. K. Vandersypen, ``Universal control of four singlet–triplet qubits,'' Nat. Nanotechnol. , vol 20, pp.209-215, Oct. 2025

  27. [27]

    K. Ono, D. G. Austing, Y. Tokura, and S. Tarucha, ``Current Rectification by Pauli Exclusion in a Weakly Coupled Double Quantum Dot System,'' Science , vol 297, pp. 1313-1317, Jul. 2002

  28. [28]

    Tanamoto and K

    T. Tanamoto and K. Ono, ``Readout using resonant tunneling in silicon spin qubits,'' J. Appl. Phys. , vol 134, 214402, Dec. 2023

  29. [29]

    Tanamoto and K

    T. Tanamoto and K. Ono, ``Effects of valley splitting on resonant-tunneling readout of spin qubits,'' J. Appl. Phys. , vol 137, 164403, Apr. 2025

  30. [30]

    J. R. Johansson, P. D. Nation, and F. Nori, ‘‘QuTiP: An open-source Python framework for the dynamics of open quantum systems,’’ Comput. Phys. Commun. , vol. 183, pp. 1760–1772, Aug. 2012

  31. [31]

    Q. Ding, A. V. Kuhlmann, A. Fuhrer, and A. Schenk ``A generalizable TCAD framework for silicon FinFET spin qubit devices with electrical control,'' Solid-State Electronics , vol 200, 108550, Feb. 2023

  32. [32]

    Birner, T

    S. Birner, T. Zibold, T. Andlauer, T. Kubis, M. Sabathil, A. Trellakis, and P. Vogl, ‘‘Nextnano: General purpose 3-D simulations,’’ IEEE Trans. Electron Devices , vol. 54, no. 9, pp. 2137–2142, Sep. 2007

  33. [33]

    Beaudoin, P

    F. Beaudoin, P. Philippopoulos, C. Zhou, I. Kriekouki, M. Pioro-Ladrière H. Guo, and P. Galy, ``Robust technology computer-aided design of gated quantum dots at cryogenic temperature,'' Appl. Phys. Lett. , vol. 120, 264001, Jun. 2022

  34. [34]

    M. M. E. K. Shehata, G. Simion, R. Li , F. A. Mohiyaddin, D. Wan, M. Mongillo, B. Govoreanu , I. Radu, K. D. Greve, and P. V. Dorpe, ``Modeling semiconductor spin qubits and their charge noise environment for quantum gate fidelity estimation,' Phys. Rev. B , vol. 108, 045305, Jul. 2023

  35. [35]

    van Rijs, I

    S. van Rijs, I. Ercan, A. Vladimirescu and F. Sebastiano, ``Single-Electron-Transistor Compact Model for Spin-Qubit Readout,'' 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) , Funchal, Portugal, 2023, pp. 1-4

  36. [36]

    B. Gys, F. A. Mohiyaddin, R. Acharya, R. Li, K. De Greve, G. Gielen, B. Govoreanu, I. P. Radu, and F. Catthoor, ``Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry,'' European Solid-State Device Research Conference (ESSDERC) , Grenoble, France, 2021, pp. 63-66

  37. [37]

    Tanamoto and K

    T. Tanamoto and K. Ono, ``Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits,'' Appl. Phys. Lett. , vol. 119, 174002, Oct. 2021

  38. [38]

    Costa, M

    D. Costa, M. Simoni, G. Piccinini and M. Graziano, ``Advances in Modeling of Noisy Quantum Computers: Spin Qubits in Semiconductor Quantum Dots,'' IEEE Access , vol. 11, pp. 98875-98913, 2023

  39. [39]

    F. A. Mohiyaddin, G. Simion, N. I. Dumoulin Stuyck, R. Li, A. Elsayed, M. Shehata, S. Kubicek, C. Godfrin, B. T. Chan, J. Jussot, F. Ciubotaru, S. Brebels, F. M. Bufler, G. Eneman, P. Weckx, P. Matagne, A. Spessot, B. Govoreanu, and I. P. Radu, ``TCAD-Assisted MultiPhysics Modeling & Simulation for Accelerating Silicon Quantum Dot Qubit Design,'' Internat...

  40. [40]

    Tanamoto, ``3D Stacked Spin Qubit by TCAD Simulations,'' International 3D Systems Integration Conference (3DIC) , 1-4, 2024

    T. Tanamoto, ``3D Stacked Spin Qubit by TCAD Simulations,'' International 3D Systems Integration Conference (3DIC) , 1-4, 2024

  41. [41]

    Tanamoto and K

    T. Tanamoto and K. Ono, ``Compact spin qubits using the common gate structure of fin field-effect transistors,'' AIP Advances , vol. 11, 045004, Apr. 2021

  42. [42]

    Ruderman and C

    A. Ruderman and C. Kittel, ``Indirect Exchange Coupling of Nuclear Magnetic Moments by Conduction Electrons,'' Phys. Rev. , vol. 96, pp.99-102 Oct. 1954

  43. [43]

    Kasuya, ``A Theory of Metallic Ferro- and Antiferromagnetism on Zener's Model,'' Prog

    T. Kasuya, ``A Theory of Metallic Ferro- and Antiferromagnetism on Zener's Model,'' Prog. Theor. Phys. , vol. 16, pp.45-57, Feb. 1956

  44. [44]

    Yosida, ``Magnetic Properties of Cu-Mn Alloys,'' Phys

    K. Yosida, ``Magnetic Properties of Cu-Mn Alloys,'' Phys. Rev. , vol. 106, pp.893-898, Feb. 1957

  45. [45]

    Fowler, M

    A.G. Fowler, M. Mariantoni, J.M. Martinis, and A.N. Cleland, ``Surface codes: Towards practical large-scale quantum computation,'' Phys. Rev. A , vol.86 , 032324, Sep. 2012

  46. [46]

    McPherson, V

    J. McPherson, V. Reddy, K. Banerjee and Huy Le, ``Comparison of E and 1/E TDDB models for SiO/sub 2/ under long-term/low-field test conditions,'' International Electron Devices Meeting (IEDM) , Technical Digest (Cat. No.98CH36217), San Francisco, CA, USA, 1998

  47. [47]

    X. Wang, A. R. Brown, Binjie Cheng and A. Asenov, ``Statistical variability and reliability in nanoscale FinFETs,'' International Electron Devices Meeting (IEDM) , Washington, DC, USA, 2011, pp. 5.4.1-5.4.4

  48. [48]

    Zhang, C

    Q. Zhang, C. Wang, H. Wang, C. Schnabel, D.-G. Park, S. K. Springer, and E. Leobandung, ``Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch,'' IEEE Trans. on Electron Devices , vol. 61, no. 2, pp. 643-646, Feb. 2014

  49. [49]

    D. E. Holcomb, W. P. Burleson, and K. Fu, ``Power-up SRAM state as an identifying fingerprint and source of true random numbers,'' IEEE Trans. Comput. , vol. 58, no. 9, pp. 1198–1210, Sep. 2009

  50. [50]

    Srinivasa, H

    V. Srinivasa, H. Xu, and J.M. Taylor, ``Tunable Spin-Qubit Coupling Mediated by a Multielectron Quantum Dot,'' Phys. Rev. Lett. , vol. 114, 226803, Jun. 2015

  51. [51]

    S. Meh, H. Bluhm, and D. P. DiVincenzo, ``Two-qubit couplings of singlet-triplet qubits mediated by one quantum state,'' Phys. Rev. B , 90, 045404, Jul. 2014

  52. [52]

    Sasaki, S

    S. Sasaki, S. Kang, K. Kitagawa, M. Yamaguchi, S. Miyashita, T. Maruyama, H. Tamura, T. Akazaki, Y. Hirayama, and H. Takayanagi, ``Nonlocal control of the Kondo effect in a double quantum dot–quantum wire coupled system,'' Phys. Rev. B , vol. 73, 161303(R), Apr. 2006

  53. [53]

    Craig, J.M

    N.J. Craig, J.M. Taylor, E.A. Lester, C.M. Marcus, M.P. Hanson, and A.C. Gossard, ``Tunable Nonlocal Spin Control in a Coupled-Quantum Dot System,'' Science , vol. 304, pp.565-567, Apr. 2004

  54. [54]

    Croot, S.J

    X.G. Croot, S.J. Pauka, J.D. Watson, G.C. Gardner, S. Fallahi, M.J. Manfra, and D.J. Reilly, ``Device architecture for coupling spin qubits via an intermediate quantum state,'' Phys. Rev. Applied. , vol. 10, 044058, Oct. 2018

  55. [55]

    Rikitake and H

    Y. Rikitake and H. Imamura, ``Decoherence of localized spins interacting via RKKY interaction,'' Phys. Rev. B , vol. 72, 033308, Jul. 2005

  56. [56]

    Coqblin and J

    B. Coqblin and J. R. Schrieffer, ``Exchange Interaction in Alloys with Cerium Impurities,'' Phys. Rev. , vol 185, pp.847-853, Sep. 1969