Pith. sign in

REVIEW 2 major objections 1 minor 164 references

Energy and Scaling Limits of Phase-Change Memory

T0 review · 2 major / 1 minor · reviewed 2026-06-29 · grok-4.3

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Phase change memory can theoretically reach single attojoules per cubic nanometer but electrical and thermal parasitics at contacts block it.

desk verdict A review summarizing PCM energy scaling work with no new results or analysis. read the letter →

arxiv 2605.28336 v1 pith:CS63JV47 submitted 2026-05-27 cond-mat.mtrl-sci

Rivka-Galya Nir-Harwood , Asir I. Khan , Emanuel Ber , Efrat Ordan , Keren Stern , Kye L. Okabe , Nicolás Wainstein , Eilam Yalon
show 1 more author
Eric Pop
This is my paper · ORCID
classification cond-mat.mtrl-sci
keywords phasechangememoryenergyefficiencyscalinglimitsheatconfinementparasiticsfemtojoulesattojoulesinterfaces
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reviews how phase change memory has already reached energy use of only tens of femtojoules per bit through device innovations. It focuses on two main strategies for further gains: shrinking the active phase change material to sub-10 nanometer sizes and improving heat confinement to reduce losses to the surroundings. These changes could push energy consumption toward single attojoules per cubic nanometer of material. A sympathetic reader would care because such efficiency would support low-power data storage and neuromorphic hardware. The review stresses that parasitics at electrical and thermal contacts and interfaces remain the chief practical barrier.

What carries the argument

Sub-10 nm scaling of the active phase change material region together with heat confinement to cut thermal dissipation into the environment during thermally induced switching.

What would settle it

Measurement of switching energy in a fabricated PCM device with sub-10 nm active volume and reduced contact resistance that shows whether consumption reaches single attojoules per cubic nanometer.

Watch

Extended reading notes

Core claim

The paper claims that PCM energy efficiency improves by minimizing the active material volume to sub-10 nm dimensions and by enhancing heat confinement during the thermally driven amorphous-to-crystalline transition, potentially reaching single attojoules per cubic nanometer, yet electrical and thermal parasitics at contacts and interfaces prevent full realization of these theoretical limits in fabricated devices.

Load-bearing premise

Thermal induction of the phase transition is the main energy cost and the two strategies of sub-10 nm scaling plus heat confinement will suffice to approach the theoretical limit despite the noted parasitics at contacts and interfaces.

Editorial extensions

If this is right

  • Energy per bit could drop below current tens of femtojoules levels if interface losses are reduced.
  • PCM devices could become viable for energy-constrained neuromorphic hardware applications.
  • Further miniaturization below 10 nm will be required to approach the stated fundamental energy bounds.
  • Contact and interface engineering must advance in parallel with material scaling.
  • The gap between theoretical and practical limits highlights the need to address parasitic effects directly.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Electrode materials with lower thermal and electrical resistance could narrow the gap to the theoretical attojoule limit.
  • The same scaling and confinement logic might extend to other thermally switched memory or logic devices.
  • Reaching these energy levels would allow denser memory arrays without proportional increases in total power.
  • Advanced fabrication that isolates the active region from surrounding contacts would serve as a direct test.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 1 minor

Summary. This manuscript is a review of phase-change memory (PCM) technology for energy-efficient data storage and neuromorphic hardware. It summarizes prior work showing energy consumption reduced to tens of femtojoules per bit via two strategies: scaling the active phase-change material to sub-10 nm dimensions and improving heat confinement to minimize thermal dissipation. The review states that theoretical limits could reach single attojoules per cubic nanometer of material but emphasizes that practical realization is significantly constrained by electrical and thermal parasitics at contacts and interfaces.

Significance. If the review accurately and comprehensively covers the cited literature on PCM scaling and thermal management, it could serve as a useful reference for identifying pathways toward lower-energy memory devices. The explicit discussion of parasitics as a remaining barrier provides a balanced perspective on the gap between theoretical limits and achievable performance.

major comments (2)
  1. [Abstract] Abstract: The assertion that 'the theoretical limits could reach single attojoules per cubic nanometer of memory material' is presented without a derivation, quantitative model, or specific citation to a calculation establishing this value. As a review, the manuscript should explicitly reference or reproduce the basis for this limit to allow readers to assess its validity against the acknowledged parasitics.
  2. [Abstract] Abstract and full text summary: The manuscript identifies sub-10 nm scaling and heat confinement as primary strategies but provides no quantitative analysis or cited data showing how these approaches reduce the impact of contact/interface parasitics relative to the stated theoretical limit. This leaves the central claim about approaching fundamental limits without load-bearing evidence in the review itself.
minor comments (1)
  1. The abstract refers to 'key innovations' and 'prior innovations' but does not list specific references or device examples in the provided text; the full manuscript should include a table or section summarizing the cited energy values, dimensions, and references for clarity.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments and recommendation for minor revision. We address each major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The assertion that 'the theoretical limits could reach single attojoules per cubic nanometer of memory material' is presented without a derivation, quantitative model, or specific citation to a calculation establishing this value. As a review, the manuscript should explicitly reference or reproduce the basis for this limit to allow readers to assess its validity against the acknowledged parasitics.

    Authors: We agree that the basis for the stated theoretical limit should be made explicit for readers. In the revised manuscript we will add a specific citation to the relevant literature calculation establishing the attojoule-per-cubic-nanometer scale together with a concise explanation of the underlying energy considerations. revision: yes

  2. Referee: [Abstract] Abstract and full text summary: The manuscript identifies sub-10 nm scaling and heat confinement as primary strategies but provides no quantitative analysis or cited data showing how these approaches reduce the impact of contact/interface parasitics relative to the stated theoretical limit. This leaves the central claim about approaching fundamental limits without load-bearing evidence in the review itself.

    Authors: The review already summarizes experimental demonstrations from the cited literature that achieve tens of femtojoules per bit through these strategies. To strengthen the presentation we will expand the relevant sections with additional quantitative examples and citations that explicitly illustrate how scaling and confinement reduce the relative contribution of parasitics, thereby providing clearer support for progress toward the theoretical limit. revision: yes

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity; paper is a literature review with no derivations

full rationale

The manuscript is a review summarizing prior work on PCM energy efficiency via sub-10 nm scaling and heat confinement. It states theoretical limits could reach single attojoules per nm³ but notes practical constraints from parasitics at contacts and interfaces. No original equations, models, fitted parameters, or derivations are presented that could reduce to inputs by construction. All content is supported by external citations without self-citation load-bearing on central claims or self-definitional constructs. The derivation chain is empty by design.

Assumptions & free parameters 0 free parameters · 1 assumptions · 0 invented entities

As a review paper, the summary rests on the accuracy of previously published work on PCM devices rather than new free parameters, axioms, or entities introduced here.

assumptions (1)
  • domain assumption PCM switching is induced thermally
    Stated directly in the abstract as the basis for focusing on heat confinement and material volume.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Energy and Scaling Limits of Phase-Change Memory." pith.science (2026). https://pith.science/paper/CS63JV47

@misc{pith2026260528336,
  author       = {Pith},
  title        = {Pith review of: Energy and Scaling Limits of Phase-Change Memory},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CS63JV47}},
  note         = {Machine review of arXiv:2605.28336}
}
read the original abstract

Phase change memory (PCM) relies on a reversible transition between amorphous and crystalline states of a material, and stands as a promising candidate for next-generation, energy-efficient data storage and neuromorphic hardware. Here, we review key innovations that have driven PCM technology to achieve energy consumption down to only tens of femtojoules per bit, and could further advance it closer to its fundamental limits. Because PCM switching is induced thermally, we highlight improvements in energy-efficiency through two primary strategies: by minimizing the active phase change material region to sub-10 nm dimensions, and by enhancing heat confinement within PCM devices to reduce thermal dissipation into the surrounding environment. While the theoretical limits could reach single attojoules per cubic nanometer of memory material, realizing these limits in practice is significantly constrained by electrical and thermal parasitics, particularly at contacts and interfaces.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

164 extracted references · 117 canonical work pages

  1. [1]

    Energy-Efficient Abundant-Data Computing: The N3XT 1,000×,

    M. M. Sabry Aly et al., “Energy-Efficient Abundant-Data Computing: The N3XT 1,000×,” IEEE Computer, vol. 48, no. 24, 2015

    2015

  2. [2]

    Energy Crisis, Global Warming & IT Industry: Can the IT Professionals make it better Some Day? A Review:,

    M. Zakarya, I. U. Rahman, and A. A. Khan, “Energy Crisis, Global Warming & IT Industry: Can the IT Professionals make it better Some Day? A Review:,” in International Conference on Emerging Technologies, IEEE, 2012

    2012

  3. [3]

    Toward energy-efficient computing,

    D. J. Brown and C. Reams, “Toward energy-efficient computing,” Communications of the ACM, vol. 53, no. 3, pp. 50–58, Mar. 2010, doi: 10.1145/1666420.1666438

    work page doi:10.1145/1666420.1666438 2010

  4. [4]

    Recalibrating global data center energy-use estimates,

    E. Masanet, A. Shehabi, N. Lei, S. Smith, and J. Koomey, “Recalibrating global data center energy-use estimates,” Science, vol. 367, no. 6481, Mar. 2020, doi: 10.1007/s12053-019-09809-8

    work page doi:10.1007/s12053-019-09809-8 2020

  5. [5]

    Prediction Studies of Electricity Use of Global Computing in 2030,

    A. S. G. Andrae, “Prediction Studies of Electricity Use of Global Computing in 2030,” International Journal of Science and Engineering Investigations, vol. 8, 2019, [Online]. Available: www.IJSEI.com

  6. [6]

    Cloud computing: Survey on energy efficiency,

    T. Mastelic, A. Oleksiak, H. Claussen, I. Brandic, J. M. Pierson, and A. V. Vasilakos, “Cloud computing: Survey on energy efficiency,” ACM Computing Surveys, vol. 47, no. 2, Jan. 2015, doi: 10.1145/2656204

    work page doi:10.1145/2656204 2015

  7. [7]

    Phase change memory,

    H. S. P. Wong et al., “Phase change memory,” in Proceedings of the IEEE, 2010, pp. 2201–2227. doi: 10.1109/JPROC.2010.2070050

    work page doi:10.1109/jproc.2010.2070050 2010

  8. [8]

    Metal-oxide RRAM,

    H. S. P. Wong et al., “Metal-oxide RRAM,” in Proceedings of the IEEE, Institute of Electrical and Electronics Engineers Inc., 2012, pp. 1951–1970. doi: 10.1109/JPROC.2012.2190369

    work page doi:10.1109/jproc.2012.2190369 2012

Show all 164 references
  1. [9]

    Conductive Bridge Random Access Memory (CBRAM): Challenges and Opportunities for Memory and Neuromorphic Computing Applications,

    H. Abbas, J. Li, and D. Ang, “Conductive Bridge Random Access Memory (CBRAM): Challenges and Opportunities for Memory and Neuromorphic Computing Applications,” Micromachines, vol. 13, no. 5, p. 725, Apr. 2022, doi: 10.3390/mi13050725

    2022 doi

  2. [10]

    Erratum: Basic principles of STT-MRAM cell operation in memory arrays (Journal of Physics D: Applied Physics (2013) 46 (074001)),

    A. V. Khvalkovskiy et al., “Erratum: Basic principles of STT-MRAM cell operation in memory arrays (Journal of Physics D: Applied Physics (2013) 46 (074001)),” Journal of Physics D: Applied Physics, vol. 46, no. 13, Apr. 2013, doi: 10.1088/0022- 3727/46/13/139601

    2013 doi

  3. [11]

    Stateful Logic Using Phase Change Memory,

    B. Hoffer, N. Wainstein, C. M. Neumann, E. Pop, E. Yalon, and S. Kvatinsky, “Stateful Logic Using Phase Change Memory,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 2, pp. 77–83, Dec. 2022, doi: 10.1109/JXCDC.2022.3219731

    2022 doi

  4. [12]

    Phase change materials and phase change memory,

    S. Raoux, F. Xiong, M. Wuttig, and E. Pop, “Phase change materials and phase change memory,” MRS Bulletin, vol. 39, no. 8, pp. 703–710, Aug. 2014, doi: 10.1557/mrs.2014.139

    2014 doi

  5. [13]

    Phase change memory materials and their applications,

    S. A. Kozyukhin, P. I. Lazarenko, A. I. Popov, and I. L. Eremenko, “Phase change memory materials and their applications,” Russian Chemical Reviews, vol. 91, no. 9, pp. 1–37, 2022, doi: 10.1070/rcr5033

    2022 doi

  6. [14]

    Reversible Electrical Switching Phenomena in Disordered Structures,

    S. R. Ovshinsky, “Reversible Electrical Switching Phenomena in Disordered Structures,” Physical Review Letters, vol. 21, 1968

    1968

  7. [15]

    Origin, secret, and application of the ideal phase‐change material GeSbTe,

    N. Yamada, “Origin, secret, and application of the ideal phase‐change material GeSbTe,” Physica Status Solidi (b), vol. 249, no. 10, pp. 1837–1842, Oct. 2012, doi: 10.1002/pssb.201200618. 30

    2012 doi

  8. [16]

    The race of phase change memories to nanoscale storage and applications,

    A. L. Lacaita and A. Redaelli, “The race of phase change memories to nanoscale storage and applications,” Microelectronic Engineering, vol. 109, pp. 351–356, 2013, doi: 10.1016/j.mee.2013.02.105

    2013 doi

  9. [17]

    Phase-Change Memory - Towards a Storage-Class Memory,

    S. W. Fong, C. M. Neumann, and H. S. P. Wong, “Phase-Change Memory - Towards a Storage-Class Memory,” IEEE Transactions on Electron Devices, vol. 64, no. 11, pp. 4374–4385, Nov. 2017, doi: 10.1109/TED.2017.2746342

    2017 doi

  10. [18]

    Direct observation of amorphous to crystalline phase transitions in nanoparticle arrays of phase change materials,

    S. Raoux et al., “Direct observation of amorphous to crystalline phase transitions in nanoparticle arrays of phase change materials,” Journal of Applied Physics, vol. 102, no. 9, 2007, doi: 10.1063/1.2801000

    2007 doi

  11. [19]

    Nitrogen-implanted Ge2Sb2Te5 film used as multilevel storage media for phase change random access memory,

    B. Liu, T. Zhang, J. Xia, Z. Song, S. Feng, and B. Chen, “Nitrogen-implanted Ge2Sb2Te5 film used as multilevel storage media for phase change random access memory,” Semiconductor Science and Technology, vol. 19, no. 6, Jun. 2004, doi: 10.1088/0268- 1242/19/6/L01

    2004 doi

  12. [20]

    Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory,

    T. Nirschl et al., “Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory,” in IEEE International Electron Devices Meeting (IEDM), 2007

    2007

  13. [21]

    Synaptic electronics: Materials, devices and applications,

    D. Kuzum, S. Yu, and H. S. Philip Wong, “Synaptic electronics: Materials, devices and applications,” Nanotechnology, vol. 24, no. 38, Sep. 2013, doi: 10.1088/0957- 4484/24/38/382001

    2013 doi

  14. [22]

    Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing,

    D. Kuzum, R. G. D. Jeyasingh, B. Lee, and H. S. P. Wong, “Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing,” Nano Letters, vol. 12, no. 5, pp. 2179–2186, May 2012, doi: 10.1021/nl201040y

    2012 doi

  15. [23]

    Nanoscale electronic synapses using phase change devices,

    B. L. Jackson et al., “Nanoscale electronic synapses using phase change devices,” ACM Journal on Emerging Technologies in Computing Systems, vol. 9, no. 2, 2013, doi: 10.1145/2463585.2463588

    2013 doi

  16. [24]

    Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element,

    G. W. Burr et al., “Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element,” IEEE Transactions on Electron Devices (TED), vol. 62, no. 11, pp. 3498–3507, Jul. 2015, doi: 10.1109/TED...

    2015 doi

  17. [25]

    Experimental demonstration of array-level learning with phase change synaptic devices,

    S. B. Eryilmaz et al., “Experimental demonstration of array-level learning with phase change synaptic devices,” in 2013 IEEE International Electron Devices Meeting, Washington, DC, USA: IEEE, Dec. 2013, p. 25.5.1-25.5.4. doi: 10.1109/IEDM.2013.6724691

    2013 doi

  18. [26]

    Neuromorphic architectures with electronic synapses,

    S. B. Eryilmaz, S. Joshi, E. Neftci, W. Wan, G. Cauwenberghs, and H.-S. P. Wong, “Neuromorphic architectures with electronic synapses,” in 2016 17th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA: IEEE, Mar. 2016, pp. 118–123. doi: 10.1109/I...

    2016 doi

  19. [27]

    Neuromorphic computing using non-volatile memory,

    G. W. Burr et al., “Neuromorphic computing using non-volatile memory,” Advances in Physics: X, vol. 2, no. 1, pp. 89–124, 2017, doi: 10.1080/23746149.2016.1259585

    2017 doi

  20. [28]

    Stochastic phase- change neurons,

    T. Tuma, A. Pantazi, M. Le Gallo, A. Sebastian, and E. Eleftheriou, “Stochastic phase- change neurons,” Nature Nanotechnology, vol. 11, no. 8, pp. 693–699, Aug. 2016, doi: 10.1038/nnano.2016.70

    2016 doi

  21. [29]

    Ultra-low switching energy and scaling in electric-field-controlled nanoscale magnetic tunnel junctions with high resistance-area product,

    C. Grezes et al., “Ultra-low switching energy and scaling in electric-field-controlled nanoscale magnetic tunnel junctions with high resistance-area product,” Applied Physics Letters, vol. 108, no. 1, p. 012403, Jan. 2016, doi: 10.1063/1.4939446. 31

    2016 doi

  22. [30]

    Enabling universal memory by overcoming the contradictory speed and stability nature of phase-change materials,

    W. Wang et al., “Enabling universal memory by overcoming the contradictory speed and stability nature of phase-change materials,” Scientific Reports, vol. 2, 2012, doi: 10.1038/srep00360

    2012 doi

  23. [31]

    Analysis of temperature in phase change memory scaling,

    S. B. Kim and H. S. P. Wong, “Analysis of temperature in phase change memory scaling,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 697–699, Aug. 2007, doi: 10.1109/LED.2007.901347

    2007 doi

  24. [32]

    Scaling analysis of nanowire phase-change memory,

    J. Liu, B. Yu, and M. P. Anantram, “Scaling analysis of nanowire phase-change memory,” IEEE Electron Device Letters, vol. 32, no. 10, pp. 1340–1342, Oct. 2011, doi: 10.1109/LED.2011.2162390

    2011 doi

  25. [33]

    Scaling Analysis of Phase-Change Memory Technology,

    A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, “Scaling Analysis of Phase-Change Memory Technology,” in Tech. Dig. -Int. Electron Devices Meetings, 2003

    2003

  26. [34]

    Threshold field of phase change memory materials measured using phase change bridge devices,

    D. Krebs, S. Raoux, C. T. Rettner, G. W. Burr, M. Salinga, and M. Wuttig, “Threshold field of phase change memory materials measured using phase change bridge devices,” Applied Physics Letters, vol. 95, no. 8, 2009, doi: 10.1063/1.3210792

    2009 doi

  27. [35]

    Minimum voltage for threshold switching in nanoscale Phase-change memory,

    D. D. Yu, S. Brittman, J. S. Lee, A. L. Falk, and P. Hongkun, “Minimum voltage for threshold switching in nanoscale Phase-change memory,” Nano Letters, vol. 8, no. 10, pp. 3429–3433, Oct. 2008, doi: 10.1021/nl802261s

    2008 doi

  28. [36]

    Nanoscale phase-change materials and devices,

    Q. Zheng, Y. Wang, and J. Zhu, “Nanoscale phase-change materials and devices,” Journal of Physics D: Applied Physics, vol. 50, no. 24, May 2017, doi: 10.1088/1361- 6463/aa70b0

    2017 doi

  29. [37]

    Phase change memory technology,

    G. W. Burr et al., “Phase change memory technology,” Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 28, no. 2, pp. 223–262, Mar. 2010, doi: 10.1116/1.3301579

    2010 doi

  30. [38]

    Stanford Memory Trends,

    H.-S. P. Wong , S. Qin, Y. C. Shen, M. Shi, J. Sohn, M. Tung, W. Wan, X. Wu, Y. Wu, S. Yu, Z. Yu, X. Zheng et al., “Stanford Memory Trends,” https://nano.stanford.edu/stanford-memory-trends

  31. [39]

    Carbon nanomaterials for non-volatile memories,

    E. C. Ahn, H.-S. P. Wong, and E. Pop, “Carbon nanomaterials for non-volatile memories,” Nat Rev Mater, vol. 3, no. 3, p. 18009, Mar. 2018, doi: 10.1038/natrevmats.2018.9

    2018 doi

  32. [40]

    Low-Power Switching of Phase-Change Materials with Carbon Nanotube Electrodes,

    F. Xiong, A. D. Liao, D. Estrada, and E. Pop, “Low-Power Switching of Phase-Change Materials with Carbon Nanotube Electrodes,” Science, vol. 332, no. 6029, pp. 568–570, Apr. 2011, doi: 10.1126/science.1201938

    2011 doi

  33. [42]

    Waser, Nanoelectronics and Information Technology: Advanced electronic Materials and Novel Devices

    R. Waser, Nanoelectronics and Information Technology: Advanced electronic Materials and Novel Devices. Wiley, 2012

    2012

  34. [44]

    High-performance flexible nanoscale transistors based on transition metal dichalcogenides,

    A. Daus et al., “High-performance flexible nanoscale transistors based on transition metal dichalcogenides,” Nat Electron, vol. 4, no. 7, pp. 495–501, Jun. 2021, doi: 10.1038/s41928-021-00598-6

    2021 doi

  35. [45]

    Nanoscale phase change memory with graphene ribbon electrodes,

    A. Behnam et al., “Nanoscale phase change memory with graphene ribbon electrodes,” Applied Physics Letters, vol. 107, no. 12, Sep. 2015, doi: 10.1063/1.4931491. 32

    2015 doi

  36. [46]

    Towards Ultimate Scaling Limits of Phase-Change Memory,

    F. Xiong et al., “Towards Ultimate Scaling Limits of Phase-Change Memory,” in IEEE International Electron Devices Meeting (IEDM), 2016, p. 4.1.1-4.1.4. Accessed: Mar. 17,

    2016

  37. [47]

    Available: 10.1109/IEDM.2016.7838342

    [Online]. Available: 10.1109/IEDM.2016.7838342

    2016 doi

  38. [50]

    Structure for phase change memory and the method of forming same,

    M. H. Lee and Y. C. Chen, “Structure for phase change memory and the method of forming same,” 2005

    2005

  39. [51]

    Non-Volatile Memory Cell Comprising a Dielectric Layer and a Phase Change Material in Series,

    R. E. Scheuerlein and S. B. Herner, “Non-Volatile Memory Cell Comprising a Dielectric Layer and a Phase Change Material in Series,” Jul. 21, 2005

    2005

  40. [52]

    Energy Dissipation in Monolayer MoS2 Electronics,

    E. Yalon et al., “Energy Dissipation in Monolayer MoS2 Electronics,” Nano Lett., vol. 17, no. 6, pp. 3429–3433, Jun. 2017, doi: 10.1021/acs.nanolett.7b00252

    2017 doi

  41. [53]

    Temperature-Dependent Thermal Boundary Conductance of Monolayer MoS2 by Raman Thermometry,

    E. Yalon et al., “Temperature-Dependent Thermal Boundary Conductance of Monolayer MoS2 by Raman Thermometry,” ACS Appl. Mater. Interfaces, vol. 9, no. 49, pp. 43013– 43020, Dec. 2017, doi: 10.1021/acsami.7b11641

    2017 doi

  42. [54]

    Thermal properties of graphene: Fundamentals and applications,

    E. Pop, V. Varshney, and A. K. Roy, “Thermal properties of graphene: Fundamentals and applications,” MRS Bull., vol. 37, no. 12, pp. 1273–1281, Dec. 2012, doi: 10.1557/mrs.2012.203

    2012 doi

  43. [55]

    Scaling properties of phase change materials,

    S. Raoux et al., “Scaling properties of phase change materials,” in 2007 Non-Volatile Memory Technology Symposium, Albuquerque, NM: IEEE, Nov. 2007, pp. 30–35. doi: 10.1109/NVMT.2007.4389940

    2007 doi

  44. [56]

    Crystallization properties of ultrathin phase change films,

    S. Raoux, J. L. Jordan-Sweet, and A. J. Kellock, “Crystallization properties of ultrathin phase change films,” Journal of Applied Physics, vol. 103, no. 11, 2008, doi: 10.1063/1.2938076

    2008 doi

  45. [57]

    Synthesis and size-dependent crystallization of colloidal germanium telluride nanoparticles,

    M. A. Caldwell, S. Raoux, R. Y. Wang, H. S. Philip Wong, and D. J. Milliron, “Synthesis and size-dependent crystallization of colloidal germanium telluride nanoparticles,” Journal of Materials Chemistry, vol. 20, no. 7, pp. 1285–1291, 2010, doi: 10.1039/b917024c

    2010 doi

  46. [58]

    Can conventional phase-change memory devices be scaled down to single-nanometre dimensions?,

    H. Hayat, K. Kohary, and C. D. Wright, “Can conventional phase-change memory devices be scaled down to single-nanometre dimensions?,” Nanotechnology, vol. 28, no. 3, p. 035202, Jan. 2017, doi: 10.1088/1361-6528/28/3/035202

    2017 doi

  47. [59]

    Exploiting nanoscale effects in phase change memories,

    B. Kersting and M. Salinga, “Exploiting nanoscale effects in phase change memories,” Faraday Discuss., vol. 213, pp. 357–370, 2019, doi: 10.1039/C8FD00119G

    2019 doi

  48. [60]

    Low-bias electron transport properties of germanium telluride ultrathin films,

    J. Liu and M. P. Anantram, “Low-bias electron transport properties of germanium telluride ultrathin films,” Journal of Applied Physics, vol. 113, no. 6, Feb. 2013, doi: 10.1063/1.4790801

    2013 doi

  49. [65]

    Kapitza Resistance,

    G. L. Pollack, “Kapitza Resistance,” Rev. Mod. Phys., vol. 41, no. 1, pp. 48–81, Jan. 1969, doi: 10.1103/RevModPhys.41.48

    1969 doi

  50. [66]

    Thermal boundary resistance,

    E. T. Swartz and R. O. Pohl, “Thermal boundary resistance,” Rev. Mod. Phys., vol. 61, no. 3, pp. 605–668, Jul. 1989, doi: 10.1103/RevModPhys.61.605

    1989 doi

  51. [67]

    Optimization Metrics for Phase Change Memory (PCM) Cell Architectures,

    M. Boniardi et al., “Optimization Metrics for Phase Change Memory (PCM) Cell Architectures,” in IEEE Electron Devices Meeting (IEDM), 2014

    2014

  52. [68]

    Phase-change heterostructure enables ultralow noise and drift for memory operation,

    K. Ding et al., “Phase-change heterostructure enables ultralow noise and drift for memory operation,” Science, vol. 366, no. 6462, pp. 210–215, Oct. 2019, doi: 10.1126/science.aay0291

    2019 doi

  53. [70]

    Temperature-Dependent Contact Resistance to Nonvolatile Memory Materials,

    S. Deshmukh et al., “Temperature-Dependent Contact Resistance to Nonvolatile Memory Materials,” IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 3816–3821, Sep. 2019, doi: 10.1109/TED.2019.2929736

    2019 doi

  54. [71]

    Electrical resistivity of liquid Ge2Sb2Te5 based on thin-film and nanoscale device measurements,

    K. Cil et al., “Electrical resistivity of liquid Ge2Sb2Te5 based on thin-film and nanoscale device measurements,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 433– 437, 2013, doi: 10.1109/TED.2012.2228273

    2013 doi

  55. [72]

    S. M. Sze, Y. Li, and K. K. Ng, Physics of Semiconductor Devices. Wiley-Interscience, 2006

    2006

  56. [74]

    The impact of thermal boundary resistance in phase-change memory devices,

    J. P. Reifenberg, D. L. Kencke, and K. E. Goodson, “The impact of thermal boundary resistance in phase-change memory devices,” IEEE Electron Device Letters, vol. 29, no. 10, pp. 1112–1114, 2008, doi: 10.1109/LED.2008.2003012

    2008 doi

  57. [75]

    Compact thermal model for vertical nanowire phase-change memory cells,

    I. R. Chen and E. Pop, “Compact thermal model for vertical nanowire phase-change memory cells,” IEEE Transactions on Electron Devices, vol. 56, no. 7, pp. 1523–1528, 2009, doi: 10.1109/TED.2009.2021364

    2009 doi

  58. [76]

    Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi₂Te₃ Thermoelectric Interfacial Layer,

    A. I. Khan et al., “Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi₂Te₃ Thermoelectric Interfacial Layer,” IEEE Electron Device Lett., vol. 41, no. 11, pp. 1657–1660, Nov. 2020, doi: 10.1109/LED.2020.3028271

    2020 doi

  59. [77]

    Impact of thermoelectric phenomena on phase- change memory performance metrics and scaling,

    J. Lee, M. Asheghi, and K. E. Goodson, “Impact of thermoelectric phenomena on phase- change memory performance metrics and scaling,” Nanotechnology, vol. 23, no. 20, May 2012, doi: 10.1088/0957-4484/23/20/205201

    2012 doi

  60. [78]

    Structural transformations of [formula omitted] films studied by electrical resistance measurements,

    I. Friedrich, V. Weidenhof, W. Njoroge, P. Franz, and M. Wuttig, “Structural transformations of [formula omitted] films studied by electrical resistance measurements,” Journal of Applied Physics, vol. 87, no. 9, pp. 4130–4134, May 2000, doi: 10.1063/1.373041. 34

    doi

  61. [79]

    Evidence of the Thermo-Electric Thomson Effect and Influence on the Program Conditions and Cell Optimization in Phase-Change Memory Cells,

    D. T. Castro et al., “Evidence of the Thermo-Electric Thomson Effect and Influence on the Program Conditions and Cell Optimization in Phase-Change Memory Cells,” 2007

    2007

  62. [80]

    Thermoelectric heating of Ge2Sb2 Te5 in phase change memory devices,

    D. S. Suh et al., “Thermoelectric heating of Ge2Sb2 Te5 in phase change memory devices,” Applied Physics Letters, vol. 96, no. 12, 2010, doi: 10.1063/1.3259649

    2010 doi

  63. [81]

    Phase purity and the thermoelectric properties of Ge 2Sb 2Te 5 films down to 25 nm thickness,

    J. Lee, T. Kodama, Y. Won, M. Asheghi, and K. E. Goodson, “Phase purity and the thermoelectric properties of Ge 2Sb 2Te 5 films down to 25 nm thickness,” Journal of Applied Physics, vol. 112, no. 1, Jul. 2012, doi: 10.1063/1.4731252

    2012 doi

  64. [82]

    Nanometer-scale temperature imaging for independent observation of Joule and Peltier effects in phase change memory devices,

    K. L. Grosse, E. Pop, and W. P. King, “Nanometer-scale temperature imaging for independent observation of Joule and Peltier effects in phase change memory devices,” Review of Scientific Instruments, vol. 85, no. 9, Sep. 2014, doi: 10.1063/1.4895715

    2014 doi

  65. [83]

    Direct observation of nanometer-scale Joule and Peltier effects in phase change memory devices,

    K. L. Grosse, F. Xiong, S. Hong, W. P. King, and E. Pop, “Direct observation of nanometer-scale Joule and Peltier effects in phase change memory devices,” Applied Physics Letters, vol. 102, no. 19, May 2013, doi: 10.1063/1.4803172

    2013 doi

  66. [85]

    Thermal boundary resistance measurements for phase-change memory devices,

    J. P. Reifenberg et al., “Thermal boundary resistance measurements for phase-change memory devices,” IEEE Electron Device Letters, vol. 31, no. 1, pp. 56–58, Jan. 2010, doi: 10.1109/LED.2009.2035139

    2010 doi

  67. [86]

    Interfacial thermal resistance: Past, present, and future,

    J. Chen, X. Xu, J. Zhou, and B. Li, “Interfacial thermal resistance: Past, present, and future,” Rev. Mod. Phys., vol. 94, no. 2, p. 025002, Apr. 2022, doi: 10.1103/RevModPhys.94.025002

    2022 doi

  68. [89]

    Interfacial phase-change memory,

    R. E. Simpson et al., “Interfacial phase-change memory,” Nature Nanotechnology, vol. 6, no. 8, pp. 501–505, 2011, doi: 10.1038/nnano.2011.96

    2011 doi

  69. [90]

    Uncovering Thermal and Electrical Properties of Sb 2 Te 3 /GeTe Superlattice Films,

    H. Kwon, A. I. Khan, C. Perez, M. Asheghi, E. Pop, and K. E. Goodson, “Uncovering Thermal and Electrical Properties of Sb 2 Te 3 /GeTe Superlattice Films,” Nano Lett., vol. 21, no. 14, pp. 5984–5990, Jul. 2021, doi: 10.1021/acs.nanolett.1c00947

    2021 doi

  70. [91]

    Understanding the switching mechanism of interfacial phase change memory,

    K. L. Okabe et al., “Understanding the switching mechanism of interfacial phase change memory,” Journal of Applied Physics, vol. 125, no. 18, May 2019, doi: 10.1063/1.5093907

    2019 doi

  71. [92]

    Improvement of Phase‐Change Memory Performance by Means of GeTe/Sb 2 Te 3 Superlattices,

    D. Térébénec et al., “Improvement of Phase‐Change Memory Performance by Means of GeTe/Sb 2 Te 3 Superlattices,” Physica Rapid Research Ltrs, vol. 15, no. 3, p. 2000538, Mar. 2021, doi: 10.1002/pssr.202000538

    2021 doi

  72. [93]

    Probing the Melting Transitions in Phase-Change Superlattices via Thin Film Nanocalorimetry,

    J. Zhao et al., “Probing the Melting Transitions in Phase-Change Superlattices via Thin Film Nanocalorimetry,” Nano Lett., vol. 23, no. 10, pp. 4587–4594, May 2023, doi: 10.1021/acs.nanolett.3c01049

    2023 doi

  73. [94]

    Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance,

    A. I. Khan et al., “Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance,” Nano Letters, vol. 22, no. 15, pp. 6285–6291, Aug. 2022, doi: 10.1021/acs.nanolett.2c01869. 35

    2022 doi

  74. [95]

    Understanding Interface-Controlled Resistance Drift in Superlattice Phase Change Memory,

    X. Wu et al., “Understanding Interface-Controlled Resistance Drift in Superlattice Phase Change Memory,” IEEE Electron Device Letters, vol. 43, no. 10, pp. 1669–1672, Oct. 2022, doi: 10.1109/LED.2022.3203971

    2022 doi

  75. [96]

    First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (-3 MA/cm2) and Low Resistance Drift (-0.002 at 105°C),

    A. Intisar Khan et al., “First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (-3 MA/cm2) and Low Resistance Drift (-0.002 at 105°C),” in Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and El...

    2022 doi

  76. [97]

    Energy Efficient Neuro-Inspired Phase–Change Memory Based on Ge4Sb6Te7 as a Novel Epitaxial Nanocomposite,

    A. I. Khan et al., “Energy Efficient Neuro-Inspired Phase–Change Memory Based on Ge4Sb6Te7 as a Novel Epitaxial Nanocomposite,” Advanced Materials, vol. 35, no. 30, Jul. 2023, doi: 10.1002/adma.202300107

    2023 doi

  77. [103]

    PHASE-CHANGE MEMORY Ultralow-switching current density multilevel phase-change memory on a flexible substrate

    A. Intisar Khan et al., “PHASE-CHANGE MEMORY Ultralow-switching current density multilevel phase-change memory on a flexible substrate.” [Online]. Available: https://www.science.org

  78. [104]

    Low RESET Current Mushroom‐Cell Phase‐Change Memory Using Fiber‐Textured Homostructure GeSbTe on Highly Oriented Seed Layer,

    G. M. Cohen et al., “Low RESET Current Mushroom‐Cell Phase‐Change Memory Using Fiber‐Textured Homostructure GeSbTe on Highly Oriented Seed Layer,” physica status solidi (RRL) – Rapid Research Letters, Jun. 2024, doi: 10.1002/pssr.202300426

    2024 doi

  79. [105]

    Fast phase transitions induced by picosecond electrical pulses on phase change memory cells,

    W. J. Wang et al., “Fast phase transitions induced by picosecond electrical pulses on phase change memory cells,” Applied Physics Letters, vol. 93, no. 4, 2008, doi: 10.1063/1.2963196

    2008 doi

  80. [106]

    Nanoscaling of phase change memory cells for high speed memory applications,

    W. Wang et al., “Nanoscaling of phase change memory cells for high speed memory applications,” Japanese Journal of Applied Physics, vol. 48, no. 4 PART 2, Apr. 2009, doi: 10.1143/JJAP.48.04C060

    2009 doi

  81. [107]

    Breaking the Speed Limits of Phase-Change Memory,

    D. Loke et al., “Breaking the Speed Limits of Phase-Change Memory,” Science, vol. 336, no. 6088, pp. 1561–1566, Jun. 2012, doi: 10.1126/science.1220119

    2012 doi

  82. [108]

    Electric field induced crystallization in phase-change materials for memory applications,

    K. Kohary and C. D. Wright, “Electric field induced crystallization in phase-change materials for memory applications,” Applied Physics Letters, vol. 98, no. 22, May 2011, doi: 10.1063/1.3595408. 36

    2011 doi

  83. [109]

    Scandium doped Ge2Sb2Te5 for high-speed and low-power-consumption phase change memory,

    Y. Wang et al., “Scandium doped Ge2Sb2Te5 for high-speed and low-power-consumption phase change memory,” Applied Physics Letters, vol. 112, no. 13, Mar. 2018, doi: 10.1063/1.5012872

    2018 doi

  84. [110]

    Impact of Ge-Sb-Te compound engineering on the set operation performance in phase-change memories,

    M. Boniardi et al., “Impact of Ge-Sb-Te compound engineering on the set operation performance in phase-change memories,” in Solid-State Electronics, Apr. 2011, pp. 11–

    2011

  85. [111]

    doi: 10.1016/j.sse.2010.11.033

    2010 doi

  86. [113]

    PHASE-CHANGE MEMORY Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing,

    F. Rao et al., “PHASE-CHANGE MEMORY Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing,” 2017. [Online]. Available: https://www.science.org

    2017

  87. [114]

    650 ps SET speed in GE 2 SB 2 TE 5 phase change memory induced by TIO 2 dielectric crystal plane,

    R. Zhao et al., “650 ps SET speed in GE 2 SB 2 TE 5 phase change memory induced by TIO 2 dielectric crystal plane,” InfoMat, p. e12598, Jul. 2024, doi: 10.1002/inf2.12598

    2024 doi

  88. [117]

    A study on OTS-PCM pillar cell for 3-d stackable memory,

    W. C. Chien et al., “A study on OTS-PCM pillar cell for 3-d stackable memory,” IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 5172–5179, Nov. 2018, doi: 10.1109/TED.2018.2871197

    2018 doi

  89. [118]

    Access devices for 3D crosspoint memory,

    G. W. Burr et al., “Access devices for 3D crosspoint memory,” Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 32, no. 4, p. 040802, Jul. 2014, doi: 10.1116/1.4889999

    2014 doi

  90. [119]

    Polarity-Induced Threshold Voltage Shift in Ovonic Threshold Switching Chalcogenides and the Impact of Material Composition,

    T. Ravsher et al., “Polarity-Induced Threshold Voltage Shift in Ovonic Threshold Switching Chalcogenides and the Impact of Material Composition,” Physica Status Solidi - Rapid Research Letters, vol. 17, no. 8, Aug. 2023, doi: 10.1002/pssr.202200417

    2023 doi

  91. [120]

    Self-Rectifying Memory Cell Based on SiGeAsSe Ovonic Threshold Switch,

    T. Ravsher et al., “Self-Rectifying Memory Cell Based on SiGeAsSe Ovonic Threshold Switch,” IEEE Trans. Electron Devices, vol. 70, no. 5, pp. 2276–2281, May 2023, doi: 10.1109/TED.2023.3252491

    2023 doi

  92. [121]

    Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory,

    T. Ravsher et al., “Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory,” in 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA: IEEE, Apr. 2024, p. 7A.5-1-7A.5-9. doi: 10.1109/IRPS48228.2024.10529450

    2024 doi

  93. [122]

    Polarity-dependent threshold voltage shift in ovonic threshold switches: Challenges and opportunities,

    T. Ravsher et al., “Polarity-dependent threshold voltage shift in ovonic threshold switches: Challenges and opportunities,” in 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA: IEEE, Dec. 2021, p. 28.4.1-28.4.4. doi: 10.1109/IEDM19574.2021.9720649

    2021 doi

  94. [123]

    Selector Only Memory: Exploring Atomic Mechanisms from First- Principles,

    S. Clima et al., “Selector Only Memory: Exploring Atomic Mechanisms from First- Principles,” in 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA: IEEE, Dec. 2024, pp. 1–4. doi: 10.1109/IEDM50854.2024.10873555

    2024 doi

  95. [124]

    3D cross-point phase-change memory for storage-class memory,

    H.-Y. Cheng, F. Carta, W.-C. Chien, H.-L. Lung, and M. J. BrightSky, “3D cross-point phase-change memory for storage-class memory,” J. Phys. D: Appl. Phys., vol. 52, no. 47, p. 473002, Nov. 2019, doi: 10.1088/1361-6463/ab39a0. 37

    2019 doi

  96. [125]

    Evolution of Phase-Change Memory for the Storage-Class Memory and Beyond,

    T. Kim and S. Lee, “Evolution of Phase-Change Memory for the Storage-Class Memory and Beyond,” IEEE Trans. Electron Devices, vol. 67, no. 4, pp. 1394–1406, Apr. 2020, doi: 10.1109/TED.2020.2964640

    2020 doi

  97. [126]

    SpecPCM: A Low-Power PCM-Based In-Memory Computing Accelerator for Full-Stack Mass Spectrometry Analysis,

    K. Fan et al., “SpecPCM: A Low-Power PCM-Based In-Memory Computing Accelerator for Full-Stack Mass Spectrometry Analysis,” IEEE J. Explor. Solid-State Comput. Devices Circuits, vol. 10, pp. 161–169, 2024, doi: 10.1109/JXCDC.2024.3498837

    2024 doi

  98. [127]

    Performance-based comparative study of existing and emerging non-volatile memories: a review,

    P. Jangra and M. Duhan, “Performance-based comparative study of existing and emerging non-volatile memories: a review,” J Opt, vol. 52, no. 4, pp. 2395–2409, Dec. 2023, doi: 10.1007/s12596-022-01058-w

    2023 doi

  99. [128]

    Multilevel phase-change memory,

    N. Papandreou et al., “Multilevel phase-change memory,” in 2010 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece: IEEE, Dec. 2010, pp. 1017–1020. doi: 10.1109/ICECS.2010.5724687

    2010 doi

  100. [129]

    Device, circuit and system-level analysis of noise in multi-bit phase- change memory,

    G. F. Close et al., “Device, circuit and system-level analysis of noise in multi-bit phase- change memory,” in IEEE International Electron Devices Meeting (IEDM), 2010

    2010

  101. [130]

    Low- field amorphous state resistance and threshold voltage drift in chalcogenide materials,

    A. Pirovano, A. L. Lacaita, F. Pellizzer, S. A. Kostylev, A. Benvenuti, and R. Bez, “Low- field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Transactions on Electron Devices (TED), vol. 51, no. 5, pp. 714–719, May 2004, doi: 10.1109/T...

    2004 doi

  102. [131]

    Aging mechanisms in amorphous phase-change materials,

    J. Y. Raty et al., “Aging mechanisms in amorphous phase-change materials,” Nature Communications, vol. 6, Jun. 2015, doi: 10.1038/ncomms8467. Supporting Information | Nir-Harwood et al. 1 Supporting Information Energy and Scaling Limits of Phase-Change Memory Rivka-Galya Nir-H...

    2015 doi

  103. [132]

    180 GST 225 µ-trench 36 1.5 600 40 20 1 200 100

  104. [133]

    180 GST 225 µ-trench 32.4 2.7 300 40 90 2 300 150

  105. [134]

    180 GST 225 --- 10.8 1.8 600 10 64.8 1.8 200 180

  106. [135]

    180 GST doped mushroom 15 1.5 100 100 36 1.2 100 300

  107. [136]

    3 GST 225 nanowire 0.3 3 5 20 0.45 3 1 150

  108. [137]

    1.7 GST 225 nanowire 0.08 --- 1.6 30 0.03 --- 0.1 300

  109. [138]

    50 SL mushroom 2.89 0.7 55 75 3.6 0.6 50 120

  110. [139]

    90 GST 225 µ-trench 22.4 1.4 400 40 20 1 200 100 Supporting Information | Nir-Harwood et al. 7

  111. [140]

    80 GST 225 Dash confined 51.2 3.2 160 100 252 4.2 60 1000

  112. [141]

    100 GST 225 Dash confined 18.25 --- 94 55 --- --- --- 1100

  113. [142]

    75 GST 225 confined 0.69 12.8 180 0.3

  114. [143]

    175 GST 225 confined 720 1.8 2000 200

    2000

  115. [144]

    40 SL 1.5 0.37 5 200 20 0.91 0.65 40 35

  116. [145]

    80 SL mushroom 2.7 0.9 300 10

  117. [146]

    190 SL mushroom 9.1 1.3 700 10

  118. [147]

    1.8 GST 225 nanowire 0.21 15 1.4 10 --- 5.28 0.5 ---

  119. [148]

    60 GeTe mushroom 1.8 0.6 1200 2.5 7.2 1 900 8 [34]* 5.5 SiTe x mushroom 9 --- 60 20 2.63 --- 5 150

  120. [149]

    Supporting Information | Nir-Harwood et al

    100 SL 6 20 [36]* 150 GST 225 mushroom 20 0.8 500 50 --- --- --- 2000 *This data is not shown in the scaling trend figures in the main text (Figure 14-15) because it is filamentary and the critical dimension (D) is independent of the bottom electrode size. Supporting Informati...

    2000

  121. [150]

    Simple Formulas for Two-and Three-Dimensional Capacitances,

    T. Sakurai and K. Tamaru, “Simple Formulas for Two-and Three-Dimensional Capacitances,” Trans. Electron Devices, vol. 30, no. 2, 1983

    1983

  122. [151]

    Drift of Schottky Barrier Height in Phase Change Materials,

    R.-G. Nir-Harwood et al., “Drift of Schottky Barrier Height in Phase Change Materials,” ACS Nano, Mar. 2024, doi: 10.1021/acsnano.3c11019

    2024 doi

  123. [152]

    Specific contact resistance of phase change materials to metal electrodes,

    D. Roy, M. A. A. Zandt, and R. A. M. Wolters, “Specific contact resistance of phase change materials to metal electrodes,” IEEE Electron Device Lett., vol. 31, no. 11, pp. 1293–1295, Nov. 2010, doi: 10.1109/LED.2010.2066256

    2010 doi

  124. [153]

    Contact resistance measurement of Ge 2Sb 2Te 5 phase change material to TiN electrode by spacer etched nanowire,

    R. Huang et al., “Contact resistance measurement of Ge 2Sb 2Te 5 phase change material to TiN electrode by spacer etched nanowire,” Semicond. Sci. Technol., vol. 29, no. 9, Sep. 2014, doi: 10.1088/0268-1242/29/9/095003

    2014 doi

  125. [154]

    Contact resistivity of amorphous and crystalline GeCu2Te3 to W electrode for phase change random access memory,

    S. Shindo, Y. Sutou, J. Koike, Y. Saito, and Y. H. Song, “Contact resistivity of amorphous and crystalline GeCu2Te3 to W electrode for phase change random access memory,” Mater. Sci. Semicond. Process., vol. 47, pp. 1–6, Jun. 2016, doi: 10.1016/j.mssp.2016.02.006

    2016 doi

  126. [155]

    High temperature electrical resistivity and Seebeck coefficient of Ge2Sb2Te5 thin films,

    L. Adnane et al., “High temperature electrical resistivity and Seebeck coefficient of Ge2Sb2Te5 thin films,” J. Appl. Phys., vol. 122, no. 12, Sep. 2017, doi: 10.1063/1.4996218

    2017 doi

  127. [156]

    Effect of metals and annealing on specific contact resistivity of GeTe/metal contacts,

    E. K. Chua, R. Zhao, L. P. Shi, T. C. Chong, T. E. Schlesinger, and J. A. Bain, “Effect of metals and annealing on specific contact resistivity of GeTe/metal contacts,” Appl. Phys. Lett., vol. 101, no. 1, Jul. 2012, doi: 10.1063/1.4732787

    2012 doi

  128. [157]

    Investigation of SET and RESET States Resistance in Ohmic Regime for Phase-Change Memory,

    S. D. Savransky and I. V. Karpov, “Investigation of SET and RESET States Resistance in Ohmic Regime for Phase-Change Memory,” 2008

    2008

  129. [158]

    Thermal resistance at Al-Ge2Sb2Te5 interface,

    J. L. Battaglia et al., “Thermal resistance at Al-Ge2Sb2Te5 interface,” Appl. Phys. Lett., vol. 102, no. 18, May 2013, doi: 10.1063/1.4803923

    2013 doi

  130. [159]

    Decoupled Thermal Resistances of Phase Change Material and Their Impact on PCM Devices,

    J. Lee et al., “Decoupled Thermal Resistances of Phase Change Material and Their Impact on PCM Devices,” in Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 12th IEEE Intersociety Conference, IEEE, 2010

    2010

  131. [160]

    Spatially Resolved Thermometry of Resistive Memory Devices,

    E. Yalon et al., “Spatially Resolved Thermometry of Resistive Memory Devices,” Sci. Rep., vol. 7, no. 1, Dec. 2017, doi: 10.1038/s41598-017-14498-3

    2017 doi

  132. [161]

    Thermal characterization of the SiO2-Ge2Sb 2Te5 interface from room temperature up to 400 °c,

    J. L. Battaglia et al., “Thermal characterization of the SiO2-Ge2Sb 2Te5 interface from room temperature up to 400 °c,” J. Appl. Phys., vol. 107, no. 4, 2010, doi: 10.1063/1.3284084

    2010 doi

  133. [162]

    Phonon and electron transport through Ge2Sb2Te 5 films and interfaces bounded by metals,

    J. Lee, E. Bozorg-Grayeli, S. Kim, M. Asheghi, H. S. Philip Wong, and K. E. Goodson, “Phonon and electron transport through Ge2Sb2Te 5 films and interfaces bounded by metals,” Appl. Phys. Lett., vol. 102, no. 19, May 2013, doi: 10.1063/1.4807141

    2013 doi

  134. [163]

    Ab initio calculation of thermal boundary resistance at the interface of metals with GeTe, In 3 SbTe 2 and In 2 GeTe 3 phase change compounds,

    S. Gabardi, D. Campi, and M. Bernasconi, “Ab initio calculation of thermal boundary resistance at the interface of metals with GeTe, In 3 SbTe 2 and In 2 GeTe 3 phase change compounds,” J. Comput. Electron., vol. 16, no. 4, pp. 1003–1010, Dec. 2017, doi: 10.1007/s10825-017-1097-1

    2017 doi

  135. [164]

    Lower current operation of phase change memory cell with a thin Ti O2 layer,

    C. Xu, Z. Song, B. Liu, S. Feng, and B. Chen, “Lower current operation of phase change memory cell with a thin Ti O2 layer,” Appl. Phys. Lett., vol. 92, no. 6, 2008, doi: 10.1063/1.2841655

    2008 doi

  136. [165]

    Electron-phonon interaction and thermal boundary resistance at the interfaces of Ge2Sb2Te5 with metals and dielectrics,

    D. Campi, E. Baldi, G. Graceffa, G. C. Sosso, and M. Bernasconi, “Electron-phonon interaction and thermal boundary resistance at the interfaces of Ge2Sb2Te5 with metals and dielectrics,” J. Phys. Condens. Matter, vol. 27, no. 17, May 2015, doi: 10.1088/0953- 8984/27/17/175009

    2015 doi

  137. [166]

    W. M. Rohsenow, J. P. (James P. ) Hartnett, and Y. I. Cho, Handbook of heat transfer. McGraw-Hill, 1998

    1998

  138. [167]

    Novel pTrench Phase-Change Memory Cell for Embedded and Stand- Alone Non-Volatile Memory Applications

    F. Pellizzer et al., “Novel pTrench Phase-Change Memory Cell for Embedded and Stand- Alone Non-Volatile Memory Applications.”

  139. [168]

    An 8Mb Demonstrator for High-Density 1.8V Phase-Change Memories,

    F. Bedeschi et al., “An 8Mb Demonstrator for High-Density 1.8V Phase-Change Memories,” Agrate

  140. [169]

    Enhanced write performance of a 64-mb phase-change random access memory,

    H. R. Oh et al., “Enhanced write performance of a 64-mb phase-change random access memory,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 122–126, Jan. 2006, doi: 10.1109/JSSC.2005.859016. Supporting Information | Nir-Harwood et al. 9

    2006 doi

  141. [170]

    Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories,

    Y. Matsui et al., “Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories,” in International Electron Devices Meeting (IEDM), 2006

    2006

  142. [171]

    Low-Power Switching of Phase-Change Materials with Carbon Nanotube Electrodes,

    F. Xiong et al., “Low-Power Switching of Phase-Change Materials with Carbon Nanotube Electrodes,” Tech. Dig. - Int. Electron Devices Meet. IEDM, vol. 332, no. 6029, 2011, doi: 10.1109/IEDM.2006.346910

    2011 doi

  143. [172]

    Self-aligned nanotube-nanowire phase change memory,

    F. Xiong et al., “Self-aligned nanotube-nanowire phase change memory,” Nano Lett., vol. 13, no. 2, pp. 464–469, Feb. 2013, doi: 10.1021/nl3038097

    2013 doi

  144. [173]

    55-μA GexTe1-x/Sb2Te3 superlattice topological-switching random access memory (TRAM) and study of atomic arrangement in Ge-Te and Sb-Te structures,

    N. Takaura et al., “55-μA GexTe1-x/Sb2Te3 superlattice topological-switching random access memory (TRAM) and study of atomic arrangement in Ge-Te and Sb-Te structures,” in IEEE International Electron Devices Meeting (IEDM), 2014

    2014

  145. [174]

    A 90nm Phase Change Memory Technology for Stand-Alone Non- Volatile Memory Applications,

    F. Pellizzer et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non- Volatile Memory Applications,” 2006

    2006

  146. [175]

    Cross-point phase change memory with 4F^2 cell size driven by low- contact-resistivity poly-Si diode,

    Y. Sasago et al., “Cross-point phase change memory with 4F^2 cell size driven by low- contact-resistivity poly-Si diode,” in Symposium on VLSI Technology, 2009

    2009

  147. [176]

    Dual- Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory,

    S. W. Fong, C. M. Neumann, E. Yalon, M. M. Rojo, E. Pop, and H. S. P. Wong, “Dual- Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory,” IEEE Trans. Electron Devices, vol. 64, no. 11, pp. 4496–4502, Nov. 2017, doi: 10.1109/TED.2017.2756071

    2017 doi

  148. [177]

    Uncovering Phase Change Memory Energy Limits by Sub-Nanosecond Probing of Power Dissipation Dynamics,

    K. Stern et al., “Uncovering Phase Change Memory Energy Limits by Sub-Nanosecond Probing of Power Dissipation Dynamics,” Adv. Electron. Mater., vol. 7, no. 8, Aug. 2021, doi: 10.1002/aelm.202100217

    2021 doi

  149. [178]

    Crystallization dynamics probed by transient resistance in phase change memory cells,

    E. Ordan, R. G. Nir-Harwood, M. M. Dahan, Y. Keller, and E. Yalon, “Crystallization dynamics probed by transient resistance in phase change memory cells,” J. Appl. Phys., vol. 135, no. 20, May 2024, doi: 10.1063/5.0202152

    2024 doi

  150. [179]

    Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory,

    X. Wu et al., “Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory,” Nat. Commun., vol. 15, no. 1, Dec. 2024, doi: 10.1038/s41467-023-42792-4

    2024 doi

  151. [180]

    Phase-change heterostructure enables ultralow noise and drift for memory operation,

    K. Ding et al., “Phase-change heterostructure enables ultralow noise and drift for memory operation,” 2019. [Online]. Available: https://www.science.org

    2019

  152. [181]

    An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes,

    J. Liang, R. G. D. Jeyasingh, H. Y. Chen, and H. S. P. Wong, “An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1155–1163, Apr. 2012, doi: 10.1109/TED.2012.2184542

    2012 doi

  153. [182]

    Nanosecond switching in GeTe phase change memory cells,

    G. Bruns et al., “Nanosecond switching in GeTe phase change memory cells,” Appl. Phys. Lett., vol. 95, no. 4, 2009, doi: 10.1063/1.3191670

    2009 doi

  154. [183]

    Phase-change memory via a phase-changeable self-confined nano- filament,

    S.-O. Park et al., “Phase-change memory via a phase-changeable self-confined nano- filament,” Nature, Apr. 2024, doi: 10.1038/s41586-024-07230-5

    2024 doi

  155. [184]

    Electro-Thermal Confinement Enables Improved Superlattice Phase Change Memory,

    A. I. Khan et al., “Electro-Thermal Confinement Enables Improved Superlattice Phase Change Memory,” IEEE Electron Device Lett., vol. 43, no. 2, pp. 204–207, Feb. 2022, doi: 10.1109/LED.2021.3133906

    2022 doi

  156. [185]

    Engineering thermal and electrical interface properties of phase change memory with monolayer MoS 2,

    C. M. Neumann, K. L. Okabe, E. Yalon, R. W. Grady, H. S. P. Wong, and E. Pop, “Engineering thermal and electrical interface properties of phase change memory with monolayer MoS 2,” Appl. Phys. Lett., vol. 114, no. 8, Feb. 2019, doi: 10.1063/1.5080959

    2019 doi

Pith tools

Reviewed June 29, 2026 · model on record in the stance chip above.