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REVIEW 2 major objections 4 minor 55 references

Extreme-ultraviolet lithography can pattern silicon spin qubits whose operation fidelities reach 99.9% for single-qubit gates and 99.1% for two-qubit gates.

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2026-08-02 06:08 UTC pith:SC72SJ2D

load-bearing objection EUV-patterned SiMOS spin qubits with GST fidelities approaching 99.9% are a real milestone, but the wafer-scale uniformity evidence and the qubit benchmarks come from different geometries, so the manufacturing-readiness claim is under-supported. the 2 major comments →

arxiv 2607.13121 v1 pith:SC72SJ2D submitted 2026-07-14 cond-mat.mes-hall quant-ph

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

Thomas Van Caekenberghe , Paul Steinacker , Bart Raes , Sofie Beyne , Clement Godfrin , Jacques Van Damme , Sylvain Baudot , Arne Loenders
show 26 more authors
Gulzat Jaliel Stefan Kubicek Johan De Backer Yannick Hermans Sugandha Sharma Shuchi Kaushik Yuchao Jiang Yosuke Shimura Roger Loo Vukan Levajac Kristof Moors George Simion Florian K. Unseld Ensar Vahapoglu Ajit Dash Tuomo Tanttu Chris C. Escott Chih Hwan Yang Andre Saraiva Arne Laucht Wee Han Lim Nard Dumoulin Stuyck Massimo Mongillo Danny Wan Andrew S. Dzurak Kristiaan De Greve
This is my paper
classification cond-mat.mes-hall quant-ph PACS 85.35.Gv03.67.Lx
keywords silicon spin qubitsEUV lithographySiMOS quantum dotsgate set tomographyquantum-dot uniformityexchange coupling300 mm wafer fabricationsemiconductor quantum computing
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper sets out to show that extreme-ultraviolet (EUV) lithography, the parallel exposure method used in advanced chip manufacturing, can replace electron-beam writing for making silicon metal-oxide-semiconductor (SiMOS) spin qubits. It reports that a full 300 mm wafer of triple-quantum-dot devices passed room-temperature leakage screening, with sub-nanometer gate-dimension control, and that two devices cooled to millikelvin temperatures operated as four double-dot qubit systems. Gate-set tomography on all four systems gave fidelities up to 99.8% for state preparation and measurement, 99.9% for single-qubit gates, and 99.1% for two-qubit gates, with reproducible exchange turn-on slopes of 10-13 dec V-1. If true, this removes a major obstacle to scaling silicon spin qubits beyond laboratory prototypes, because EUV exposure is high-throughput, wafer-scale, and already aligned with industrial CMOS manufacturing.

Core claim

The central claim is that EUV lithography can define SiMOS quantum-dot spin qubits with the dimensional control required for high-fidelity operation, and that this was achieved on a 300 mm pilot line. The evidence is a wafer in which all 89 dies passed room-temperature gate-to-gate leakage tests, critical dimensions varied by less than 1 nm, and gate-oxide thickness varied by fractions of a nanometer. Two triple-dot devices with 60 nm dot-to-dot pitch, comprising four double-dot systems, were then characterized at 10 mK. Gate-set tomography yielded SPAM fidelities up to 99.8%, single-qubit X-gate fidelities up to 99.9%, and CZ two-qubit fidelities up to 99.1%, comparable to e-beam-defined de

What carries the argument

The load-bearing object is a three-layer overlapping polysilicon gate stack patterned by single-exposure 0.33 NA EUV lithography with a metal-oxide resist. The critical dimension is the exchange gate: at 60 nm dot-to-dot pitch, the J gates are narrower than 20 nm at the Si/SiO2 interface, and their voltage response follows a reproducible exponential turn-on of 10-13 dec V-1. This uniformity, combined with ~12 nm gate-oxide thickness and 1.5 nm overlay precision, is what lets four double-dot systems reach near-threshold fidelities with similar operating points. Gate-set tomography is the benchmarking mechanism that translates this fabrication reproducibility into per-gate operation fidelities

Load-bearing premise

The load-bearing premise is that the two triple-dot devices measured at millikelvin temperatures are representative of the whole 89-die wafer; the paper does not state how they were chosen, so wafer-scale qubit yield is inferred rather than directly measured.

What would settle it

Cryogenically benchmark a random sample of dies from the same wafer with the same gate-set-tomography protocol. If a substantial fraction of the 60-80 nm-pitch devices fail to form stable double dots or yield single-qubit fidelities far below 99%, the manufacturing-readiness claim collapses. A simpler first check is to report how devices A and B were selected from the 89-die population.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • EUV becomes a viable front-end for silicon spin-qubit production, replacing serial e-beam writing with a single-exposure, high-throughput process.
  • Qubit operation fidelities approaching the surface-code threshold can be achieved without custom laboratory fabrication.
  • Uniform gate dimensions and exchange turn-on reduce calibration overhead, making automated electrostatic tune-up feasible across many devices.
  • The same process can be extended to denser architectures, with future high-NA EUV possibly enabling single-layer gate layouts.
  • Manufacturing and qubit performance become jointly optimizable: process metrics such as leakage yield and critical-dimension spread can be tracked at wafer scale.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A natural extension the authors do not state: if the two devices were drawn at random from the wafer, the same uniformity arguments would support qubit-level yield across the 89-die population; cryogenic testing of additional random dies would confirm this.
  • The consistent exchange turn-on suggests shared operating-voltage patterns could work across a die, which would ease automated tune-up and move the field closer to shared-control crossbar architectures.
  • As fabrication uniformity improves, the effective bottleneck shifts from making qubits to measuring them; multiplexed or wafer-level cryogenic probing would be the next capability to develop.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The manuscript reports a 300 mm pilot-line fabrication of SiMOS quantum-dot spin qubits using extreme-ultraviolet (EUV) lithography. The authors present wafer-scale room-temperature gate-to-gate leakage yield (100% for the targeted 80 nm-pitch triple-dot design), capacitance-equivalent oxide thickness uniformity across three gate layers, sub-nanometer critical-dimension control (σ = 0.8 nm for plunger-to-plunger spacing), and overlay control (σ = 1.5 nm for GL2–GL3). They then characterize two 60 nm-pitch triple-dot devices at 10 mK, operating each as two double-dot systems, and perform gate-set tomography (GST) to report single-qubit X-gate fidelities up to 99.9%, CZ fidelities up to 99.1%, and SPAM fidelities up to 99.8%, with exchange turn-on slopes of 10–13 dec/V. On this basis they claim EUV lithography is a viable manufacturing technology for SiMOS spin qubits.

Significance. The result is significant because it is, to my knowledge, the first demonstration of high-fidelity SiMOS spin qubits patterned by EUV lithography, a technology with throughput and overlay advantages over e-beam. The use of GST with reported 95% confidence intervals is a strength, as is the wafer-scale metrology. The main limitation is that the process-level claims rest on two cryogenically characterized devices, and the wafer-scale uniformity data are for a different (80 nm) pitch than the qubit geometry (60 nm).

major comments (2)
  1. [FABRICATION UNIFORMITY / Fig. 2] The manufacturing-readiness claim is load-bearing, but the wafer-scale yield and uniformity data (Fig. 2a–d) are explicitly for the targeted 80 nm dot-to-dot-pitch design. The qubit devices are 'two more aggressively scaled 60 nm-pitch triple-quantum-dot devices fabricated on the same wafer' (QUBIT BENCHMARKING). No room-temperature leakage yield, CD/overlay statistics, or other screening data are reported for the 60 nm geometry. Since 60 nm pitch is a different and more challenging variant, the 80 nm metrics do not establish wafer-scale manufacturability of the actual qubit architecture. Please either provide equivalent data for the 60 nm design or revise the manufacturing claim to reflect the scope of the evidence.
  2. [QUBIT BENCHMARKING] The paper does not state how devices A and B were selected for cryogenic measurement. Only two devices (four double-dot systems) are characterized. Without a defined selection rule, it is not possible to assess whether the reported fidelities are representative of the 60 nm-pitch population or are the result of favorable selection. This is critical because the conclusion generalizes from 'two triple-dot devices' to a process-level statement. Please state the selection criteria (e.g., sequential from a fixed location, random, best-of) and, if possible, provide room-temperature screening or yield data for the 60 nm devices on the same wafer.
minor comments (4)
  1. [Author list] The first author's name appears as 'Thomas V an Caekenberghe' with a spurious space; please fix the formatting.
  2. [Fig. 2b caption] The phrase 'Theinsetshows' should read 'The inset shows'.
  3. [Abstract / Fig. 4e] The unit for exchange controllability is written inconsistently as 'dec/V' in the abstract and 'dec V^{-1}' in the main text; harmonize.
  4. [DISCUSSION] The phrase 'fault-tolerance threshold commonly associated with the surface error correction code' is vague; specify a concrete threshold value or cite the specific estimate used.

Circularity Check

0 steps flagged

No circularity found: reported fidelities are measured by GST, not derived from fitted inputs, and self-citations are methodological rather than load-bearing.

full rationale

The paper is an experimental demonstration, not a derivation, so there is no equation-level chain in which an output reduces to an input by construction. The central claim, that EUV-fabricated SiMOS spin qubits achieve high fidelities, is supported by gate set tomography (GST), an external and self-contained benchmarking protocol. The GST fidelities in Tables I and II are measurement outcomes, not predictions obtained from parameters fitted to those same fidelities. The exchange controllability of 11.3(2.6) dec/V is obtained by fitting the exchange interaction as a function of gate voltage (Fig. 4e), but this is a descriptive characterization of the device response; it is not used to derive the qubit fidelities, and no fitted quantity is renamed as a prediction. The wafer-scale uniformity data (100% leakage yield, dpp sigma = 0.8 nm, overlay sigma = 1.5 nm) are reported for the 80 nm-pitch design, while the qubit devices are 60 nm-pitch variants; this is a potential representativeness or sampling gap in supporting the manufacturing-readiness claim, but it is not circularity because the paper does not claim that the 80 nm metrics logically force the 60 nm fidelities. The self-citations (e.g., refs. 39, 43, 45, 41) provide process-flow details, real-time feedback protocols, and prior e-beam benchmarks; they are methodological support and comparison, not an invoked uniqueness theorem or an ansatz that carries the central result. The device fidelities are independently measured against an external benchmark, and no specific reduction from output to input can be exhibited. Therefore, no significant circularity is present.

Axiom & Free-Parameter Ledger

1 free parameters · 4 axioms · 0 invented entities

The central claims rest on measurement assumptions rather than mathematical derivations. The only fitted quantitative input is the exchange controllability slope. No new physical entities are introduced.

free parameters (1)
  • Exchange controllability slope b = 11.3(2.6) dec/V
    Extracted from exponential fits J_exchange = a exp(b V_J) to measured exchange curves (Fig. 4e). It is a descriptive uniformity metric, not a predictive constant, but the paper's uniformity claim depends on its reproducibility across four systems.
axioms (4)
  • domain assumption GST's Markovian/stationary noise model accurately describes these devices; non-Markovian noise would bias reported gate fidelities.
    Invoked in the 'Qubit benchmarking' section where GST fidelities are reported; standard assumption of gate set tomography.
  • domain assumption Pauli spin blockade readout at the (1,3)-(0,4) transition faithfully maps spin parity to charge state with negligible leakage.
    Used for all SPAM and gate fidelity measurements; readout errors are folded into reported SPAM fidelity.
  • ad hoc to paper The two devices characterized at 10 mK (A and B) are representative of the EUV-patterned wafer population.
    The paper does not state how devices A/B were selected from the 89-die wafer; qubit-level yield is not measured, so the manufacturing-readiness claim rests on this unstated representativeness assumption.
  • domain assumption Exchange coupling between neighboring dots is controlled predominantly by the J gates and can be pulsed to implement a CZ gate without unintended crosstalk beyond GST-reported errors.
    Assumed in two-qubit gate implementation (Fig. 4 and Methods); standard for gate-defined spin qubits.

pith-pipeline@v1.3.0-alltime-deepseek · 13746 in / 11355 out tokens · 70178 ms · 2026-08-02T06:08:47.981626+00:00 · methodology

0 comments
read the original abstract

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

discussion (0)

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    (Fig. 1) between GL2 and GL3 measured after GL3 lithography. The wafer-wide standard deviation isσ= 1.5 nm. The gate etch further reduces the overlay error, with typical values of|µ|+ 3σ <3 nm [39]. were shorted. The die under test was considered to pass if no gate in any of the nine tested triple-dot devices exhibited a gate-to-gate leakage current excee...